Fast Estimation and Mitigation of Substrate Noise in Early Design Stage for Large Mixed Signal SOCs Shi-Hao Chen, Hsiung-Kai Chen, Albert Li Design Service Division, GLOBAL UNICHIP CORP., Taiwan, ROC Xiaopeng Dong, Vassilios Gerousis, Miles Zhang, Yanling Weng, Rose Li IC Design Group, Cadence Design Systems, San Jose, USA Notice of Copyright This material is protected under the copyright laws of the U.S. and other countries and any uses not in conformity with the copyright laws are prohibited. Copyright for this document is held by the creator authors and sponsoring organizations of the material, all rights reserved. This document has been submitted to, and reviewed and posted by, the editors of DAC.com. Please recycle if printed.
Page 2 of 8 ARTICLE: Early Substrate Noise Estimation Fast Estimation and Mitigation of Substrate Noise in Early Design Stage for Large Mixed Signal SOCs Shi-Hao Chen, Hsiung Kai Chen, Albert Li Design Service Division, GLOBAL UNICHIP CORP., Taiwan, ROC Xiaopeng Dong, Vassilios Gerousis, Miles Zhang, Yanling Weng, Rose Li IC Design Group, Cadence Design Systems, San Jose, USA Abstract Making devices smarter and smaller requires the ability to put the entire system on a single chip, where digital and analog design blocks are all integrated on a single chip substrate. Just as timing, die size and power must be considered and addressed in the design, the interdependence of analog and digital must also be properly handled. One of the most significant design challenges is that of signal integrity, where noise caused by digital switching inside the digital section couples through the common substrate and impacts the functionality of analog blocks [1]. It is commonly understood that sensitive analog blocks should be separated from digital blocks, with additional protection required. Modern tools insert guard rings around sensitive blocks, but this increases die size and cost. To address substrate noise coupling and mitigate the substrate noise impact to analog blocks in the early stages of design is an even more challenging task. Obviously, addressing substrate noise coupling in the prototyping stage has the potential to greatly improve quality of silicon and shorten time to market. The difficulties lie in the modeling and characterization of digital switching noise, the fast extraction of substrate, the fast propagation of substrate noise at full-chip scale, and the mitigation of substrate noise based on these analyses. This article describes a substrate analysis and mitigation flow based on the Cadence Encounter Digital Implementation (EDI) system, along with results obtained for a large mixed-signal design in TSMC 90nm process technology. The EDI substrate noise analysis capabilities afford mixed-signal designers the ability to run simulation, observe VCO noise and determine guidelines for the digital block implementation. Additional details will be presented at the 2010 DAC User Track. Index Terms Substrate noise, noise-aware floorplan guidance and mitigation, mixed-signal design prototyping.
Page 3 of 8 I. INTRODUCTION The foundation for the contribution reported in this article (and in the forthcoming 2010 DAC User Track) consists of a substrate noise-aware implementation methodology and underlying tool capabilities. Figure 1 illustrates how substrate noise is caused by digital switching inside the digital section, coupled through the common substrate to impact the functionality of analog blocks. Digital VDD in out Digital GND Analog GND N+ P+ P+ N+ N+ P+ P+ N+ N+ N-Well Digital P-Substrate Analog Figure 1: Substrate noise through common substrate. Figure 2: Substrate noise-aware implementation flow. Figure 2 shows three stages of the design flow where substrate noise analysis (SNA) can be performed. The first stage is early in the implementation, when the floorplan and power plan are ready. The second opportunity to perform SNA is after placement and routing. The third stage is after fullchip implementation has been completed, when the designer must extract the full-chip noise model and run simulation to verify whether the IP has the potential to fail. This last analysis is part of systemlevel co-simulation, in that a P/G package model is needed for accurate analysis. At the third stage, because timing and power are fixed, more detailed analysis results accurate parasitics, clean
Page 4 of 8 constraints, etc. and hence more accurate SNA results are possible. In Figure 2, if there is too large a substrate noise value after the floorplan and power planning stage, we would need to change our design in stage A to meet the design criteria. If there is a large substrate noise value after placement and routing, we can reduce this in stage A or B. And, if we have a large substrate noise value after timing and power have been closed, we can mitigate this in stage B or C. Changing the design in a later stage entails greater effort to finish (close) the design. Another available solution to fix substrate noise is to add a guard ring around sensitive analog blocks or noise sources. Although some tools exist for characterization of substrate noise, these tools are normally targeted to later design stages and used for analog IP characterization. These tools also lack the capacity to handle large mixed-signal ICs. In general, there are four issues that must be solved in order to overcome the substrate noise problem for large mixed signal ICs: 1) digital noise characterization; 2) substrate modeling and substrate noise estimation; 3) evaluation of analog IPs in the light of substrate noise; and 4) substrate noise prevention. Dynamic Rail Analysis Substrate Noise Analysis Figure 3: Substrate noise analysis step. Figure 4: Tile model correlation. The substrate noise aware implementation flow shown in Figure 3 provides solutions to all the above four issues. Dynamic rail analysis is used to compute the digital noise injection. In the early design stage, even with partial data, designers can utilize a tool such as Cadence s ERA (early rail analysis) to perform dynamic rail analysis for digital noise injection characterization. The flow also uses the concept of a tile model and a tile model pre-characterization approach. This makes substrate
Page 5 of 8 modeling and noise estimation easier to accomplish in an implementation flow. The tile model can be extracted using tools such as Cadence QRC RF, based on the foundry s process design kit (PDK). Validation against golden tools such as QRC RF using test structures has been performed, with good results. (QRC RF has been silicon-qualified on advanced process nodes at various foundries.) Figure 4 shows the quality of correlation between the tile model based analysis and QRC RF. The difference is within 2dB even through distances up to 2000um. With respect to substrate noise analysis (SNA), three major capabilities are provided. (1) The first capability is the intuitive noise contour map which helps designers to handle the many different design aspects that impact substrate noise. A substrate constraint file can help bring characterized noise tolerance information into this design flow. (2) The second capability is for floorplan guidance. In applying the substrate noise aware implementation flow at early design stage, we have demonstrated how a substrate noise contour map can be computed and used as a guide for floorplan exploration and DC source assignments. (3) The third capability involves a virtual guard ring. By exploiting the ability to estimate guard ring impact on substrate noise, we have created a technique whereby the tool is used to determine the width of a guard ring that would help to maximize the noise reduction while preserving as much chip area as possible. Beyond generating a substrate noise contour map, the tool can also provide FFT-based frequency analysis for propagated noise waveforms and noise source waveforms. Designers can relate the noise to required noise tolerance at specific frequencies. Preliminary Power Planning Power-aware DFT Power planning Power Switch Placement Planning VCD pattern Timing Window 1st Placement power analysis Auto-fixing No Meet? Yes CTS/Post-route Meet VCD pattern Timing Window 2nd power analysis Traditional Flow Simulation-free Dynamic IR Prediction Static/Transient Power Analysis No Meet? Yes Meet Decap insertion lengthy loop Decap insertion Power SwitchOpt. Power Domain Check (UPDC) CTS/Post-route Timing Optimization Figure 5: Dynamic IR prevention. Because substrate noise results are highly related to dynamic rail results, dynamic IR prevention can also help to reduce substrate noise. Reference [2] proposes a dynamic IR prevention flow to improve chip yield. Figure 5 shows a complete solution for dynamic IR prevention. II. SUMMARY OF RESULTS A large mixed-signal design based on TSMC 90nm process has been used to validate our flow and methodology. The design goal is to mitigate substrate coupling for the sensitive on-chip analog IPs, especially the PLL blocks. The design parameters that can be adjusted are floorplan, DC source location, and guard ring. The reported results are obtained using the Cadence EDI system including
Page 6 of 8 EPS and ERA for dynamic rail analysis and EDI SNA for substrate noise analysis. All results that we discuss in the following are generated for this testcase design implemented in TSMC 90nm process. Table 1 shows testcase parameters. All runtimes correspond to a 2.6GHz AMD dual-core Opteron with 16G memory. Table 1 Testcase Parameters. Process TSMC 90nm LP Die Size 3700um x 3700um Instance count 100K VDD/VSS Power/Ground Nets VDDA/VSSA VDDD/VSSD QRC RF [1] is a golden analysis tool for substrate noise. Table 2 shows that EDI SNA and QRC RF have almost the same runtime for substrate noise analysis. However, EDI SNA can handle a larger design size than QRC RF. Due to runtime (turnaround time), we do not use QRC RF for chiplevel substrate analysis. Table 2 Runtime Comparison. EDI SNA QRC RF Size 100K Cells 3.6K devices Run Time 135 minutes 120 minutes Clean room for analog block Noisy region Figure 6: Low substrate noise impact in dotted circle. (a) Max substrate Noise Value: 90.9501mV Max dynamic IR drop value: 7.69% (b) Figure 7: (a) Substrate noise analysis result; (b) dynamic rail analysis result.
Page 7 of 8 Max substrate Noise Value: 59.91mV Max dynamic IR drop value: 5.25% Add DC source (a) (b) Figure 8: (a) Substrate noise analysis result; (b) dynamic rail analysis result with addition of one DC source in dotted circle. The first set of results demonstrate the generation of substrate noise contour map for the full chip including the impact of digital package, analog ground network and analog package loading. These are based on both EPS and ERA dynamic rail analysis results for digital noise injection, and show correlated substrate noise results (see Figure 6). The SNA contour map is useful for identifying quiet areas for possible analog block placement in the floorplan stage. The second set of results demonstrates floorplan improvement to mitigate the substrate noise as well as the use of DC sources to mitigate excessive noise injection due to ground bounce. Table 3 Dynamic IR and Substrate Noise Results for Figures 7 and 8. Fig. 7 Fig. 8 Max. IR drop 7.69% 5.25% Max. Substrate Noise 90.95mV 59.91mV We see that the power plan should be taken into account, since a better dynamic rail result corresponds to a better substrate noise result. In Figure 7, the worst/best locations of substrate noise are similar to these locations identified in the dynamic rail analysis. Table 3 summarizes the dynamic IR and substrate noise results of Figure 7 and Figure 8. PLL LDO LDO PLL Min noise: 64.3mV Max noise: 72.15mV Delta noise: 7.85mV (a) Min. noise: 59.41mV Max. noise: 77.12mV Delta noise: 17.71mV (b) Figure 9: (a) SNA result with old floorplan; (b) SNA result with new floorplan.
Page 8 of 8 Enlarge virtual guard ring (a) Noise (mv) 60 50 40 30 20 The most efficient guard ring width 10 0 0 10 20 30 40 50 Width (um) (b) Enlarge virtual guard ring (c) Figure 10: (a) Substrate noise result with 100um virtual guard ring width; (b) minimum substrate noise in with different virtual guard ring width; (c) substrate noise result with 10um virtual guard ring width. Figure 9 shows the change in worst dynamic rail results after changing the design floorplan. As noted above, the worst dynamic rail result has a strong correspondence to the worst substrate noise result. We observe that changing the floorplan might not improve the substrate noise result directly if the power grid design is bad (it may hurt the dynamic rail result). Table 4 summarizes the dynamic IR and substrate noise results of Figure 9, as well as the result of Figure 10(c) discussed in the following. Table 4 Dynamic IR and Substrate Noise Results for Figure 9. Fig. 9 (a) Fig. 9 (b) Fig. 10 (c) Max. IR Drop 7.69% 8.29% 7.69% Max. Substrate Noise 72.15mV 77.12mV 17.13mV Max. Substrate Noise 90.95mV 98.68mV 90.95mV A third set of results demonstrates the use of the virtual guard ring capability for area-effective reduction of substrate noise to sensitive IPs. A set of noise reduction curves against different loadings of observation points inside the virtual guard ring helps identify the tradeoff between substrate noise reduction and preservation of chip area resource (see Figure 10). III. CONCLUSION We have described a substrate noise-aware implementation flow that can be applied at a full-chip level. Floorplan guidance is provided at the prototype stage according to a substrate noise contour map. Because substrate noise is closely related to the dynamic rail result, we can reduce substrate noise by reducing dynamic rail noise. What-if analysis obtains a substrate noise result with a virtual guard ring, allowing determination of an effective guard ring width. Further, with pre-characterized noise sensitivity of a given analog block, the SoC designer may not need to feed the noise waveform to the analog block with time-consuming SPICE simulations. REFERENCES [1] A. Afzali-Kusha, M. Nagata, N. K. Verghese and D. J. Allstot, Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation, Proceedings of the IEEE 94 (2006), pp. 2109-2138. [2] S.-H. Chen, K.-C. Chu, J.-Y. Lin and C.-H. Tsai, DFM/DFY Practices During Physical Designs for Timing, Signal Integrity, and Power, Proc. Asia and South Pacific Design Automation Conference, 2007, pp. 232-237. [3] Cadence Design Systems, Inc., Parasitic Extraction and Postlayout Verification for RF/Wireless Designs, Workshop Manual, April 2007.