Industrial Inverters Switch Mode Power Supplies (SMPS)

H. Amp Output Current IGBT Gate Drive Optocoupler Technical Data HCPL- Features. A Minimum Peak Output Current kv/µs Minimum Common Mode Rejection (CMR) at V CM = V. V Maximum Low Level Output Voltage (V OL ) Eliminates Need for Negative Gate Drive I CC = ma Maximum Supply Current Under Voltage Lock-Out Protection (UVLO) with Hysteresis Wide Operating V CC Range: to Volts ns Maximum Switching Speeds Industrial Temperature Range: - C to C Safety Approval UL Recognized - V rms for minute per UL CSA Approval VDE Approved with V IORM = V peak (Option only) Applications Isolated IGBT/MOSFET Gate Drive AC and Brushless DC Motor Drives Industrial Inverters Switch Mode Power Supplies (SMPS) Description The HCPL- consists of a GaAsP LED optically coupled to an integrated circuit with a power output stage. This optocoupler is ideally suited for driving power IGBTs and MOSFETs used in Functional Diagram A. µf bypass capacitor must be connected between pins and. N/C ANODE CATHODE N/C TRUTH TABLE SHIELD motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving IGBTs with ratings up to V/ A. For IGBTs with higher ratings, the HCPL- can be used to drive a discrete power stage which drives the IGBT gate. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. - 9-9E V CC V O V O V EE V CC - V EE V CC - V EE POSITIVE GOING NEGATIVE GOING LED (i.e., TURN-ON) (i.e., TURN-OFF) V O OFF - V - V LOW ON - V - 9. V LOW ON -. V 9. - V TRANSITION ON. - V - V HIGH

Ordering Information Specify Part Number followed by Option Number (if desired) Example HCPL-#XXX No Option = Standard DIP Package, per tube. = VDE V IORM = V peak Option, per tube. = Gull Wing Surface Mount Option, per tube. = Tape and Reel Packaging Option, per reel. Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor. OPTOCOUPLERS Package Outline Drawings Standard DIP Package 9. (.) 9.9 (.9) HP Z YYWW OPTION CODE* DATE CODE. (.9). (.). (.). (.). (.). (.) TYP. PIN ONE.9 (.) MAX.. (.) MAX. PIN ONE. (.) MAX..9 (.) MIN.. (.) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). PIN DIAGRAM *MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION V DD V DD OPTION NUMBERS AND NOT MARKED. V IN V OUT. (.). (.). (.) MAX.. (.9). (.) V IN V OUT GND GND Gull Wing Surface Mount Option 9. ±. (. ±.) PAD LOCATION (FOR REFERENCE ONLY). (.).9 (.) HP Z YYWW. ±. (. ±.). TYP. (.9) 9.9 (.) 9.9 (.9) MOLDED.9 (.). (.). (.). (.).9 (.) MAX.. (.) MAX..9 (.) MAX. 9. ±. (. ±.). ±. (. ±.). (.). (.). ±. (. ±.). (.) BSC. ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx =. xx.xxx =. LEAD COPLANARITY MAXIMUM:. (.). ±. (. ±.) NOM. -

Reflow Temperature Profile TEMPERATURE C T = C,. C/SEC T = C,. C/SEC TIME MINUTES T = C, C/SEC 9 MAXIMUM SOLDER REFLOW THERMAL PROFILE (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.) Regulatory Information The HCPL- has been approved by the following organizations: UL Recognized under UL, Component Recognition Program, File E. CSA Approved under CSA Component Acceptance Notice #, File CA. VDE (Option Only) Approved under VDE /.9 with V IORM = V peak. VDE Insulation Characteristics (Option Only) Description Symbol Characteristic Unit Installation classification per DIN VDE /.9, Table for rated mains voltage V rms I-IV for rated mains voltage V rms I-III Climatic Classification // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM Vpeak Input to Output Test Voltage, Method b* V IORM x. = V PR, % Production Test with t m = sec, V PR Vpeak Partial discharge < pc Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and Sample Test, t m = sec, V PR 9 Vpeak Partial discharge < pc Highest Allowable Overvoltage* V IOTM Vpeak (Transient Overvoltage t ini = sec) Safety Limiting Values Maximum Values Allowed in the Event of a Failure, Also See Figure, Thermal Derating Curve. Case Temperature T S C Input Current I S, INPUT ma Output Power P S, OUTPUT mw Insulation Resistance at T S, V IO = V R S 9 Ω *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, (VDE ) for a detailed description of Method a and Method b partial discharge test profiles. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. -

Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air L(). mm Measured from input terminals to output terminals, Gap (External shortest distance through air. Clearance) Minimum External L(). mm Measured from input terminals to output terminals, Tracking (External shortest distance path along body. Creepage) Minimum Internal Plastic. mm Insulation thickness between emitter and detector; Gap (Internal Clearance) also known as distance through insulation. Tracking Resistance CTI Volts DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa Material Group (DIN VDE, /9, Table ) Option - surface mount classification is Class A in accordance with CECC. OPTOCOUPLERS Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S -. C Operating Temperature T A - C Average Input Current I F(AVG) ma Peak Transient Input Current (< µs pulse width, pps) I F(TRAN). A Reverse Input Voltage V R Volts High Peak Output Current I OH(PEAK). A Low Peak Output Current I OL(PEAK). A Supply Voltage (V CC - V EE ) Volts Output Voltage V O V CC Volts Output Power Dissipation P O mw Total Power Dissipation P T 9 mw Lead Solder Temperature C for sec.,. mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage (V CC - V EE ) Volts Input Current (ON) I F(ON) ma Input Voltage (OFF) V F(OFF) -.. V Operating Temperature T A - C -

Electrical Specifications (DC) Over recommended operating conditions (T A = - to C, I F(ON) = to ma, V F(OFF) = -. to. V, V CC = to V, V EE = Ground) unless otherwise specified. Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note High Level I OH.. A V O = (V CC - V),, Output Current. A V O = (V CC - V) Low Level I OL.. A V O = (V EE. V),, Output Current. A V O = (V EE V) High Level Output V OH (V CC - ) (V CC - ) V I O = - ma,,, Voltage 9 Low Level Output V OL.. V I O = ma,, Voltage High Level Supply I CCH.. ma Output Open,, Current I F = to ma Low Level Supply I CCL.. ma Output Open, Current V F = -. to. V Threshold Input I FLH.. ma I O = ma, 9,, Current Low to High V O > V Threshold Input Voltage High to Low V FHL. V Input Forward V F... V I F = ma Voltage Temperature V F / T A -. mv/ C I F = ma Coefficient of Forward Voltage Input Reverse BV R V Ir = µa Breakdown Voltage Input Capacitance C IN pf f = MHz, V F = V UVLO Threshold V UVLO... V V O > V, I F = ma, V UVLO 9... UVLO Hysteresis UVLO HYS. * All typical values at T A = C and V CC - V EE = V, unless otherwise noted. -

Switching Specifications (AC) Over recommended operating conditions (T A = - to C, I F(ON) = to ma, V F(OFF) = -. to. V, V CC = to V, V EE = Ground) unless otherwise specified. Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Propagation Delay t PLH... µs Rg = Ω,,, Time to High Cg = nf,, Output Level f = khz,, Propagation Delay t PHL... µs Duty Cycle = % Time to Low Output Level Pulse Width PWD. µs Distortion Propagation Delay (t PHL - t PLH ) -.. µs, Difference Between PDD Any Two Parts Rise Time t r. µs Fall Time t f. µs UVLO Turn On t UVLO ON. µs Delay V O > V, I F = ma UVLO Turn Off t UVLO OFF. V O < V, I F = ma Delay Output High Level CM H kv/µs T A = C,, Common Mode I F = to ma, Transient V CM = V, Immunity V CC = V Output Low Level CM L kv/µs T A = C,, Common Mode V CM = V, Transient V F = V, Immunity V CC = V OPTOCOUPLERS *All typical values at T A = C and V CC - V EE = V, unless otherwise noted. Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output V ISO V RMS RH < %,, 9 Momentary t = min., Withstand Voltage** T A = C Resistance R I-O Ω V I-O = V DC 9 (Input - Output) Capacitance C I-O. pf f = MHz (Input - Output) LED-to-Case θ LC C/W Thermocoupler Thermal Resistance LED-to-Detector θ LD C/W located at center underside of Thermal Resistance Detector-to-Case θ DC C/W package Thermal Resistance **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or HP Application Note entitled Optocoupler Input-Output Endurance Voltage. -

Notes:. Derate linearly above C free-air temperature at a rate of. ma/ C.. Maximum pulse width = µs, maximum duty cycle =.%. This value is intended to allow for component tolerances for designs with I O peak minimum =. A. See Applications section for additional details on limiting I OH peak.. Derate linearly above C free-air temperature at a rate of. mw/ C.. Derate linearly above C free-air temperature at a rate of. mw/ C. The maximum LED junction temperature should not exceed C.. Maximum pulse width = µs, maximum duty cycle =.%.. In this test V OH is measured with a dc load current. When driving capacitive loads V OH will approach V CC as I OH approaches zero amps.. Maximum pulse width = ms, maximum duty cycle = %.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage Vrms for second (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (method b) shown in the VDE Insulation Characteristic Table, if applicable. 9. Device considered a two-terminal device: pins,,, and shorted together and pins,,, and shorted together.. The difference between t PHL and t PLH between any two HCPL- parts under the same test condition.. Pins and need to be connected to LED common.. Common mode transient immunity in the high state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in the high state (i.e., V O >. V).. Common mode transient immunity in a low state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a low state (i.e., V O <. V).. This load condition approximates the gate load of a V/A IGBT.. Pulse Width Distortion (PWD) is defined as t PHL -t PLH for any given device. (V OH V CC ) HIGH OUTPUT VOLTAGE DROP V - - - - - - I F = to ma I OUT = - ma V CC = to V V EE = V T A TEMPERATURE C I OH OUTPUT HIGH CURRENT A...... - - I F = to ma V OUT = (V CC - V) V CC = to V V EE = V T A TEMPERATURE C (V OH V CC ) OUTPUT HIGH VOLTAGE DROP V - - - - - - I F = to ma V CC = to V V EE = V... C C - C. I OH OUTPUT HIGH CURRENT A. Figure. V OH vs. Temperature. Figure. I OH vs. Temperature. Figure. V OH vs. I OH. V OL OUTPUT LOW VOLTAGE V..... - V F(OFF) = -. to. V I OUT = ma V CC = to V V EE = V - T A TEMPERATURE C I OL OUTPUT LOW CURRENT A - V F(OFF) = -. to. V V OUT =. V V CC = to V V EE = V - T A TEMPERATURE C V OL OUTPUT LOW VOLTAGE V. V F(OFF) = -. to. V V CC = to V V EE = V.. C C - C. I OL OUTPUT LOW CURRENT A. Figure. V OL vs. Temperature. Figure. I OL vs. Temperature. Figure. V OL vs. I OL. -

I CC SUPPLY CURRENT ma..... - - V CC = V V EE = V I F = ma for I CCH I F = ma for I CCL I CCH I CCL T A TEMPERATURE C I CC SUPPLY CURRENT ma... I. F = ma for I CCH I F = ma for I CCL T A = C V EE = V. I CCH I CCL V CC SUPPLY VOLTAGE V I FLH LOW TO HIGH CURRENT THRESHOLD ma - - V CC = TO V V EE = V OUTPUT = OPEN T A TEMPERATURE C OPTOCOUPLERS Figure. I CC vs. Temperature. Figure. I CC vs. V CC. Figure 9. I FLH vs. Temperature. T p PROPAGATION DELAY ns I F = ma T A = C Rg = W Cg = nf DUTY CYCLE = % f = khz V CC SUPPLY VOLTAGE V T PLH T PHL T p PROPAGATION DELAY ns V CC = V, V EE = V Rg = Ω, Cg = nf T A = C DUTY CYCLE = % f = khz T PLH T PHL I F FORWARD LED CURRENT ma T p PROPAGATION DELAY ns - I F = ma V CC = V, V EE = V Rg = Ω, Cg = nf DUTY CYCLE = % f = khz - T A TEMPERATURE C T PLH T PHL Figure. Propagation Delay vs. V CC. Figure. Propagation Delay vs. I F. Figure. Propagation Delay vs. Temperature. T p PROPAGATION DELAY ns V CC = V, V EE = V T A = C I F = ma Cg = nf DUTY CYCLE = % f = khz T PLH T PHL T p PROPAGATION DELAY ns V CC = V, V EE = V T A = C I F = ma Rg = Ω DUTY CYCLE = % f = khz T PLH T PHL V O OUTPUT VOLTAGE V Rg SERIES LOAD RESISTANCE Ω Cg LOAD CAPACITANCE nf I F FORWARD LED CURRENT ma Figure. Propagation Delay vs. Rg. Figure. Propagation Delay vs. Cg. Figure. Transfer Characteristics. -9

T A = C I F FORWARD CURRENT ma... V F I F I F = to ma. µf I OH V V CC = to V....... V F FORWARD VOLTAGE VOLTS Figure. Input Current vs. Forward Voltage. Figure. I OH Test Circuit.. µf I OL. V V CC = to V I F = to ma. µf V OH V CC = to V ma Figure. I OL Test Circuit. Figure 9. V OH Test Circuit.. µf ma. µf V OL V CC = to V I F V O > V V CC = to V Figure. V OL Test Circuit. Figure. I FLH Test Circuit.. µf I F = ma V O > V V CC Figure. UVLO Test Circuit. -9

KHz % DUTY CYCLE I F = to ma Ω. µf V O Ω V CC = to V I F t r t f 9% % OPTOCOUPLERS nf V OUT % t PLH t PHL Figure. t PLH, t PHL, t r, and t f Test Circuit and Waveforms. V CM V I F A B. µf V O V CC = V V V O t δv V CM δt = t V OH SWITCH AT A: I F = ma V O V OL V CM = V SWITCH AT B: I F = ma Figure. CMR Test Circuit and Waveforms. Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL- has a very low maximum V OL specification of. V. The HCPL- realizes this very low V OL by using a DMOS transistor with Ω (typical) on resistance in its pull down circuit. When the HCPL- is in the low state, the IGBT gate is shorted to the emitter by Rg Ω. Minimizing Rg and the lead inductance from the HCPL- to the IGBT gate and emitter (possibly by mounting the HCPL- on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL- input as this can result in unwanted coupling of transient signals into the HCPL- and degrade performance. (If the IGBT drain must be routed near the HCPL- input, then the LED should be reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-.) V Ω HCPL-. µf V CC = V HVDC Rg CONTROL INPUT Q -PHASE AC XXX OPEN COLLECTOR Q - HVDC Figure. Recommended LED Drive and Application Circuit. -9

Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses. Step : Calculate Rg Minimum from the I OL Peak Specification. The IGBT and Rg in Figure can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-. (V CC V EE - V OL ) Rg I OLPEAK (V CC V EE - V) = I OLPEAK ( V V - V) =. A =. Ω Ω The V OL value of V in the previous equation is a conservative value of V OL at the peak current of.a (see Figure ). At lower Rg values the voltage supplied by the HCPL- is not an ideal voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used V EE in the previous equation is equal to zero volts. Step : Check the HCPL- Power Dissipation and Increase Rg if Necessary. The HCPL- total power dissipation (P T ) is equal to the sum of the emitter power (P E ) and the output power (P O ): P T = P E P O P E = I F V F Duty Cycle P O = P O(BIAS) P O (SWITCHING) = I CC (V CC - V EE ) E SW (R G, Q G ) f For the circuit in Figure with I F (worst case) = ma, Rg = Ω, Max Duty Cycle = %, Qg = nc, f = khz and T A max = C: P E = ma. V. = mw P O =. ma V. µj khz = mw mw = 9 mw > mw (P O(MAX) @ C = mw C*. mw/c) V Ω HCPL-. µf V CC = V HVDC Rg CONTROL INPUT XXX OPEN COLLECTOR V EE = - V Q Q -PHASE AC - HVDC Figure. HCPL- Typical Application Circuit with Negative IGBT Gate Drive. P E Parameter I F V F Duty Cycle Description LED Current LED On Voltage Maximum LED Duty Cycle P O Parameter I CC V CC V EE E SW (Rg,Qg) f Description Supply Current Positive Supply Voltage Negative Supply Voltage Energy Dissipated in the HCPL- for each IGBT Switching Cycle (See Figure ) Switching Frequency -9

The value of. ma for I CC in the previous equation was obtained by derating the I CC max of ma (which occurs at - C) to I CC max at C (see Figure ). Since P O for this case is greater than P O(MAX), Rg must be increased to reduce the HCPL- power dissipation. P O(SWITCHING MAX) = P O(MAX) - P O(BIAS) = mw - mw = 9 mw P O(SWITCHINGMAX) ESW(MAX) = f 9 mw = =. µw khz For Qg = nc, from Figure, a value of E SW =. µw gives a Rg =. Ω. Thermal Model The steady state thermal model for the HCPL- is shown in Figure. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through θ CA which raises the case temperature T C accordingly. The value of θ CA depends on the conditions of the board design and is, therefore, determined by the designer. The value of θ CA = C/W was obtained from thermal measurements using a. x. inch PC board, with small traces (no ground plane), a single HCPL- soldered into the center of the board and still air. The absolute maximum power dissipation derating specifications assume a θ CA value of C/W. From the thermal mode in Figure the LED and detector IC junction temperatures can be expressed as: T JE = P E (θ LC (θ LD θ DC ) θ CA ) θ LC * θ DC PD ( θ CA ) T A θlc θ DC θ LD θ LC θ DC TJD = P E ( θ CA ) θ LC θ DC θ LD P D (θ DC (θ LD θ LC ) θ CA ) T A Inserting the values for θ LC and θ DC shown in Figure gives: T JE = P E ( C/W θ CA ) P D ( C/W θ CA ) T A T JD = P E ( C/W θ CA ) P D ( C/W θ CA ) T A For example, given P E = mw, P O = mw, T A = C and θ CA = C/W: T JE = P E 9 C/W P D C/W T A = mw 9 C/W mw C/W C = C T JD = P E C/W P D 9 C/W T A = mw C/W mw 9 C/W C = C T JE and T JD should be limited to C based on the board layout and part placement (θ CA ) specific to the application. LED Drive Circuit Considerations for Ultra High CMR Performance. Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 9. The HCPL- improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. How ever, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins - as shown in Figure. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure ), can achieve kv/µs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. Esw ENERGY PER SWITCHING CYCLE µj Qg = nc Qg = nc Qg = nc V CC = 9 V V EE = -9 V Rg GATE RESISTANCE Ω Figure. Energy Dissipated in the HCPL- for Each IGBT Switching Cycle. OPTOCOUPLERS -9

θ LD = C/W T JE T JD θ LC = C/W θ DC = C/W T C θ CA = C/W* T A T JE = LED junction temperature T JD = detector IC junction temperature T C = case temperature measured at the center of the package bottom θ LC = LED-to-case thermal resistance θ LD = LED-to-detector thermal resistance θ DC = detector-to-case thermal resistance θ CA = case-to-ambient thermal resistance θ CA will depend on the board design and the placement of the part. Figure. Thermal Model. CMR with the LED On (CMR H ). A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of ma provides adequate margin over the maximum I FLH of ma to achieve kv/µs CMR. CMR with the LED Off (CMR L ). A high CMR LED drive circuit must keep the LED off (V F V F(OFF) ) during common mode transients. For example, during a -dv cm /dt transient in Figure, the current flowing through C LEDP also flows through the R SAT and V SAT of the logic gate. As long as the low state voltage developed across the logic gate is less than V F(OFF), the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure, cannot keep the LED off during a dvcm/dt transient, since all the current flowing through C LEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMR L performance. Figure is an alternative drive circuit which, like the recommended application circuit (Figure ), does achieve ultra high CMR performance by shunting the LED in the off state. Under Voltage Lockout Feature. The HCPL- contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL- supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL- output is in the high state and the supply voltage drops below the HCPL- V UVLO threshold (9. < V UVLO <.) the optocoupler output will go into the low state with a typical delay, UVLO Turn Off Delay, of. µs. When the HCPL- output is in the low state and the supply voltage rises above the HCPL- V UVLO threshold (. < V UVLO <.) the optocoupler output will go into the high state (assumes LED is ON ) with a typical delay, UVLO Turn On Delay of. µs. IPM Dead Time and Propagation Delay Specifications. The HCPL- includes a Propagation Delay Difference (PDD) specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q and Q in Figure ) are off. Any overlap in Q and Q conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. -9

C LEDP C LEDN C LEDP C LEDN C LEDO C LEDO OPTOCOUPLERS SHIELD Figure 9. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. Figure. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. V V SAT C LEDP I LEDP C LEDN. µf V CC = V Rg V C LEDP SHIELD Q C LEDN I LEDN * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING dv CM /dt. SHIELD V CM Figure. Equivalent Circuit for Figure During Common Mode Transient. Figure. Not Recommended Open Collector Drive Circuit. V C LEDP C LEDN SHIELD Figure. Recommended LED Drive Circuit for Ultra-High CMR. To minimize dead time in a given design, the turn on of LED should be delayed (relative to the turn off of LED) so that under worst-case conditions, transistor Q has just turned off when transistor Q turns on, as shown in Figure. The amount of delay necessary to achieve this conditions is equal to the maximum value of the propagation delay difference specification, PDD MAX, which is specified to be ns over the operating temperature range of - C to C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the -9

maximum and minimum propagation delay difference specifications as shown in Figure. The maximum dead time for the HCPL- is ns (= ns - (- ns)) over an operating temperature range of - C to C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. I LED V OUT V OUT I LED Q ON Q OFF t PHL MAX tplh MIN Q OFF Q ON PDD* MAX = (t PHL - t PLH ) MAX = t PHL MAX - t PLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. V O OUTPUT VOLTAGE V (., 9.) (.,.) (.,.) (.,.) (V CC - V EE ) SUPPLY VOLTAGE V Figure. Minimum LED Skew for Zero Dead Time. Figure. Under Voltage Lock Out. I LED V OUT V OUT I LED Q ON Q OFF t PHL MIN t PHL MAX (t PHL- t PLH ) MAX PDD* MAX t PLH MIN t PLH MAX Q OFF Q ON MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (t PHL MAX - t PHL MIN ) (t PLH MAX - t PLH MIN ) = (t PHL MAX - t PLH MIN ) (t PHL MIN - t PLH MAX ) = PDD* MAX PDD* MIN OUTPUT POWER P S, INPUT CURRENT I S P S (mw) I S (ma) T S CASE TEMPERATURE C Figure. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE. *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure. Waveforms for Dead Time. -9