MOS Field Effect Transistors

Similar documents
Lecture 16: MOS Transistor models: Linear models, SPICE models. Context. In the last lecture, we discussed the MOS transistor, and

Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism;

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

Digital Electronics. Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region. Positive Logic.

Electronic Circuits for Mechatronics ELCT 609 Lecture 6: MOS-FET Transistor

MOSFET Terminals. The voltage applied to the GATE terminal determines whether current can flow between the SOURCE & DRAIN terminals.

Three Terminal Devices

Solid State Device Fundamentals

Field Effect Transistors (FET s) University of Connecticut 136

MOS Field-Effect Transistors (MOSFETs)

Lecture-45. MOS Field-Effect-Transistors Threshold voltage

Week 7: Common-Collector Amplifier, MOS Field Effect Transistor

Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD?

I E I C since I B is very small

Week 9a OUTLINE. MOSFET I D vs. V GS characteristic Circuit models for the MOSFET. Reading. resistive switch model small-signal model

Semiconductor Physics and Devices

Design cycle for MEMS

NAME: Last First Signature

Microelectronics Circuit Analysis and Design. MOS Capacitor Under Bias: Electric Field and Charge. Basic Structure of MOS Capacitor 9/25/2013

97.398*, Physical Electronics, Lecture 21. MOSFET Operation

Lecture 15. Field Effect Transistor (FET) Wednesday 29/11/2017 MOSFET 1-1

Review Sheet for Midterm #2

EEC 118 Spring 2010 Lab #1: NMOS and PMOS Transistor Parameters

LECTURE 09 LARGE SIGNAL MOSFET MODEL

Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor

Topic 2. Basic MOS theory & SPICE simulation

Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor

Field Effect Transistor (FET) FET 1-1

Lecture 13. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) MOSFET 1-1

ECEN325: Electronics Summer 2018

8. Characteristics of Field Effect Transistor (MOSFET)

UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences.

EE301 Electronics I , Fall

Lecture 24 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) The Long Metal-Oxide-Semiconductor Field-Effect Transistor

Session 10: Solid State Physics MOSFET

Microelectronics Circuit Analysis and Design

MOSFET & IC Basics - GATE Problems (Part - I)

Experiment 3. 3 MOSFET Drain Current Modeling. 3.1 Summary. 3.2 Theory. ELEC 3908 Experiment 3 Student#:

Sub-Threshold Region Behavior of Long Channel MOSFET

problem grade total

Digital Electronics. By: FARHAD FARADJI, Ph.D. Assistant Professor, Electrical and Computer Engineering, K. N. Toosi University of Technology

Chapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers

MEASUREMENT AND INSTRUMENTATION STUDY NOTES UNIT-I

EE70 - Intro. Electronics

Show the details of the derivation for Eq. (6.33) for the PMOS device.

6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers

UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press

VLSI Design I. The MOSFET model Wow!

Lecture 4. MOS transistor theory

EE105 Fall 2015 Microelectronic Devices and Circuits: MOSFET Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

ECSE-6300 IC Fabrication Laboratory Lecture 9 MOSFETs. Lecture Outline

55:041 Electronic Circuits

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier

6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers

Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages

Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati

Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs)

MTLE-6120: Advanced Electronic Properties of Materials. Semiconductor transistors for logic and memory. Reading: Kasap

Chapter 1. Introduction

Solid State Devices- Part- II. Module- IV

MOS TRANSISTOR THEORY

55:041 Electronic Circuits

CMOS Analog Design. Introduction. Prof. Dr. Bernhard Hoppe LECTURE NOTES. Prof. Dr. Hoppe CMOS Analog Design 2

FET. Field Effect Transistors ELEKTRONIKA KONTROL. Eka Maulana, ST, MT, M.Eng. Universitas Brawijaya. p + S n n-channel. Gate. Basic structure.

MOSFET FUNDAMENTALS OPERATION & MODELING

ECE 440 Lecture 39 : MOSFET-II

Analog IC Design. Lecture 1,2: Introduction & MOS transistors. Henrik Sjöland. Dept. of Electrical and Information Technology

CHAPTER 8 FIELD EFFECT TRANSISTOR (FETs)

INTRODUCTION TO ELECTRONICS EHB 222E

Basic Fabrication Steps

ITT Technical Institute. ET215 Devices 1. Unit 8 Chapter 4, Sections

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02

(Refer Slide Time: 02:05)

Chapter 6: Field-Effect Transistors

D n ox GS THN DS GS THN DS GS THN. D n ox GS THN DS GS THN DS GS THN

HW#3 Solution. Dr. Parker. Spring 2014

Session 2 MOS Transistor for RF Circuits

Course Outline. 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT)

Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET

Laboratory #5 BJT Basics and MOSFET Basics

MOSFET in ON State (V GS > V TH )

FET. FET (field-effect transistor) JFET. Prepared by Engr. JP Timola Reference: Electronic Devices by Floyd

FET(Field Effect Transistor)

Field Effect Transistors

Metal-Oxide-Silicon (MOS) devices PMOS. n-type

LECTURE 19 DIFFERENTIAL AMPLIFIER

Why Scaling? CPU speed Chip size R, C CPU can increase speed by reducing occupying area.

Experiment 5 Single-Stage MOS Amplifiers

EE5320: Analog IC Design

ECE 340 Lecture 40 : MOSFET I

Digital circuits. Bởi: Sy Hien Dinh

Summary. Electronics II Lecture 5(b): Metal-Oxide Si FET MOSFET. A/Lectr. Khalid Shakir Dept. Of Electrical Engineering

ECE 340 Lecture 37 : Metal- Insulator-Semiconductor FET Class Outline:

EECE2412 Final Exam. with Solutions

EE 330 Laboratory 7 MOSFET Device Experimental Characterization and Basic Applications Spring 2017

1 Introduction to analog CMOS design

Homework Assignment 07

Learning Outcomes. Spiral 2-6. Current, Voltage, & Resistors DIODES

Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm Exam

6.012 Microelectronic Devices and Circuits

Transcription:

MOS Field Effect Transistors A gate contact gate interconnect n polysilicon gate source contacts W active area (thin oxide area) polysilicon gate contact metal interconnect drain contacts A bulk contact source interconnect deposited oxide source interconnect (a) n polysilicon gate edge of active area bulk drain interconnect interconnect field oxide n source diffusion [ p-type ] L gate oxide drain interconnect n drain diffusion L diff p (b)

MOSFET Circuit Symbols Two complementary devices (each with two symbols): both are very useful p-substrate (n-type channel under gate oxide) n-substrate (p-type channel under gate oxide) G n _ D V DS > 0 B _ V BS S G n D S B _ G V SG p S V _ SB B V SD > 0 D G p S D B (a) n-channel MOSFET (b) p-channel MOSFET Drain n Source p Gate p Bulk or Body Gate n Bulk or Body Source n Drain p Four electrical terminals: source (lowest potential for n-channel highest for p- channel) drain gate and bulk. Basic concept: inversion layer (called the channel) formed under gate between source and drain enables drift current

n-channel MOSFET Drain Characteristics Set-up: I G = 0 V DB = V DS > 0 to reverse-bias pn junctions to bulk. Measurement scheme: short bulk to source to make it a three terminal device vary gate voltage drain voltage and see effect on drain current. D n ( V DS ) G S B V DS (a) = 3.5 V 600 n (µa) 500 400 300 200 100 (triode region) V DS = V Tn = 1 V constant current (saturation) region = 3 V = 2.5 = 0 0.5 1 V (cutoff region) = 2 V = 1.5 V 1 2 3 4 (b) 5 V DS (V)

p-channel MOSFET Drain Characteristics Set-up: I G = 0 V BD = V SD > 0 to reverse-bias pn junctions to bulk. Measurement scheme: short bulk to source to make it a three terminal device vary gate voltage drain voltage and see effect on drain current - S V SG _ V SD G B V G p _ D V D 5 V (V SG V SD ) (a) V SG = 3.5 V 300 p (µa) 250 200 150 100 50 (triode region) V SD = V SG V Tp = V SG 1 V V SG = 3 V (saturation region) V SG = 25 V SG = 0 0.5 1 V (cutoff region) V SG = 2 V V SG = 1.5 V 1 2 3 4 (b) 5 V SD (V)

Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to gate n polysilicon gate y p-type metal interconnect to bulk (a) W y* t ox E y (y * ) n drain gate oxide x channel electrons at position y = y * drifting with velocity v y (y * ) from source to drain x (b)

Drift Current Equation Drift current for electrons in the channel: J y ( x y) = qnx ( y)v y () y The drain current at position y is the integral of the drift current density across the cross section. Since the conventional direction of is opposite to the direction of the y axis we insert a minus sign: x x = W J y ( x y)dx = Wv y () y qn( x y)dx 0 0 The integral is the negative of the electron charge in the channel per unit area at point y. The symbol for this quantity is - Q N (y): = Wv y ()Q y N () y Note that isn t a function of the position in the channel

MOSFET DC Model: a First Pass metal interconnect to gate V GS _ n polysilicon gate Start simple -- small V DS makes the channel uniform V DS (< 0.1 V) n source 0 x y Q N p-type metal interconnect to bulk y = L n drain Channel charge: MOS capacitor in inversion with V GB =. Q N = C ox ( V GB V Tn ) = C ox ( V Tn ) Drift velocity: electric field is just E y = - V DS / L so v y = - µ n (-V DS / L) Drain current equation for V DS small... say less than 0.1 V. W = µ n C ox ---- ( VGS V L Tn )V DS Note that is proportional to V DS with channel resistance under gate control. This voltage controlled resistor region is sometimes useful.

Triode Region metal interconnect to gate n polysilicon gate Increase V DS -- channel charge becomes a function of position y. V DS _ n source 0 y x Q N (y) p-type metal interconnect to bulk n drain y = L First pass: approximate the drain current equation by taking averages of the channel charge and the drift velocity (Second pass: Section 4.4 (not assigned)) WQ N v y Average drift velocity: still use µ n (V DS / L) -- which is a very rough approximation.

Triode Region (Cont.) Next approximate the average channel charge by averaging Q N (y=0) at the source end and Q N (y=l) at the drain end of the channel: Q N ( y=0) = C ox ( V Tn ) At the drain end the positive drain voltage reduces the magnitude of the channel charge... why? The effect can be approximated by using V GD (the drop from drain to channel at y = L) -- Q N ( y=l) = C ox ( V GD V Tn ) = C ox ( V DS V Tn ) Note that V GD = - V DS > V Tn in order for there to be a channel left at the drain end. Substituting we derive the equation for the triode region which is defined by - V DS > V Tn and > V Tn. = µ n C W ox ---- ( VGS V L Tn V DS 2)V DS

Drain Characteristics Example: µ n C ox (W/L) = 50 µa/v 2 V Tn = 1 V and (W/L) = 4. (µa) 1000 800 = 4 V SAT 600 400 = 3 V 200 = 2 V < V Tn 0 1 2 3 4 V DS (V) What happens when V DS > - V Tn = V DS(sat)? Q N (y = L) = 0! Initial thought is that the lack of a channel at the drain end means that must drop to zero... WRONG! Drain terminal loses control over channel --> drain current saturates and remains constant (to first approximation) at the value given by V DS = V DS(sat).

Saturation Region When > V Tn and V DS > V DS(sat) = - V Tn the drain current is: W = ( sat ) = µ n C ox ------ ( VGS V 2L Tn ) 2 V DSSAT metal interconnect to gate I V DSAT GS _ n polysilicon gate n source 0 y n drain x Q N (y = L) = 0 p-type metal interconnect to bulk Full model: (µa) 1000 800 600 400 triode region Eq. (4.17) SAT = 4 V vs. V DSSAT constant current (saturation) region Eq. (4.21) = 3 V 200 = 2 V 0 1 2 3 4 V DS (V) < 1 V

MOSFET Circuit Models n-channel MOSFET drain current in cutoff triode and saturation: = 0 A ( V Tn ) = µ n C ox ( W L) [ V Tn ( V DS 2) ]( 1 λ n V DS )V DS ( VGS V Tn V DS V Tn ) = µ n C ox ( W ( 2L) )( V Tn ) 2 ( 1 λ n V DS ) ( VGS V Tn V DS V Tn ) Numerical values: µ n is a function of along the channel and is much less than the mobility in the bulk (typical value 215 cm 2 /(Vs) ) -- therefore we consider that µ n C ox is a measured parameter. Typical value: µ n C ox = 50 µav -2 λ n sometimes called the channel length modulation parameter increases as the channel length L is reduced: 0.1µmV 1 λ n ------------------------- L The triode region equation has (1 λ n V DS ) added in order to avoid a jump at the boundary with the saturation region. For hand calculation of DC voltages and currents this term is usually omitted from. V Tn = threshold voltage = 0.7-1.0 V typically for an n-channel MOSFET.

Backgate Effect The threshold voltage is a function of the bulk-to-source voltage V BS through the backgate effect. V Tn = V TOn γ n ( V BS 2φ p 2φ p ) where V TO is the threshold voltage with V BS = 0 and γ is the backgate effect parameter γ n = ( 2qε s N a ) C ox Physical origin: V BS (a negative voltage to avoid forward biasing the bulk-tosource pn junction) increases the depletion width which increases the bulk charge and thus the threshold voltage. = ( V DS V BS ) since V Tn = V Tn (V BS ) Common situation is that V BS = 0 by electrically shorting the source to the bulk (either the substrate or a deep diffused region called a well) source and bulk terminals are shorted together --> no backgate effect p n source p well n substrate n drain For this case V Tn = V TOn.

p-channel MOSFETs Structure is complementary to the n-channel MOSFET In a CMOS technology one or the other type of MOSFET is built into a well -- a deep diffused region -- so that there are electrically isolated bulk regions in the same substrate n-channel p-channel MOSFET MOSFET (a) A A common bulk contact for all n-channel MOSFETs (to ground or to the supply) isolated bulk contact with p-channel MOSFET shorted to source (b) p n source n drain p drain p source n p-type substrate n well