Credit Suisse European Technology Conference 2008

Similar documents
Holistic View of Lithography for Double Patterning. Skip Miller ASML

DUV. Matthew McLaren Vice President Program Management, DUV. 24 November 2014

Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference

A Closer Look at ASML. September 26-27, 2002

EUV Supporting Moore s Law

Imaging for the next decade

Doug Dunn ASML President and Chief Executive Officer Deutsche Bank Conference London, England September 19, / Slide 1

TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm

Competitive in Mainstream Products

Enabling Semiconductor Innovation and Growth

Leadership Through Innovation Litho for the future

Multiple Patterning for Immersion Extension and EUV Insertion. Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group

EUV lithography: today and tomorrow

EUVL getting ready for volume introduction

CLSA Investors Forum 2017

ASML Market dynamics. Dave Chavoustie EVP Sales Analyst Day, September 30, 2004

EUVL Scanners Operational at Chipmakers. Skip Miller Semicon West 2011

Advanced Patterning Techniques for 22nm HP and beyond

Outline. Introduction on IMEC & IMEC cooperation model. Program Challenges in CMOS scaling

Nikon Medium Term Management Plan

Public. Introduction to ASML. Ron Kool. SVP Corporate Strategy and Marketing. March-2015 Veldhoven

GIGAPHOTON INTRODUCTION

A Perspective on Semiconductor Equipment. R. B. Herring March 4, 2004

Double Patterning Combined with Shrink Technique to Extend ArF Lithography for Contact Holes to 22nm Node and Beyond

Pierre Brondeau Vice President, Business Group Executive Electronic Materials Regional Director - Europe Lehman Brothers Conference Call November

IC Knowledge LLC, PO Box 20, Georgetown, MA Ph: (978) , Fx: (978)

(Complementary E-Beam Lithography)

Double Patterning Combined with Shrink Technique to Extend ArF Lithography for Contact Holes to 22nm Node and Beyond

EUV lithography: status, future requirements and challenges

EUV: Status and Challenges Ahead International Workshop on EUVL, Maui 2010

Status and challenges of EUV Lithography

Beyond Immersion Patterning Enablers for the Next Decade

ASML, Brion and Computational Lithography. Neal Callan 15 October 2008, Veldhoven

Shooting for the 22nm Lithography Goal with the. Coat/Develop Track. SOKUDO Lithography Breakfast Forum 2010 July 14 (L1)

Lithography Industry Collaborations

The Development of the Semiconductor CVD and ALD Requirement

Computational Lithography Requirements & Challenges for Mask Making. Naoya Hayashi, Dai Nippon Printing Co., Ltd

Importance of Layer-to-Layer Alignment

Alignment of Defense Contractors Innovation Strategies With US DOD RDT&E Plans: The Winners and Losers.

21 st Annual Needham Growth Conference

The future of EUVL. Outline. by Winfried Kaiser, Udo Dinger, Peter Kuerz, Martin Lowisch, Hans-Juergen Mann, Stefan Muellender,

Update on 193nm immersion exposure tool

Optical Microlithography XXVIII

Toward 5nm node ; Untoward Scaling with Multi-patterning

Lithography in our Connected World

Scaling of Semiconductor Integrated Circuits and EUV Lithography

Litho Metrology. Program

Mask magnification at the 45-nm node and beyond

Lithography Roadmap. without immersion lithography. Node Half pitch. 248nm. 193nm. 157nm EUVL. 3-year cycle: 2-year cycle: imec 2005

immersion optics Immersion Lithography with ASML HydroLith TWINSCAN System Modifications for Immersion Lithography by Bob Streefkerk

R is in the unit of ma/mw or A/W. For semiconductor detectors, the value is approximately, 0.5 ma/mw.

Facing Moore s Law with Model-Driven R&D

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EE143 Final Exam

Acknowledgements. o Stephen Tobin. o Jason Malik. o Dr. Dragan Djurdjanovic. o Samsung Austin Semiconductor, Machine Learning

Current Science, Technology and Innovation Developments in India

5 th Annual ebeam Initiative Luncheon SPIE February 26, Aki Fujimura CEO D2S, Inc. Managing Company Sponsor ebeam Initiative

SEMICONDUCTOR INDUSTRY ASSOCIATION FACTBOOK

PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS. LUC VAN DEN HOVE President & CEO imec

The name 'Lethaby' has been associated with umbrellas since The current George M Lethaby Ltd was formed by a family member in 1947.

Present Status and Future Prospects of EUV Lithography

Growing the Semiconductor Industry in New York: Challenges and Opportunities

Property right statement: Copyright of charts, tables and sentences in this report belongs to

Optical Lithography. Keeho Kim Nano Team / R&D DongbuAnam Semi

BER Performance Analysis of Cognitive Radio Physical Layer over Rayleigh fading Channel

PHILIPPINES INTERNATIONAL METALWORKING August 2018 World Trade Center Metro Manila SMART TECH

The US ITER Role in Magnet Technology

CAPSTONE S EXTENDED VALUATION INDEX MARCH 2017 EV/EBITDA. EV (Enterprise Value in millions of USD) INDUSTRY EV/REVENUE ABOUT CAPSTONE S EXTENDED INDEX

Sub-12nm Optical Lithography with 4x Pitch Division and SMO-Lite

MAPPER: High throughput Maskless Lithography

Lithography on the Edge

TSMC Property. EUV Lithography. The March toward HVM. Anthony Yen. 9 September TSMC, Ltd

Improving the Active Power Filter Performance with a Prediction Based Reference Generation

Lithography. International SEMATECH: A Focus on the Photomask Industry

The 450mm Semiconductor. Wafer Size Transition contrasted to Prior Generations

From ArF Immersion to EUV Lithography

The European Semiconductor industry: 2005 Competitiveness Report. DG Enterprise

Photoresists & Ancillaries. Materials for Semiconductor Manufacturing A TECHCET Critical Materials Report

2010 IRI Annual Meeting R&D in Transition

Spring of EUVL: SPIE 2012 AL EUVL Conference Review

Electron Multi-Beam Technology for Mask and Wafer Direct Write. Elmar Platzgummer IMS Nanofabrication AG

Manufacturing Case Studies: Copy Exactly (CE!) and the two-year cycle at Intel

Used Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09

DSA and 193 immersion lithography

Optics for EUV Lithography

IMPACT OF 450MM ON CMP

2018 1Q IR PRESENTATION

Negative tone development process for double patterning

Rectangular-shaped Inductive Proximity Sensor. website

The future of lithography and its impact on design

G450C. Global 450mm Consortium at CNSE. Michael Liehr, General Manager G450C, Vice President for Research

Newer process technology (since 1999) includes :

2008 European EUVL. EUV activities the EUVL shop future plans. Rob Hartman

Impact of 3-D Mask Effects on CD and Overlay over Image Field in Extreme Ultraviolet Lithography

450mm patterning out of darkness Backend Process Exposure Tool SOKUDO Lithography Breakfast Forum July 10, 2013 Doug Shelton Canon USA Inc.

Mask Technology Development in Extreme-Ultraviolet Lithography

"L avenir est comme le reste il n est plus ce qu il était Paul Valery, Notre Destin et Les Lettres, 1937)"

Global Artificial Intelligence (AI) Semiconductor Market: Size, Trends & Forecasts ( ) August 2018

A Heuristic Method for Bus Rapid Transit Planning Based on the Maximum Trip Service

Gfinity plc ("Gfinity" or the "Company") Proposed placing to raise 7.0m Posting of Circular and Notice of General Meeting

Commercializing Innovation:

Transcription:

Credit Suisse European Technoogy Conference 2008 ASML continues to execute its eadership strategy and expects gradua order pick-up Franki D Hoore Director European Investor Reations London, 15 May 2008 / Side 1

Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform Act of 1995: the matters discussed in this document may incude forward -ooking statements, incuding statements made about our outook, reaization of backog, IC unit demand, financia resuts, average saes price, gross margin and expenses. These forward ooking statements are subject to risks and uncertainties incuding, but not imited to: economic conditions, product demand and semiconductor equipment industry capacity, wordwide demand and manufacturing capacity utiization for semiconductors (the principa product of our customer base), competitive products and pricing, manufacturing efficiencies, new product deveopment and customer acceptance of new products, abiity to enforce patents and protect inteectua property rights, the outcome of inteectua property itigation, avaiabiity of raw materias and critica manufacturing equipment, trade environment, changes in exchange rates and other risks indicated in the risk factors incuded in ASML s Annua Report on Form 20 -F and other fiings with the US Securities and Exchange Commission. / Side 2

ASML - the word s argest suppier of ithography equipment Revenue evoution Leadership in immersion for voume chip manufacturing Lam Research KLA Tencor Tokyo Eectron ASML Appied Materias Nikon 24% Canon 11% ASML 65% Top 5 semiconductor equipment suppiers 2007 Market share 2007 / Side 3 Source: Semi & ASML

/ Side 4 The Market

Market in genera Goba economic weakness drives sowdown of overa 2008 semiconductor capex forecast by anaysts and customers DRAM makers reduce capacity pan and are driving prices of memory chips up Two Fash makers deay new factories, fash prices continue to be weak Customer factory utiization rates remain high Independent market researchers are uncertain about semiconductor growth rates / Side 5

ASML affected by changing market environment - Recent capacity deay decisions by one DRAM factory expansion and two new Fash factories impact Q1 orders and 08 outook - Rationaization efforts amongst Taiwanese DRAM payers ongoing - Overa economic growth uncertainty deaying capex decisions for Foundries + Demand for immersion toos remain strong / Side 6

ASML s assessment of 2008 wordwide ithography demand March 2008 Apri 2008 ASML shipped 260 machines in 2007 with ASP of 12.9 miion ASML expects market share gains and substantia ASP growth in 2008 Numbers incude new and used equipment Source: ASML Apri 2008 / Side 7

Industry anayst 2008 memory forecasts DRAM Unit Growth NAND Unit Growth Unit Growth Gartner IC Insights VLSIR Time of Forecast / Side 8 Source: ASML MCC

2008 : Foundry 65nm ramp, MPU 45nm, 5xnm DRAM (1Gb), 4xnm NAND (32Gb), 3xnm process deveopment with DPT 200 Resoution, Shrink (nm) 100 80 60 40 AT:850 AT:1200 ASML Product Introduction XT:1400 XT:1700i XT:1900i DPT EUV 00 01 02 03 04 05 06 07 08 09 10 11 12 / Side 9

FOUNDRY Saes by process technoogy: 65nm starts voume ramp in 2008 N90 Quaification Period N90 Production Ramp 90nm Piot 65nm Piot Source: TSMC Quartery Reports / Side 10

FOUNDRY Bi-annua capacity increase pattern* suggests improved 2H/08 Foundry utiization triggers ASML itho equipment purchases 2002 2003 2004 2005 2006 2007 2008 TWINSCAN Add Point * Utiization seems to drop mainy as resut of capacity additions. If pattern hods, foundry wi ikey add capacity again in 2008. This is not a forecast. Source: ASML MCC (SAP-IFP update 12/07) / Side 11

ASML technoogy eader / Side 12

ASML immersion instaed base 86 toos Immersion technoogy used in voume production for 55 nm resoution and beyond 25 in the US 8 in Europe 53 in ASIA, (16 in Japan) Source: ASML / Side 13

Next generation ithography: EUV Abany Prototypes shipped in 2006 / Side 14 Leuven Five Piot production machines to ship 2010

EUVL Roadmap down to 11 nm support 22 nm and 16 nm node with a singe projection system Res 2010 2011 2012 2013 2014 2015 11 nm 0.4x NA 16 nm 22 nm same projection system, enhanced off-axis iumination 0.32 NA +off axis iumination 0.32 NA, 3 nm OVL, >100 wph 27 nm 0.25 NA, 4 nm OVL impementation voume production / Side 15

Doube patterning wi bridge the gap between singe exposure 193 nm immersion and EUV 200 NAND Fash DRAM Logic Resoution, "Shrink" [nm] 100 80 60 50 40 30 20 AT:1200 XT:1400 XT:1700i ASML product Introduction XT:1900i Next DFM supported ow k 1, ight DPT EUV Strong DPT EUV EUV Year of Production Start* *Process deveopment 1.5 ~ 2 years in advance (updated 12/07) / Side 16

Options to print beow immersion singe exposure imit Cost, compexity and cyce time *Wafer does not eave the exposure system between the two exposures *Wafer preferaby does not eave the itho ce between the exposures Singe exposure SE 45nm *Wafer eaves itho ce for etch between the exposures Spacer DPT SPCR 32nm Litho DPT - LELE LDPT 32nm Litho DPT - LFLE LDPF 32nm Doube exposure DE 38 nm SiON /HM Etch Cean Strip Fim Etch Metroogy Deveop Expose Top coat Resist BARC SiON / SiC Hard Mask Device fim Si / Side 17

Litho cost per ayer: estimates for 32 nm & 22 nm Singe exposure schemes more cost effective Normaized itho cost per ayer 3.0 2.5 2.0 1.5 1.0 0.5 0.0 45 nm 32 nm 32 nm 32 nm 22 nm 22 nm 22 nm ArFi 193 nm Spacer DPT 193 nm Litho DPT EUV 193 nm Spacer DPT 193 nm Litho DPT EUV Fixed Operating Source Chemica CVD Metroogy Etch Cean Retice Retice cost based on 5000 wafers / mask usage / Side 18

/ Side 19 Business summary

Q1 resuts 8 th consecutive quarter with saes over 900 miion Soid operating margin of 20.5% Cash generation 263 miion from operations Backog at 1,167 miion, 65 systems Booked 26 systems Shipped 14 immersion toos Record average seing price for new shipped systems of 18.7 miion / Side 20

Tota net saes M 3,597 3,768 2,465 2,529 1,543 *2007 numbers are adjusted retrospectivey with respect to the change in accounting poicy. / Side 21

Net saes breakdown in vaue: Q1 2008 Technoogy Saes in Units i-line 3% ArF dry 32% KrF 14% Region End-use Taiwan 15% Korea 32% Foundry 13% Europe 7% USA 24% Japan 7% Other 1% Numbers have been rounded for readers convenience / Side 22

Backog ithography in vaue per March 30th, 2008 Tota vaue M 1,167 = 65 systems Technoogy End-use Memory 56% i-line 3% KrF 9% IDM 30% ArF dry 31% ArF immersion 57% Foundry 14% USA 20% Region Korea 30% Europe 13% Other 6% Japan 9% China 9% Taiwan 13% Numbers have been rounded for readers convenience / Side 23

/ Side 24 Outook

Q2 2008 outook ASML expects to ship 42 systems ASP for new + refurbished systems expected to be 17.0 miion Gross margin approximatey 40% R&D is expected at 130 miion net of credit SG&A is expected at 58 miion Given current market weakness, we are trimming Manufacturing and SG&A variabe costs for 2008 second haf whie keeping R&D stabe / Side 25

Outook Order pattern transates into weaker net saes for next 2 quarters We expect gradua unit order pick-up from Q2 onwards, due to: Improvements in memory suppy/demand baance Voume production ramps of 45nm node Fash memory to start in H2 2008 Foundry contribution ASML s market share gains Due to advanced technoogy too mix, Q2 bookings vaue increase wi be significant / Side 26