High Performance Signaling Jan Rabaey Sources: Introduction to Digital Systems Engineering, Bill Dally, Cambridge Press, 1998. Circuits, Interconnections and Packaging for VLSI, H. Bakoglu, Addison-Wesley, 1990.
Common Wire Cross-Sections Coaxial Cable Triplate Strip Line MicroStrip Wire above Ground Plane CL = εµ
Example: Coaxial Wire
The Transmission Lines V in r l r l r l x r l V out g c g c g c g c Return path
The Lossless Transmission Line OBSERVE: ONLY FOR OFF-CHIP INTERCONNECT
Travelling Waves Response equals sum of incident and reflected waves
Wave Reflection for Different Terminations
Transmission Line Response (R L = ) 5.0 4.0 V 3.0 2.0 V Dest V Source 1.0 0.0 4.0 3.0 R S = 5Z 0 (a) V 2.0 1.0 0.0 8.0 6.0 R S = Z 0 (b) V 4.0 2.0 R S = Z 0 /5 0.0 0.0 5.0 t (in t 10.0 15.0 lightf ) (c)
Impact of Rise/Fall Time Transmission line effects only important when tr < tf Rule of thumb: Consider transmission line effects when tr < 2.5 tf = 2.5 l / ν Otherwise: Used lumped capacitor Example: no difference between RLC and RC models for 700 ps rise time (250 ohm, 1pf wire)
Critical Line Lengths versus Rise Times
Driving Transmission Lines Voltage-mode driver Current-mode driver
A Comparative Study 1m coax 100 MHz Clock Rate Full-swing CMOS transmission Low-swing current-mode transmission
Results
Signaling Modes Method to encode signal on transmission line Voltage versus current versus pulse mode Bipolar versus unipolar Differential versus single-ended Terminations: source, receiver
Terminations Off- versus On-chip Terminations Should be linear and process, supply-voltage and temperature independent
FET Terminations IV-characteristic of two-element resistor
Pass-gate Style Termination
Adjustable Terminators Thermometer-coded Adjustments Reduces switch-noise
Voltage-Mode Transmitters For reduced swings NMOS pull-up is smaller than PMOS In 0.35 micron CMOS, making R on ~ 10 % of Z 0 of 50 Ω (initial step of 90%): W/L = 320 or W = 112 µm
Series-Terminating Driver In 0.35 micron CMOS, making R on ~ Z 0 = 50 Ω W NMOS = 11 µm and W PMOS = 28 µm
Break-before-Make Pre-drivers Reduces Direct Path Current during switching Problem: noise sensitivity and delay
Current-Mode Drivers Inaccurate Trimming needed Eliminates series connection
Differential Current-Steering Drivers Smaller delay Advantages: sharp transient response constant current draw
Bipolar Current-Mode Drivers V T typically equals VDD/2 Other driver issues: - rise/fall time control - multiplexed transmitters
Receivers
Combining Detection and Sampling Less Power Reduced timing uncertainty
Receiver Structures Inverter: Bad sensitivity and Offset High Power, Large Variations (~ 500 mv in VT) Possible solution: Switching threshold compensation e.g. Inverter generating compensation voltage
Source-Coupled Amplifiers Self-Biasing Issues: Common Mode, Input Isolation Clocked SA
Lossy LRC Transmission Lines (1) Resistive Loss If (R > Lω) Cut-off frequency: Line acts as RC line f o = R/(2PL) If (R < Lω) Incident and reflected waves are attenuated: combination of travelling wave and diffusive behavior V(x)/V(0) = exp(-rx/2z 0 ) = exp(-ax) Diffusion and dispersion Wave propagation
Waveforms in lossy transmission line
Waveforms in lossy transmission line If R l >> 2 Z 0 RC like behavior if R l = Z0/2 78% of step reaches end of line Hence transmission line behavior if Rl < Z0/2 On-chip wires (Al, 0.35 micron): R = 74 Ω/mm (minimum width) Z0 = ~ 50 Ω (assume c = 160 ff/mm and l = 0.27 nh/mm) or: l < 1/3 mm for minimum width wire
Inductance versus Resistance
Copper Metalization IBM 7S process Leff = 0.12 micron 6 copper layers
(2) Skin Effect For f > fs
Impact of Skin Effect Resistance and Attenuation for 5 mil stripguuide and 24 AWG twisted pair
Aluminum Wires