DATASHEET HI25 -Bit, 80 MSPS D/A onverter (Ultra-Low Glitch Version) FN4 Rev.1.00 Features Throughput Rate.......................... 80MHz Low Power.............................. 150mW Single Power Supply........................ +5V Differential Linearity Error................ 0.5 LSB TTL/MOS ompatible Inputs Built in Bandgap Voltage Reference Power Down and Blanking ontrol Pins Low Glitch Pin ompatible with Sony XD26 Direct Replacement for Sony XD25Q Description The HI25 is a -bit, 80MHz, high speed, low power MOS D/A converter. The converter incorporates a -bit input data register with current outputs. The HI25 includes a power down feature that reduces power consumption and a blanking control. The on-chip bandgap reference can be used to set the output current range of the D/A. Ordering Information PART NUMBER TEMP. RANGE ( o ) PAKAGE PKG. NO. HI25JQ -20 to 5 32 Ld MQFP Q32.x-S Applications Wireless ommunications Direct Digital Frequency Synthesis Signal Reconstruction Test Equipment High Resolution Imaging and Graphics Systems Pinout HI25 (MQFP) TOP VIEW D2 D1 D0 (LSB) D3 D4 D5 D6 D D8 D (MSB) 32 2 28 2 26 25 1 24 2 23 3 22 4 21 5 20 6 1 18 8 1 12 13 15 16 IO IO VG V REF S REF I REF FN4 Rev.1.00 Page 1 of
Functional Block Diagram (LSB) D0 D1 D2 D3 D4 D5 D6 D D8 D 32 1 2 3 4 5 6 28 13 15 2 DEODER DEODER LOK GENERATOR LATHES 4 LSBs URRENT LLS 6 MSBs URRENT LLS URRENT LLS (FOR FULL SALE) BIAS VOLTAGE GENERATOR BAND GAP REFEREE 18 + - 24 IO 25 23 22 1 1 21 IO VG V REF I REF 20 S REF Pin Descriptions PIN NO. SYMBOL EQUIVALENT IRUIT DESRIPTION to 32 1 to D0 to D Digital Input. TO Blanking pin. No signal (0V output) at high and output state at low. onnect a capacitor of approximately F. + - lock pin. FN4 Rev.1.00 Page 2 of
Pin Descriptions (ontinued) PIN NO. SYMBOL EQUIVALENT IRUIT DESRIPTION 15, 2 Digital GND. 25 Analog GND. 1 I REF onnect resistance 16R which is 16 times output resistance R. 1 V REF Sets output full scale value. 1 AV + 22 VG DD - onnect a capacitor of approximately F. 1 22 20, 21 Analog V DD. 24 IO urrent Output pin. Output can be retrieved by connecting resistance. The standard is 200. 23 IO Inverted urrent Output pin. onnect to GND 24 normally. 23 13, 28 Digital V DD. hip Enable pin. No signal (0V output) at high makes power consumption minimum. 18 S REF AV Independent onstant-voltage Source Output pin DD using band gap reference. Stable voltage independent of the fluctuation for supply voltage can be obtained by connecting to V REF. See Application 18 ircuit 2 for details. FN4 Rev.1.00 Page 3 of
Absolute Maximum Ratings T A =25 o Thermal Information Supply Voltage (V DD ).................................. V Input Voltage (V IN )...................V SS -0.5V to V DD + 0.5V Output Voltage (I OUT ).........................0mA to 15mA Operating onditions Supply Voltage,.............................. 5.0V ± 0.25V,...............................5.0V ± 0.25V Reference Input Voltage (V REF )..................0.5V to 2.0V lock Pulse Width (t PW1, t PW0 ).................. 6.25ns (Min) Temperature Range (T OPR ).................... -20 o to 5 o Thermal Resistance (Typical, Note 1) JA ( o /W) MQFP Package............................ 122 Maximum Junction Temperature (MQFP Package)........ 150 o Maximum Storage Temperature Range..........-65 o to 150 o Maximum Lead Temperature (Soldering s)............. 0 o (MQFP - Lead Tips Only) AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation P board in free air. Electrical Specifications T A = 25 o, f = 80MHz, V DD = 5V, R = 200, V REF = 2.0V, 16R = 3.3k PARAMETER SYMBOL TEST ONDITIONS MIN TYP MAX UNITS Resolution n - - Bit Maximum onversion Rate f MAX 80 - - MHz Linearity Error EL -1.5-1.5 LSB Differential Linearity Error ED -0.5-0.5 LSB Output Full-Scale Voltage V FS 1.8 1.4 2.0 V Output Full-Scale urrent I FS.0. ma Output Off-Set Voltage V OS - - 1 mv Output Impedance - 0 - k Supply urrent I DD - - ma Digital Input urrent High Level I IH - - 5 A Low Level I IL -5 - - A Digital Input Voltage High Level V IH 2.45 - - V Low Level V IL - - 0.85 V Accuracy Guarantee Output Voltage Range V O 1.8 1.4 2.0 V Setup Time t S 3.0 - - ns Hold Time t H 3.0 - - ns Rise Time t r 5.0 - - ns Propagation Delay Time t PD - 5 - ns Glitch Energy GE R OUT = 200, 2V P-P - - pv/s Differential Gain DG - - 1.0 % Differential Phase DP - - 1.0 Degrees S REF Output Voltage S REF T A = 25 o 1.0 1.2 1.4 V FN4 Rev.1.00 Page 4 of
Test ircuits -BIT OUNTER WITH LATH D0 (LSB) IO 23 D (MSB) VG 22 200 OSILLOSOPE V REF 1 2V 5K 80MHz (MAX) SQUARE WAVE I REF 1 3.3K FIGURE 1. MAXIMUM ONVERSION RATE TEST IRUIT ONTROLLER D0 (LSB) IO 23 D (MSB) VG 22 200 DVM 80MHz SQUARE WAVE V REF I REF 1 1 2V 3.3K 5K FIGURE 2. D HARATERISTIS TEST IRUIT MHz (MAX) SQUARE WAVE FREQUEY DEMULTIPLIER D0 (LSB) IO 23 D (MSB) VG 22 V REF 1 I REF 1 2V 3.3K 5K 200 OSILLOSOPE FIGURE 3. PROPAGATION DELAY TIME TEST IRUIT FN4 Rev.1.00 Page 5 of
Test ircuits (ontinued) -BIT OUNTER WITH LATH D0 (LSB) IO 23 D (MSB) VG 22 200 OSILLOSOPE DELAY ONTROLLER V REF 1 2V 5K 1MHz SQUARE WAVE DELAY ONTROLLER I REF 1 3.3K FIGURE 4. SETUP HOLD TIME AND GLITH ENERGY TEST IRUIT FN4 Rev.1.00 Page 6 of
Timing Diagram t PW1 t PW0 TABLE 1. I/O ORRESPONDEE TABLE (2.00V Output Full Scale Voltage) INPUT ODE OUTPUT VOLTAGE t S t H t S t H t S t H MSB LSB 1 1 1 1 1 1 1 1 1 1 2.0V DATA D/A OUT t PD t PD t PD 0% 50% 1 0 0 0 0 0 0 0 0 0 1.0V 0 0 0 0 0 0 0 0 0 0 0V 0% Typical Application ircuits R3 R1 R4 R2 25 24 IO 23 22 21 20 1 18 1 IO VG V REF S REF I REF 16 26 15 2 28 13 2 12 D0 D1 32 D2 D3 D4 D5 D6 D D8 D 1 2 3 4 5 6 8 LOK INPUT NOTE: 2. When 5.0V supply voltage ( and ). Digital input from pins to 32 and pins 1 to. Pin 18 is Left Open When Using Normally. R1 = 200 R2 = 3.3 (Resistance 16 Times R1), R3 = 3.0k, R4 = 2.0k = F. FIGURE 5. APPLIATION IRUIT 1 FN4 Rev.1.00 Page of
Typical Application ircuits (ontinued) R1 R2 25 24 IO 23 22 21 20 1 18 1 IO VG V REF S REF I REF 16 26 15 2 28 13 2 12 D0 D1 32 D2 D3 D4 D5 D6 D D8 D 1 2 3 4 5 6 8 LOK INPUT NOTE: 3. When 5.0V supply voltage ( and ). Digital input from pins to 32 and pins 1 to. R1 = 200 R2 = 2.0k, = F. FIGURE 6. APPLIATION IRUIT 2 Typical Performance urves OUTPUT FULL SALE VOLTAGE (V) 2.0 1.0 1.0 REFEREE VOLTAGE (V) 2.0 OUTPUT FULL SALE VOLTAGE (V) 1.5 1.3 0 V = 0.2mV/ o -25 0 25 50 5 AMBIENT TEMPERATURE ( o ) FIGURE. OUTPUT FULL SALE VOLTAGE (V FS ) vs REFEREE VOLTAGE (V REF ) FIGURE 8. OUTPUT FULL SALE VOLTAGE vs AMBIENT TEMPERATURE FN4 Rev.1.00 Page 8 of
Typical Performance urves (ontinued) V = 0.mV/ o S REF OUTPUT VOLTAGE (V) 1.25 1.15 URRENT ONSUMPTION (ma) 20 0-25 0 25 50 5 0 1 20 40 AMBIENT TEMPERATURE ( o ) OUTPUT FREQUEY (MHz) FIGURE. S REF vs AMBIENT TEMPERATURE FIGURE. OUTPUT FREQUEY vs URRENT ONSUMPTION NOTE: 4. Standard Measurement onditions and Description: V DD = 5.0V, V REF = 2.0V, R = 200, 16R - 3.3k, T A = 25 o. The temperature characteristics of external input data in Figure = all 0 and 1 of rectangular wave; clock frequency = 80MHz. GE (Glitch Energy) GE, as described in the HI25, is a spike noise which appears synchronizing with the clock falling edge when the input data (for 1 to 24 input) changes to 128, 256, 384, 512, 640, 68, 86, and 24. Figure shows the change state of GE for the staircase wave output, and Figure 12 shows the repetitive output waveform where the GE appears. These figures exhibit the difference of this I from the convention device. The HI25 reduces the GE as shown in Figures and 12. 2.0 ANALOG OUTPUT (V) 1.0 ONVENTIONAL DEVI HI25 0 512 24 DIGITAL INPUT (V) FIGURE. HANGE OF GE FOR STAIRASE WAVE OUTPUT FN4 Rev.1.00 Page of
HI580 (GE TYP = 200pV/S) HI25 (GE TYP = pv/s) FIGURE 12. REPETITIVE OUTPUT WAVEFORM WHERE GE APPEARS (FOR 200, 2V P-P OUTPUT) Notes On Operation Selecting the Output Resistance - HI25 is a current output type D/A converter. To create the output voltage, connect the resistor to the current output pin. Specifications: Output full-scale voltage V FS (Max) = 2.0V Output full-scale current I FS (Max) = ma - alculate the output resistance from V FS = I FS x R. onnect a resistance sixteen times the output resistance to the reference current pin I REF. In some cases, as this value may not exist, a similar value can be used instead. Note that the V FS will be the following: V FS = V REF x 16 R/R. - R is the resistor to be connected to the IO and R is the resistor to be connected to the I REF. Power consumption can be reduced by increasing the resistance, but this will on the contrary increase the glitch energy and data settling time. Set the best values according to the purpose of use. orrelation between Data and lock - For the HI25 to display the desired performance as a D/A converter, the data transmitted form outside and the clock must be synchronized properly. Adjust the setup time (t S ) and hold time (t H ) as specified in Electrical haracteristics. V DD, V SS - Separate the analog and digital signals around the device to reduce noise effects. By-pass the V DD pin to each GND with a F ceramics capacitor as near to the pin as possible for both the digital and analog signals. Latch up - The and pins must be able to share the same power supply of the board. This is prevent latch up caused by potential difference between the two pins when the power is turned on. I REF pin - The I REF pin is very sensitive to improve the A characteristics. Pay attention for capacitance component not to attach to this pin because its output may become unstable. VG Pin - It is recommended to use a 1 F capacitor to improve the A characteristics though the typical capacitance value externally connected to the VG pin is F. S REF - The S REF is independent regulated current source. By connecting it to the V REF, stable output amplitudes that do not depend on fluctuations in the power supply can be obtained. - In this case, as V FS = S REF x 16R/R, set the V FS according to R. - Do not use this pin as a reference power supply for other Is because this is dedicated for the D/A converter. opyright Intersil Americas LL 1-2002. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see www.intersil.com FN4 Rev.1.00 Page of