DATASHEET ISL Features. Applications. Related Literature. Ordering Information

Transcription

1 DATASHEET ISL54058 Ultra Low ON-Resistance, Low-Voltage, Single Supply, Dual 4 to 1 Analog Multiplexer FN6380 Rev 0.00 The Intersil ISL54058 device contains precision, bidirectional, analog switches configured as a dual 4-channel multiplexer/demultiplexer, designed to operate from a single +1.6V to +3.6V supply. ON resistance is 0.41 with a +3V supply and 0.61 with a single +1.8V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 4nA max at +25 or 40nA max at +85 with a +3.3V supply. All digital inputs are 1.8V logic-compatible when using a single +3V supply. The ISL54058 is a dual 4 to 1 multiplexer device that is offered in a 16 Ld 2.6x1.8x0.5mm TQFN package. Table 1 summarizes the performance of this family. TABLE 1. FEATURES AT A GLANE onfiguration 3V R ON 0.41 Related Literature Dual 4:1 Mux 3V t RANS 29ns 1.8V R ON V t RANS 34ns Packages ISL Ld 2.6x1.8x0.5mm TQFN Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Application Note AN557 Recommended Test Procedures for Analog Switches Features Pb-Free Plus Anneal Available (RoHS ompliant) ON Resistance (R ON ) - = +3.0V = +1.8V R ON Matching Between hannels R ON Flatness Across Signal Range Single Supply Operation V to +3.6V Low Power onsumption (PD) <0.18 W Fast Switching Action (V S = +3V) - t RANS ns Break-Before-Make High urrent Handling apacity (300mA ontinuous) Available in 16 Ld 2.6x1.8x0.5mm TQFN 1.8V MOS-Logic ompatible (+3V Supply) Applications Battery Powered, Handheld, and Portable Equipment - ellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops Portable Test and Measurement Medical Equipment Audio and Video Switching Ordering Information PART NUMBER (NOTE) PART MARKING TEMP. RANGE ( ) PAKAGE PKG. DWG. # ISL54058IRUZ-T GA -40 to Ld Thin QFN Tape and Reel (Pb-free) L16.2.6x1.8A NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-020. FN6380 Rev 0.00 Page 1 of 10

2 Pinouts (Note 1) ISL54058 (16 LD TQFN) TOP VIEW) B2 A0 A2 OMA A3 A1 ADDA B1 OMB B0 B3 ADDB0 ADDB1 ADDA1 NOTE: mmx1.8mmx0.5mm Truth Table Pin Descriptions ISL54058 PIN FUNTION ADDA1 ADDA0 ADDB1 ADDB0 SWITH ON System Power Supply Input (1.6V to 3.6V) 0 0 X X A0 0 1 X X A1 1 0 X X A2 1 1 X X A3 X X 0 0 B0 X X 0 1 B1 X X 1 0 B2 X X 1 1 B3 NOTE: Logic 0 0.5V. Logic 1 1.4V, with a 3V supply. X = Don t are. OMA OMB A0-A3 B0-B3 ADDAx ADDBx Ground onnection Analog Switch hannel A Output Analog Switch hannel B Output Analog Switch hannel A Input Analog Switch hannel B Input Address Input Pin Address Input Pin FN6380 Rev 0.00 Page 2 of 10

3 Absolute Maximum Ratings to to 4.7V Input Voltages Ax, Bx, ADDx (Note 2) to () + 0.3V Output Voltages OMx (Note 2) to () + 0.3V ontinuous urrent NO or OM mA Peak urrent NO or OM (Pulsed 1ms, 10% Duty ycle, Max) mA ESD Rating HBM >4kV MM >300V DM >1kV Thermal Information Thermal Resistance (Typical, Note 3) JA ( /W) TQFN Package Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range to +150 Maximum Lead Temperature (Soldering 10s) (Lead Tips Only) Operating onditions Temperature Range ISL54058IRUZ to +85 AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on Ax, Bx, OMx, ADDx exceeding or are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications: 3V Supply Test onditions: V SUPPLY = +2.7V to +3.3V, = 0V, V INH = 1.4V, V INL = 0.5V (Note 4, 8), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( ) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full 0 - V ON Resistance, R ON = 2.7V, I OM = 100mA, V Ax or V Bx = 0V to (See Figure 4) Full R ON Matching Between hannels, R ON = 2.7V, I OM = 100mA, V Ax or V Bx = Voltage at max R ON ( Note 6) R ON Flatness, R FLAT(ON) = 2.7V, I OM = 100mA, V Ax or V Bx = 0V t0 (Note 7) Full Full = 3.3V, V INH = V ADD = 0V or Ax or Bx OFF Leakage urrent, = 3.3V, V OM = 0.3V, 3V, V Ax or V Bx = 3V, 0.3V na I Ax(OFF) or I Bx(OFF) Full na OM ON Leakage urrent, = 3.3V, V OM = V Ax or V Bx = 0.3V, 3V na I OM(ON) Full na DIGITAL INPUT HARATERISTIS Input Voltage High, V INH, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I INH, I INL, I ADDH, Full A I ADDL DYNAMI HARATERISTIS Address Transition Time, t TRANS = 2.7V, V Ax or V Bx = 1.5V, R L = 50, L = 35pF ns (See Figure ) Full ns Break-Before-Make Time, t BBM = 3.3V, V Ax or V Bx = 1.5V, R L = 50, L = 35pF ns (See Figure 2) Full ns Ax or Bx OFF apacitance, OFF f = 1MHz, V Ax or V Bx = V OM = 0V (See Figure 6) pf OM ON apacitance, OM(ON) f = 1MHz, V Ax or V Bx = V OM = 0V (See Figure 6) pf OFF Isolation R L = 50, L = 35pF, f = 100kHz (See Figures 3 and 5) db rosstalk (Note 9) db FN6380 Rev 0.00 Page 3 of 10

4 Electrical Specifications: 3V Supply Test onditions: V SUPPLY = +2.7V to +3.3V, = 0V, V INH = 1.4V, V INL = 0.5V (Note 4, 8), Unless Otherwise Specified (ontinued) TEMP (NOTE 5) (NOTE 5) PARAMETER TEST ONDITIONS ( ) MIN TYP MAX UNITS POWER SUPPLY HARATERISTIS Power Supply Range Full V Positive Supply urrent, I+ = 3.3V, V INH, V ADD = 0V or, Switch On or Off A Full A NOTES: 4. V IN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. R ON matching between channels is calculated by subtracting the channel with the highest max R ON value from the channel with lowest max R ON value. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Parts are 100% tested at +25. Limits across the full temperature range are guaranteed by design and correlation. 9. Between any two switches. Electrical Specifications: 1.8V Supply Test onditions: = +1.8V, = 0V, V INH = 1V, V INL = 0.4V (Note 4, 8), Unless Otherwise Specified PARAMETER TEST ONDITIONS TEMP ( ) MIN (NOTE 5) TYP MAX (NOTE 5) UNITS ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full 0 - V ON Resistance, R ON = 1.8V, I OM = 10.0mA, V Ax or V Bx = 1.0V (See Figure 4) Full R ON Matching Between hannels, = 1.8V, I OM = 10.0mA, V Ax or V Bx = 1.0V (Note 6) R ON) Full R ON Flatness, R FLAT(ON) = 1.8V, I OM = 10.0mA, V Ax or V Bx = 0V, 0.9V, 1.6V (Note 7) Full DIGITAL INPUT HARATERISTIS Input Voltage High, V INH, V ADDH Full V Input Voltage Low, V INL, V ADDL Full V Input urrent, I INH, I INL, I ADDH, Full A I ADDL DYNAMI HARATERISTIS Address Transition Time, t TRANS = 1.8V, V Ax or V Bx = 1.0V, R L = 50, L = 35pF(See ns Figure 1) Full ns Break-Before-Make Time, t BBM = 1.8V, V Ax or V Bx = 1.0V, R L = 50, L = 35pF (See Figure 2) ns FN6380 Rev 0.00 Page 4 of 10

5 Test ircuits and Waveforms LOGI INPUT 0V 50% t r < 5ns t f < 5ns t TRANS A0,B0 SWITH OUTPUT VA0, VB0 0V V OUT 10% 0V 90% LOGI INPUT A1-A3 B1-B3 ADD1-0 OMA OMB V OUT R L 50 L 35pF t TRANS Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. ADDRESS t TRANS MEASUREMENT POINTS Repeat test for other switches. L includes fixture and stray capacitance. R L V OUT = V (NO or N) R L + R ON FIGURE 1B. ADDRESS t TRANS TEST IRUIT FIGURE 1. SWITHING TIMES LOGI INPUT SWITH OUTPUT V OUT 0V 0V t BBM t r < 5ns t f < 5ns 90% LOGI INPUT A0-A3 B0-B3 ADD1-0 OMA OMB V OUT R L 50 L 35pF FIGURE 2A. t BBM MEASUREMENT POINTS Repeat test for other switches. L includes fixture and stray capacitance. FIGURE 2B. t BBM TEST IRUIT FIGURE 2. BREAK-BEFORE-MAKE TIME FN6380 Rev 0.00 Page 5 of 10

6 Test ircuits and Waveforms (ontinued) SIGNAL GENERATOR R ON = V 1 /100mA Ax or Bx Ax or Bx V NX ADDX 0V or 100mA V 1 ADDX 0V or ANALYZER R L OMx OMx FIGURE 3. OFF ISOLATION TEST IRUIT FIGURE 4. R ON TEST IRUIT SIGNAL GENERATOR Ax OM A 50 Ax or Bx 0V or ADDX IMPEDANE ANALYZER ADDX 0V or ANALYZER OM B Bx N.. OMx R L FIGURE 5. ROSSTALK TEST IRUIT FIGURE 6. APAITANE TEST IRUIT Detailed Description The ISL54058 analog switches offer precise switching capability from a single 1.6V to 3.6V supply with low on-resistance (0.41 ) and high speed operation (t RANS = 29ns). The device is especially well suited to portable battery powered equipment thanks to the low operating supply voltage (1.6V), low power consumption (0.17 W), low leakage currents (60nA max), and the tiny TQFN package. The ultra low on-resistance and R ON flatness provide very low insertion loss and distortion to applications that require signal reproduction. Supply Sequencing And Overvoltage Protection With any MOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the I. All I/O pins contain ESD protection diodes from the pin to and to (see Figure 7). To prevent forward biasing these diodes, must be applied before any input signals, and the input signal voltages must remain between and. OPTIONAL SHOTTKY DIODE OPTIONAL PROTETION RESISTOR OPTIONAL SHOTTKY DIODE ADD X Ax or Bx V OMX FIGURE 7. OVERVOLTAGE PROTETION FN6380 Rev 0.00 Page 6 of 10

7 If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the rail. Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 7). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low R ON switch. onnecting schottky diodes to the signal pins as shown in Figure 7 will shunt the fault current to the supply or to ground thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current. Power-Supply onsiderations The ISL54058 construction is typical of most MOS analog switches, in that they have two supply pins: and. and drive the internal MOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.6V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. and power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched and V- signals to drive the analog switch gate terminals. Logic-Level Thresholds This device is 1.8V MOS compatible (0.5V and 1.4V) over a supply range of 2.7V to 3.6V. At 2.7V the V IL level is about 0.54V. This is still above the 1.8V MOS guaranteed low output maximum level of 0.5V but noise margin is reduced. High-Frequency Performance In 50 systems, signal response is reasonably flat even past 10MHz with a -3dB bandwidth of 70MHz (see Figure 12). The frequency response is very consistent over a wide range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch s input to its output. Off Isolation is the resistance to this feed through, while rosstalk indicates the amount of feed through from one switch to another. Figure 11 details the high Off Isolation and rosstalk rejection provided by this family. At 100kHz, Off Isolation is about 65dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and rosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage onsiderations Reverse ESD protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. Virtually all the analog leakage current comes from the ESD diodes to or. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and or. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from to with a fast transition time minimizes power dissipation. FN6380 Rev 0.00 Page 7 of 10

8 Typical Performance urves T A = +25, Unless Otherwise Specified I OM = 100mA = 1.65V = 3V I OM = 100mA R ON ( ) = 1.8V R ON ( ) = 2.7V = 3V = 3.6V V OM (V) FIGURE 8. ON RESISTANE vs SUPPLY VOLTAGE vs SWITH VOLTAGE V OM (V) FIGURE 9. ON RESISTANE vs SWITH VOLTAGE = 1.8V I OM = 100mA = 3V R ON ( ) ROSSTALK (db) ISOLATION OFF ISOLATION (db) V OM (V) FIGURE 10. ON RESISTANE vs SWITH VOLTAGE ROSSTALK k 10k 100k 1M 10M 100M 500M FREQUENY (Hz) FIGURE 11. ROSSTALK AND OFF ISOLATION FN6380 Rev 0.00 Page 8 of 10

9 Typical Performance urves T A = +25, Unless Otherwise Specified (ontinued) Die haracteristics NORMALIZED GAIN (db) 0 GAIN -10 = 3V 0 PHASE PHASE ( ) SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR OUNT: 228 PROESS: Submicron MOS R L = 50 V IN = 0.2V P-P to 2V P-P FREQUENY (MHz) FIGURE 12. FREQUENY RESPONSE opyright Intersil Americas LL All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN6380 Rev 0.00 Page 9 of 10

10 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) D A B L16.2.6x1.8A 16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTI PAKAGE 6 INDEX AREA N 2X X 0.10 TOP VIEW 0.10 A 0.05 SEATING PLANE A1 SIDE VIEW e PIN #1 ID 1 2 L1 (DATUM B) (DATUM A) BOTTOM VIEW L (A1) NX (b) 5 e SETION "-" NX L E NX b 5 16X 0.10 M A B 0.05 M L TERMINAL TIP SYMBOL MILLIMETERS MIN NOMINAL MAX NOTES A A A REF - b D E e 0.40 BS - L L N 16 2 Nd 4 3 Ne Rev. 4 8/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDE Reference MO For additional information, to assist with the PB Land Pattern Design effort, see Intersil Technical Brief TB LAND PATTERN FN6380 Rev 0.00 Page 10 of 10