A CMOS Impulse Radio Ultra-Wideband Transceiver for Inter/Intra-chip Wireless Interconnection

Similar documents
A CMOS UWB Transmitter for Intra/Inter-chip Wireless Communication

ULTRA-WIDEBAND (UWB) is defined as a signal that occupies

CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN

A 3 8 GHz Broadband Low Power Mixer

HIGH-GAIN CMOS LOW NOISE AMPLIFIER FOR ULTRA WIDE-BAND WIRELESS RECEIVER

A Low Power Interference Robust IR-UWB Transceiver SoC for WBAN Applications

CMOS LNA Design for Ultra Wide Band - Review

Design and Implementation of a 1-5 GHz UWB Low Noise Amplifier in 0.18 um CMOS

SP 22.3: A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver

Low-Power RF Integrated Circuit Design Techniques for Short-Range Wireless Connectivity

DESIGN ANALYSIS AND COMPARATIVE STUDY OF RF RECEIVER FRONT-ENDS IN 0.18-µM CMOS

A Low Power Integrated UWB Transceiver with Solar Energy Harvesting for Wireless Image Sensor Networks

A Low Power Single Ended Inductorless Wideband CMOS LNA with G m Enhancement and Noise Cancellation

A low-if 2.4 GHz Integrated RF Receiver for Bluetooth Applications Lai Jiang a, Shaohua Liu b, Hang Yu c and Yan Li d

Quadrature GPS Receiver Front-End in 0.13μm CMOS: The QLMV cell

Single Chip CMOS Transmitter for UWB Impulse Radar Applications

A Switched VCO-based CMOS UWB Transmitter for 3-5 GHz Radar and Communication Systems

1P6M 0.18-µm Low Power CMOS Ring Oscillator for Radio Frequency Applications

Design and Implementation of Impulse Radio Ultra-Wideband Transmitter

DESIGN OF 3 TO 5 GHz CMOS LOW NOISE AMPLIFIER FOR ULTRA-WIDEBAND (UWB) SYSTEM

A Novel Sine Wave Based UWB Pulse Generator Design for Single/Multi-User Systems

A COMPACT WIDEBAND MATCHING 0.18-µM CMOS UWB LOW-NOISE AMPLIFIER USING ACTIVE FEED- BACK TECHNIQUE

Design technique of broadband CMOS LNA for DC 11 GHz SDR

Designing a 960 MHz CMOS LNA and Mixer using ADS. EE 5390 RFIC Design Michelle Montoya Alfredo Perez. April 15, 2004

An Energy Efficient 1 Gb/s, 6-to-10 GHz CMOS IR-UWB Transmitter and Receiver With Embedded On-Chip Antenna

ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.5

Design of Single to Differential Amplifier using 180 nm CMOS Process

A 3 5 GHz CMOS High Linearity Ultra Wideband Low Noise Amplifier in 0.18µ CMOS

ISSCC 2006 / SESSION 20 / WLAN/WPAN / 20.5

ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.2

A 3-10GHz Ultra-Wideband Pulser

Bluetooth Receiver. Ryan Rogel, Kevin Owen I. INTRODUCTION

Quiz2: Mixer and VCO Design

Ultra Wideband Amplifier Senior Project Proposal

Ultra-Wideband RF Transceiver Design in CMOS Technology

Fully integrated CMOS transmitter design considerations

Design and Simulation of 5GHz Down-Conversion Self-Oscillating Mixer

High-Performance Analog and RF Circuit Simulation using the Analog FastSPICE Platform at Columbia University. Columbia University

Design of a Low Noise Amplifier using 0.18µm CMOS technology

A CMOS GHz UWB LNA Employing Modified Derivative Superposition Method

A Volterra Series Approach for the Design of Low-Voltage CG-CS Active Baluns

Pulse-Based Ultra-Wideband Transmitters for Digital Communication

A High Gain and Improved Linearity 5.7GHz CMOS LNA with Inductive Source Degeneration Topology

2.Circuits Design 2.1 Proposed balun LNA topology

Berkeley. Mixers: An Overview. Prof. Ali M. Niknejad. U.C. Berkeley Copyright c 2014 by Ali M. Niknejad

LOW POWER CMOS LNA FOR MULTI-STANDARD WIRELESS APPLICATIONS Vaithianathan.V 1, Dr.Raja.J 2, Kalimuthu.Y 3

A Differential K-Band UWB Transmitter for Short Range Radar Application with Continuous Running Local Oscillator

Design of a Low Power 5GHz CMOS Radio Frequency Low Noise Amplifier Rakshith Venkatesh

Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-µm technology scale

AVoltage Controlled Oscillator (VCO) was designed and

A Compact GHz Ultra-Wideband Low-Noise Amplifier in 0.13-m CMOS Po-Yu Chang and Shawn S. H. Hsu, Member, IEEE

Design of a Broadband HEMT Mixer for UWB Applications

A Flexible, Low Power, DC-1GHz Impulse-UWB Transceiver Front-end

Design and Simulation Study of Active Balun Circuits for WiMAX Applications

THE INTERNATIONAL JOURNAL OF SCIENCE & TECHNOLEDGE

UWB Impact on IEEE802.11b Wireless Local Area Network

International Journal of Pure and Applied Mathematics

ULTRA WIDEBAND RECEIVER FRONT-END AHMAD MAHMOUD SHEREEF HASSAN ELHEMEILY AHMED MOHAMMED AHMED SAYED A THESIS

ALTHOUGH zero-if and low-if architectures have been

Reconfigurable and Simultaneous Dual Band Galileo/GPS Front-end Receiver in 0.13µm RFCMOS

A Low Power 900MHz Superheterodyne Compressive Sensing Receiver for Sparse Frequency Signal Detection

Document Version Publisher s PDF, also known as Version of Record (includes final page, issue and volume numbers)

An 8mA, 3.8dB NF, 40dB Gain CMOS Front-End for GPS Applications

UWB Hardware Issues, Trends, Challenges, and Successes

A 5.2GHz RF Front-End

RF CMOS 0.5 µm Low Noise Amplifier and Mixer Design

A HIGH FIGURE-OF-MERIT LOW PHASE NOISE 15-GHz CMOS VCO

Research and Design of Envelope Tracking Amplifier for WLAN g

DESIGN OF 2.4 GHZ LOW POWER CMOS TRANSMITTER FRONT END

A New Current-Mode Sigma Delta Modulator

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

1-13GHz Wideband LNA utilizing a Transformer as a Compact Inter-stage Network in 65nm CMOS

Dual-band LNA Design for Wireless LAN Applications. 2.4 GHz LNA 5 GHz LNA Min Typ Max Min Typ Max

Channel-based Optimization of Transmit-Receive Parameters for Accurate Ranging in UWB Sensor Networks

Design of a Wideband LNA for Human Body Communication

Design of High Gain and Low Noise CMOS Gilbert Cell Mixer for Receiver Front End Design

The Measurement and Characterisation of Ultra Wide-Band (UWB) Intentionally Radiated Signals

1.Circuits Structure. 1.1 Capacitor cross-coupled

print close Related Low-Cost UWB Source Low-Cost Mixers Build On LTCC Reliability LTCC Launches Miniature, Wideband, Low-Cost Mixers

Designing a fully integrated low noise Tunable-Q Active Inductor for RF applications

A NOVEL SYNCHRONIZATION SCHEME FOR MOSTLY DIGITAL UWB IMPULSE RADIO ARCHITECTURE ZHANG QI

DESIGN OF LOW POWER CMOS LOW NOISE AMPLIFIER USING CURRENT REUSE METHOD-A REVIEW

C th NATIONAL RADIO SCIENCE CONFERENCE (NRSC 2011) April 26 28, 2011, National Telecommunication Institute, Egypt

Highly linear common-gate mixer employing intrinsic second and third order distortion cancellation

A 2.4GHz Cascode CMOS Low Noise Amplifier

NEW WIRELESS applications are emerging where

Design of Wide Tuning Range and Low Power Dissipation of VCRO in 50nm CMOS Technology

High Gain CMOS UWB LNA Employing Thermal Noise Cancellation

Microelectronics Journal

Novel RF Front-End Design for Low Power UWB Applications

Hot Topics and Cool Ideas in Scaled CMOS Analog Design

65-GHz Receiver in SiGe BiCMOS Using Monolithic Inductors and Transformers

Research and Development Activities in RF and Analog IC Design. RFIC Building Blocks. Single-Chip Transceiver Systems (I) Howard Luong

Project: IEEE P Working Group for Wireless Personal Area Networks N

Chapter 6. Case Study: 2.4-GHz Direct Conversion Receiver. 6.1 Receiver Front-End Design

A 5 GHz CMOS Low Power Down-conversion Mixer for Wireless LAN Applications

ISSCC 2006 / SESSION 33 / MOBILE TV / 33.4

A low noise amplifier with improved linearity and high gain

A GSM Band Low-Power LNA 1. LNA Schematic

Transmission-Line-Based, Shared-Media On-Chip. Interconnects for Multi-Core Processors

Transcription:

Journal of Emerging Trends in Engineering and Applied Sciences (JETEAS) 3(6): 929-933 Scholarlink Research Institute Journals, 2012 (ISSN: 2141-7016) jeteas.scholarlinkresearch.org Journal of Emerging Trends in Engineering and Applied Sciences (JETEAS) 3(6):929-933(ISSN: 2141-7016) A Impulse Radio Ultra-Wideband Transceiver for Inter/Intra-chip Wireless Interconnection Nhan Nguyen 1, Nghia Duong 2, Anh Dinh 3 1 Faculty of Physics and Engineering Physics, University of Science-VNU Hochiminh City, Vietnam; 2 Faculty of Electrical and Electronics Engineering, University of Technology, VNU Hochiminh City, Vietnam; 3 Dept. of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, Canada. Corresponding Author: Nhan Nguyen Abstract This paper presents a impulse radio ultra-wideband (IR-UWB) transceiver designed and implemented using IBM 0.13um technology for inter-chip and intra-chip wireless interconnec-tion. The IR-UWB transmitter is based on the high order derivative Gaussian pulse using LC-Tank oscillator. A pulse for the 6.3-10GHz IR-UWB transmitter generated with low power, high peak amplitude, and high frequency. This pulse PSD fully complies with the FCC spectrum mask. The IR-UWB receiver is based on the non-coherent architecture which removes the complexity of RF architecture (such as DLL or PLL) and reduces power consumption. The receiver consists of three blocks: a low noise amplifier (LNA) with active balun, a correlator, and a comparator. Simulation results of the IR-UWB transmitter show a pulse width of 1.1ns, a peak to peak amplitude pulse of 90mV and an energy consumption of 39pJ/pulse at 200MHz pulse repetition rate (PRR). The receiver provides a power gain (S21) of 12.5dB, a noise figure (NF) of 3.05dB, an input return loss (S11) of less than -16.5dB, a conversion gain of 18dB, a NF DSB of 22, and a third order intercept point (IIP3) of -1.3dBm. The transceiver uses an area of 0.38mm 2 and consumes 30.7mW of power on the 1.4V power supply. The results show a promising transceiver for wireless communications applicable to 3-D ICs due to its low complexity and small chip area. Keywords: IR-UWB transmitter, IR-UWB receiver, inner-chip/inter-chip wireless interconnection, Gaussian pulse, non-coherent receiver INTRODUCTION Traditional wire interconnect systems using metal are projected to be limited in their ability to meet the future interconnect needs (Brian A. Floyd et al., 2001). The limitation of the traditional wire interconnects can be viewed from four aspects, namely, interconnect resistance, interconnect capacitance, interconnect inductance, and bit-rate capacity (James D. Meindl et al., 2001; Jeffery A. Davis et al., 2001; A. Deutsch et al., 2001). The interconnect resistance is calculated as R interconnect = R wire + R contact + R via (1) With interconnect resistance increasing, more and more interconnect wires are becoming RC transmission lines with RC delay constant, which can be seen as τ delay = R interconnect x C interconnect (2) To address this problem, inter-chip and intra-chip wireless interconnects using microwaves are being evaluated (Takahide Terada et al., 2006; Yuanjin Zheng et al., 2006;). In this paper, we propose a transceiver architecture to be used as wireless interconnect system using ultra-wideband (UWB) technology. The technology employs ultra-wide bandwidth and very low emission power density. UWB can be potentially used in low cost, low power, and short range high-speed communication applications. In 2002, the Federal Communications Commission (FCC) has released unlicensed 3.1-10.6GHz frequency band for UWB related applications. The UWB transmission is defined as the occupied fraction band-width of >20% or larger than 500MHz of the absolute bandwidth and the power spectrum density (PSD) of the pulse must be below - 41.3dBm/MHz (FCC, 2002). In recent years, a number of research works focused on inter-chip and intra-chip wireless interconnections by using IR-UWB communi-cations due to its low complexity and low power (Tiuraniemi et al., 2005; Yuanjin Zheng et al., 2005; S. Jeong-Bae et al., 2008; Yuanjin Zheng et al., 2006). In this work, a fully integrated transmitter and receiver based (TX- RX) on the UWB technique were designed and implemented in a 0.13um technology. The implemented TX-RX can achieve a transmission rate 929

of 100-200Mbps in noncoherent mode and consumes a minimum amount of power. The layout area is as small as 0.38mm 2. IR-UWB TRANSCEIVER OVERVIEW Figure 1 is a simplified block diagram of the proposed IR-UWB transceiver. for the loss in the tank. The oscillation frequency of this circuit can be found as: 2 1 1 R C (3) LC L Figure 2. LC-tank model. To generate a negative conductance, a balanced NMOS circuit topology shown in Figure 3 is chosen for this work. In practical integrated LC-tank, the inductors are on-chip spiral inductors with low quality factor that dominates the loss of the LC-tank. Figure 1. Block diagram of the proposed transceiver In IR-UWB systems, the receiver is an important component and is more complex than the transmitter. A high order derivative Gaussian pulse generator using a LC tank is proposed for the transmitter. This generator is intended to be used in the upper UWB frequency band of 6-10GHz. PSD of the generated pulse fully complies with the FCC spectrum mask for indoor applications. In addition to the spectrum requirement, wireless applications require outstanding noise (phase noise and jitter) performance at high frequency, LC tank is the component of choice in the design. The receiver consists of a low-noise amplifier (LNA) with an active balun, a correlator, and a comparator. There are basically two different types of receivers employed in IR-UWB systems namely coherent receiver and non-coherent receiver. An IR-UWB based non-coherent single chip receiver was presented (Tiuraniemi et al., 2005; Yuanjin Zheng et al., 2005). The receiver covers the high frequency band 6.0-10GHz of the UWB system. The received UWB signal is amplified through a low-noise amplifier (LNA) with an active balun. This amplifier provides a constant gain optimized around the operation frequency of 8.0 GHz. After being first amplified by the LNA, the received pulse is then selfcorrelated by a correlator. The received signal is then sent to a comparator for digital quantization. Figure 3. Balanced NMOS Figure 4. Schematic diagram of the LC-tank based high order derivative Gaussian pulse generator IR-UWB TRANSMITTER CIRCUIT DESIGN The proposed high order derivative Gaussian pulse generator was designed using a LC-tank oscillator and implemented in IBM 0.13μm technology with 1.4V supply voltage. Figure 2 shows the LCtank model, where the conductance g tank represents the tank loss and -g active is the effective negative conductance of the active devices that compensates 930 A completed circuit of the high order derivative Gaussian pulse generator is shown in Figure 4. This circuit comprises three stages. The first stage is a chain of inverters that is used to delay the input signal in the order of picosecond. The second stage is a XOR gate that used to generate a short pulse. The final stage is a LC-tank that is used to generate a high order derivative Gaussian pulse. The frequency

selective tank consists of two inductors in parallel with capacitor C 4, C 5. Resistor R represents the inductor equivalent series resistance. The crossedcouple pair of nmos M 11,12 is biased with the current I/2, implemented with nmos M 13 in the saturation region. The crossed-couple pair generates a negative resis-tance of -2/gm 11,12 to compensate for the resistance R, where g m11,12 are the transconductances of the transistors M 11,12. There are two complementary short pulses generated by the inverter chain M 1 -M 10 and the XOR gate. Capacitors C 1 -C 3 and the XOR gate control the switches SW 1,2. When SW 1 is open (i.e., SW 2 is closed), the LC tank starts oscillate due to noise. The amplitude of the oscillating signal increases gradually within a certain period. When SW 1 is closed (i.e., SW 2 is open), the energy inside the LC tank is released through SW 1, and the oscillation signal gradually disappear. IR-UWB RECEIVER CIRCUIT DESIGN The proposed IR-UWB receiver employs the noncoherent receiver architecture. The receiver consists of a low-noise amplifier (LNA) with an active balun, a correlator, and a comparator. A. LNA and Active Balun: The UWB LNA design uses resistive feedback current reuse technique. The design was implemented in the IBM 0.13um technology with appropriate impedance matching and noise/power optimizations. The LNA achieves up to 12.5dB power gain with a noise figure of 3.05dB over the UWB 3.1-10.6GHz frequency range. Figure 5 shows the schematic of the designed LNA. Figure 5. Schematic diagram of the LNA The input inductor L 1 is added to compensate for the parasitic capacitors of M 1 and M 2 transistors at high frequencies. A resistive feedback buffer with peaking inductor load is coupled with the reuse UWB stage through capacitor C 3 to drive the 50Ohm output load. In addition, in the resistive feedback current reuse configuration (the first stage), loading the NMOS transistor M 1 with the PMOS transistor M 2 allows the circuit to operate under lower supply voltage than resistive load configuration. and the input of the second cascode. Since v gs5 =-v gs6, two balanced differential outputs can be achieved on the condition of g m5 =g m6 Figure 6. Schematic diagram of the active balun B. Correlator: The output of the LNA must be correlatively multiplied and then integrated in order to detect the energy of the received signal. Figure 7 shows the block diagram of correlator and equation (4) shows the output signal of correlator. Figure 7. Block diagram of the correlator t 0 0 ( ). template ( ) t0 T r t r t S t dt (4) where r 0 (t) is the output signal of the correlator, r(t) is the input signal of the correlator and S template (t) is the template signal. Figure 8 shows the schematic diagram of the correlator. The correlator employs the Gilbert mixer topology, and the integrator is realized by capacitors C1 and C2. After the pulse is mixed with itself, the integrator begins to integrate; between the pulses intervals, the integrator discharges energy and is ready for the next integration. The capacitances of C1 and C2 should be large enough to hold the integrated voltage for the comparator and yet small enough to discharge between pulses intervals in order to be ready for the next integration cycle. The transmission data rate relies on the speed of the integration process. A two-cascode stage active balun of Figure 6 is used to convert the single-ended output of the LNA to differential signals. The output of M4 connects to M6 931 Figure 8. Schematic diagram of the correlator

C. Comparator: After the received signal is squared and integrated by the correlator, a comparator compares it with a reference voltage and performs digital quantization. However the comparator output is a return-to-zero (RZ) signal which needs to be converted to a non-return-to-zero (NRZ) signal that can synchronize with the baseband clock. In a coherent receiver, a DLL/PLL is usually introduced to perform synchronization between the received pulse and the local pulse. This requires a precision on the order of several tens of picoseconds. However, in a noncoherent receiver, the RZ signal quantized by the comparator exhibits a duty cycle on the order of nanoseconds. Therefore, a low jitter DLL/PLL is no longer necessary and a sliding correlator is employed. The technique reduces complexity of the receiver. The topology of the comparator consists of differential amplifier with buffering inverter and common-source amplifier. The block diagram and the schematic diagram of the comparator are shown in Figure 9 and Figure 10, respectively. Figure 10. Gaussian pulse FCC Mask Figure 11. Normalized PSD of Gaussian pulse Figure 9. Block diagram of the comparator SIMULATION RESULTS The IR-UWB transceiver was designed and simulated using Cadence tools applicable in IBM 0.13um technology. Figure 10 and Figure 11 show the simulation results in time domain and the normalized PSD of the generated high order derivative Gaussian pulse with 50Ω load (for antenna matching purpose). The peak-to-peak swing is 90mV. For wireless communications at short distances, this pulse amplitude is sufficient to deliver the pulse to the antenna without the need for a wide band amplification. The pulse duration is 1.1ns exhibits the high spectral allocation in the 6.3 10GHz range, shown in Figure 10. Figure 11 shows the power spectral density of this pulse. Figure 12 shows the layout view of the IR-UWB transceiver. The area of the transceiver is about 0.38mm 2. The power consumption of the trans-ceiver is 30.7mW for the 1.4V supply voltage. Table 1 shows the performance parameters of the designed IR-UWB transceiver compared with other published works. Figure 12. Layout view of the IR-UWB Transceiver 932

Table 1: Performance parameters summary and comparison with the other transceivers Parameters Technology This work 0.13um Yuanjin Zheng (2005) Bandwidth (GHz) 6.3-10 3.1-5 Takahide Terada (2006) 250MHz F c=400 MHz Pulse Width (ns) 1.1 0.8 2 0.7 V pp (mv) 90 35 100 20 Energy(pJ/pulse) 39 - - - S11 (db) < -16.5 - - - Gain Max(dB) (S21) 12.5 18 16 - NF (db) 3.05 7.5 5.6 - Conversion Gain(dB) 18 5 - - IIP3 (dbm) -1.3-14 - - M. Anis (2007) 6-8.5 Data rate(mbps) 200 50 1 4MHz Power (mw) 30.7 41.4 ~9.2 2.6 Chip Area(mm 2 ) 0.38 4.67 0.42 3.15 CONCLUSION In this work, a IR-UWB transceiver was designed and simulated using Cadence tool with IBM 0.13um technology for inter-chip and intrachip interconnection. The results show a promising transceiver for wireless communications applicable to 3-D ICs due to its low complexity and small chip area. The simulation shows a data rate of 200Mbps can be achieved. However, the transceiver circuit also has high power consumption due to the tail current needed in the transmitter architecture. REFERENCES A. Deutsch, Paul W. Coteus, Gerard V. Kopcsay (2001): On-chip wiring design challenges for Gigahertz operation, Proceedings of the IEEE, Vol. 89, No. 4., 2001. Federal Communications Commission (2002): First report and order, revision of part 15 of the commission s rules regarding ultra wideband transmission system, Washington, DC, ET Docket 98-153, 2002. J.A. Davis, R. Venkatesan, A. Kaloyeros, M. Bylansky, S.J. Souri, K. Banerjee, K.C. Saraswat, A. Rahman, R. Reif, and J.D. Meindl, (2001): Interconnect Limits on Gigascale Integration (GSI) in the 21st Century, Proceedings of the IEEE, vol. 89, no. 3, pp. 305-324, March 2001. S. Jeong-Bae, K. Jong-Ha, S. Hyuk, and Y. Tae- Yeoul, (2008): "A Low-Power and High-Gain Mixer for UWB Systems," Microwave and Wireless Components Letters, IEEE, Vol. 18, pp. 803-805, 2008. Takahide Terada, Shingo Yoshizumi, Muhammad Muqsith, Yukitoshi Sanada, and Tadahiro Kuroda (2006): A Ultra-Wideband Impulse Radio Transceiver for 1-Mb/s Data Communications and ±2.5-cm Range Finding, IEEE Journal of Solid-State Circuits, Vol. 41, No. 4, 2006. Tiuraniemi, S., Stoica, L.; Rabbachin, A., and Oppermann, I., (2005): Front-end receiver for low power, low complexity non-coherent UWB communication system, IEEE International Conference on Ultra-Wideband, pp. 339-343, 2005. Yuanjin Zheng, Yan Tong, Jiangnan Yan; Yong-Ping Xu, Wooi Gan Yeoh, and Fujiang Lin, (2005): A low power non-coherent UWB transceiver ICs, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers, pp. 347-350, 2005. Yuanjin Zheng, Yueping Zhang, and Yan Tong, (2006): A Novel Wireless Interconnect Techno-logy Using Impulse Radio for Interchip Communications, IEEE Transactions On Micro-wave Theory And Techniques, Vol. 54, No. 4, 2006. M. Anis and R. Tielert (2007): Design of UWB Pulse Radio Transceiver Using Statistical Correlation Technique In Frequency Domain, Advances in Radio Science, 5, 297-304, doi:10.5194/ars-5-297- 2007. James D. Meindl, Raguraman Venkatesan, Jeffrey A. Davis, James Joyner, Azad Naeemi, (2001): Interconnecting Device Opportunities for Gigascale Integration (GSI), Electron Devices Meeting 2001 (IEDM '01) Technical Digest International. 933