Flip-Chip Bumping Services: Driving Value-Added Businesses

Research Brief Flip-Chip Bumping Services: Driving Value-Added Businesses Abstract: Wafer-bumping services are diversifying their forms with the evolution of flip-chip packaging technology. By Masao Kuniba and Philip Koh Recommendations IDMs need to consider how to utilize wafer-bumping services, which are provided by SATS providers or foundry service providers as a turnkey solution for flip-chip packaging. The plating Au wafer-bumping service market will be in a long-term declining trend and wafer-bumping service providers need to consider value-added services including flip-chip packaging in addition to developing plating solder and lead-free bumping methods. Combination of the stud-bumping method and advanced flip-chip packaging technique will allow integration of three-dimensional packaging into system-in-apackage, and IDMs and SATS need to consider standardization of dies optimized for SIP. Publication Date:October 9, 2002

2 Flip-Chip Bumping Services: Driving Value-Added Businesses Introduction Wafer-bumping and die-bumping techniques of gold (Au), solder and other lead-free alloys are indispensable for flip-chip packaging and will be key to packaging solutions both for system on chip (SOC) and system-in-apackage (SIP). Gartner Dataquest expects strong growth of high value-added flip-chip bumping services by semiconductor assembly and test services (SATS) providers, foundries and integrated device manufacturers (IDMs). This Perspective reviews the technology and market trends of each bumping method and the regional distribution of wafer-bumping service providers. Classification of Bumping Technologies and Recent Development Trends Recently, diversification of flip-chip packaging types and the pace of technological advancement have sparked continuous development and modification of bumping technology. Gartner Dataquest classifies bumping technologies into five types according to the bump-formation method (see "Flip-Chip Packaging Update: Emerging Market With Solder Bumping Service Providers," SEMC-WW-DP-0057). Here, the five bumping technologies are reviewed in terms of wafer-bumping and die-bumping technologies, and the latest technology trends are added as required. They are as follows: Plating Au-bumping method This is a wafer-bumping technique for bump formation by electrolytic or electroless Au plating. This technique has been established as a mainstream bump-formation technology for liquid crystal-display (LCD) drivers. The market and its growth trend aresignificantlyaffectedbythefuturedevelopmentofthepackaging market, especially tape-carrier-package (TCP) and chip-on-flexible (COF). LCD driver packaging is increasingly moving toward chip-onglass (COG), together with the adoption of low-temperature polysilicon/organic electroluminescent technology for next-generation display implementation. As a result, this segment will be in a long-term decline. Plating solder-bumping method This is a wafer-bumping method for bump formation by electrolytic or electroless solder plating. This technique is being rapidly adopted as full-area bump technology for high value-added SOCs such as microprocessing units (MPUs), digital signal processors (DSPs), advanced memories and application-specific integrated circuit/application-specific standard products (ASIC/ASSPs). While it offers high reliability, it requires a relatively long turnaround time, ranging from mask design to wafer-bumping, probe test and flip-chip packaging. Cost advantage can be realized if volume production is achieved, but the long turnaround time makes it difficult to meet flexible production requirements for multifunction mobile electronic equipment with a short life cycle in which time to market is a critical success factor. Also, the relatively high cost is a major

hurdle for the solder plating solution to be deployed into the costsensitive emerging markets. Meanwhile, the industry is striving to address future lead-free needs by developing a tin-silver (Sn-Ag) solution to replace solder (Sn-Pb). Printing solder bumping This is a wafer-bumping method for bump formation using a solder paste and the screen printing by stencil. However, it is technically difficult to meet finer bump pitch requirements less than 150 microns because of the technical bottleneck in stencil technology. On the other hand, it offers a shorter turnaround time than the solder-plating method, and cost reduction is expected with the improvement in bump reliability. Stud bumping This is a die-bumping method using gold wire and the ball bonding technique. It can enjoy the established infrastructure conventional wire bonding technology and equipment and satisfy small pitch requirements, albeit limited to the peripheral bump. By leveraging these advantages, development and modification is under way to establish flip-chip technology capable of fitting in the flexible production environment characterized by small lots and a large variety of products. Combining the stud-bumping method with the ultrasonic flip-chip packaging technique will allow integration of threedimensional packaging into SIP within a short period of time. In particular, by deploying advanced memories and microcontroller units (MCUs) optimized for SIP as a common module, the method is expected to become a time-to-market solution for the cost-sensitive emerging market multifunction mobile electronic equipment. Finally, the use of gold wire has a future cost advantage, as it is free from the lead-free development efforts. Ball bumping This is the method transferring solder balls and other lead-free alloy balls and forming bumps by reflow. This method is implemented by either wafer-bumping or die-bumping technology. Leading-edge methods are developed, including modification, using micro-balls such as low-alpha solder balls and other lead-free alloys (for example, Sn-Ag and Sn-zinc [Zn]) to meet the packaging needs for advanced memories. With the ability to minimize the variation of ball diameters, the method boasts a high level of uniformity in terms of coplanarity and can assure a 100 percent yield because of reparability. However, as the cost-effectiveness of the microball solution is still uncertain, it will be first considered for the advanced market high-end ICs and the emerging market, such as advanced memories with a relatively small number of input/outputs (I/Os), about 150 pin counts. Growth Factors for the Bumping Market Development of wafer-bumping technology has been progressing rapidly side by side with development and upgrading of flip-chip packaging and related technologies since 1995. That is when Intel adopted flip-chip interconnection technology based on the solder-plating method for its MPU packages, driven by the need to meet the rapid increase in operating 3

4 Flip-Chip Bumping Services: Driving Value-Added Businesses frequency. Pentium 4, running at close to 3GHz, uses the 478 I/O counts flip-chip pin grid array (PGA). Thus, wafer-bumping technology has successfully expanded its application, which was previously limited to high-end devices for mainframes and servers, from the advanced market to high-volume MPUs as part of Intel's strategic move. In fact, this strategy has led, with the success of Intel's MPU as the de facto PC standard, to a concentration of cost-reduction efforts and technological breakthroughs in the entire flip-chip packaging infrastructure, including not only the waferbumping process but the buildup substrate used as an interposer. A number of technological advancements and solutions have accelerated the pervasiveness of the wafer-bumping technology into volume production of non-mpu devices. In particular, in the high-speed data communications market one of the future growth markets diverse flip-chip packaging solutions are being proposed at an accelerated rate. In ASIC/ASSP and DSP applications, the focus of technological development is moving to the flip-chip interconnection using the solder-plating-based wafer-bumping technology to reduce inductance or noise between the die and the interposer for increasing operating frequency and data processing speeds. Meanwhile, the plating Au-bumping method faces major challenges related to its limitations in terms of cost reduction and technological evolution. Development and upgrading efforts in the field of LCD driver packaging, traditionally using the plating Au method namely TCP, COF and COG center on commercialization of low-cost midsize and large LCDs to replace cathode-ray tube (CRT) displays. The cost reduction efforts will likely continue for a while, as led by LCD vendors in South Korea and Taiwan. In the process, it has become apparent that the plating Au-bumping method is close to its limit in further cost reduction, while it has technical difficulty in full-area bump formation, making it difficult to meet the needs for commercialization of SIP, including 3-D packaging. Gartner Dataquest predicts that the plating Au-bumping method will face slowing demand growth. Instead, the plating solder and related methods (plating lead-free, such as Sn-Ag) as well as other bumping methods will hold the key to accurate forecasting of wafer-bumping market growth, especially in what applications the wafer-bumping and die-bumping technologies based on these methods will be adopted. Flip-Chip Package Growth Forecast In 2001, the world semiconductor package market fell more than 10 percent, to 74 billion units. Figure 1 shows the breakdown of bare-die interconnections, with bump formation, in the overall market, and the unit shipment forecast. Notably, the bare-die interconnections' segment recorded an annual growth rate of about 10 percent in 2001, despite the general decline. The mixed results are also apparent from the compound annual growth rate (CAGR) on a unit basis between 2002 and 2006. While direct-chip attach (DCA) for the high-end market is expected to show a CAGR of negative 16.8 percent, flip chip in package shows an impressive 33.5 percent growth.

5 Figure 1 Flip-Chip and Other Bare-Die Connection Forecast, (2000-2006) Millions of Units 10,000 8,000 6,000 Others DCA COG TCP COF Flip Chip On Board Flip Chip in Package 4,000 2,000 0 2000 2001 2002 2003 2004 2005 2006 110460-00-01 The flip-chip in package category includes single-chip flip-chip packages such as flip-chip PGA, flip-chip land-grid array (LGA), and flip-chip ballgrid array (BGA). These are used in the advanced market, such as high speed MPUs and ASICs and DSPs for network servers, which will continue to rely on flip-chip packaging based on the plating solder-bumping method because of reliability and the ability to meet full-area bumping requirements. At the same time, fine-pitch ball-grid array (FBGA) used for multifunction mobile electronic equipment in the emerging market is expected to adopt pressure-welded or ultrasonic flip-chip packaging technology using the stud Au-bumping method as the SIP solution. As for the plating Au-bumping method, which faces limitations in terms of cost and technology, LCD driver package demand is destined to decline as LCD driver ICs will be embedded into LCD panels in accordance with the generation shift of key technology from the conventional amorphous thin film transistor (TFT) to low-temperature polysilicon or organic electroluminescent. COF is expected to show a 3.1 percent CAGR in units between 2002 and 2006, whereas TCP will have a CAGR of negative 14.6 percent. In the long run, the slowdown in the plating Au-bumping segment is a foregone conclusion. Value-Added Services by Wafer-Bumping Service Providers Flip-chip packaging technology is highly dependent on equipment and materials. In particular, wafer-bumping technology and its strategic

6 Flip-Chip Bumping Services: Driving Value-Added Businesses direction (applications and suitable market segments) are determined by the selection of a bumping method and flip-chip packaging equipment and materials (package substrate, underfill, and so on). It is difficult to convert one process to another. This demands a timely investment decision and requires considerable time and resources for commercialization. IDMs that do not have their own wafer-bumping process have to rely on outside service providers. Tables 1 through 3 show the recent changes in wafer-bumping service providers by bumping method. Tables 4 and 5 list leading IDMs that work with the studbumping and ball-bumping methods for high-density flip-chip packaging, including those providing bumping services. The capacity and wafer size are Gartner Dataquest estimates, and the data were gathered through primary and secondary research. Table 1 Plating Au Bumping: Wafer-Bumping Service Providers, LCD Package Country/Company Capacity (Wafers/Month) Diameter (mm) Bare-Die Assembly Germany PacTech 10,000 125-200 Yes Japan Casio Micronics 200,000 125-200 Yes Chisso (Sun Electronics) 60,000 125-200 Yes Citizen Watch 9,000 100-150 Yes Fujitsu Tohoku Electronics 5,000 150 Yes Singapore MicroFab Technology 20,000 125-200 No South Korea Microscale 5,000 125-200 No Switzerland EM Microelectronics-Marin 5,000 125-200 Yes Taiwan ASE 10,000 125 200 Yes Chipbond Technology 50,000 125-200 Yes FuPo Electronics 20,000 150-200 Yes Megic 15,000 125-200 No United States Aptos 3,000 125-200 Yes

7 Table 2 Plating Solder Bumping: Wafer-Bumping Service Providers, Flip-Chip Package Country/Company Capacity (Wafers/Month) Diameter (mm) Flip Chip Assembly China (Hong Kong) AIT 5,000 125-200 Yes Germany PacTech 8,000 125-300 Yes Japan Casio Micronics 8,000 125-200 No Chisso (Sun Electronics) 4,000 125-150 Yes Citizen Watch 11,000 100-150 Yes Fujitsu Tohoku Electronics 8,000 150-200 Yes Shinko Electronics 3,000 125-200 Yes Singapore MicroFab Technology 10,000 125-200 No South Korea Amkor Technology 3,000 150-200 Yes Switzerland EM Microelectronics-Marin SA 5,000 125-200 Yes Taiwan ASE 3,000 125-200 Yes Chipbond Technology 5,000 125-200 Yes FuPo Electronics 3,000 125-200 Yes Megic 3,000 125-200 No TSMC 5,000 200-300 No Unitive Taiwan 12,000 100 300 No United States Aptos 8,000 125 200 Yes Unitive 8,000 125 200 No Table 3 Printing Solder Bumping: Wafer-Bumping Service Providers Country/Company Capacity (Wafers/Month) Diameter (mm) Flip Chip Assembly South Korea Amkor 30,000 125 200 Yes Taiwan APack 8,000 150-200 Yes ASE 15,000 125-200 Yes SPIL 10,000 150-300 Yes United States Kulicke & Soffa 80,000 125-200 No

8 Flip-Chip Bumping Services: Driving Value-Added Businesses Table 4 Stud Au Bumping: IDM and Die-Bumping Service Providers Country/Company Japan Capacity (Millions of Units/Month) Diameter (mm) Flip Chip Assembly Fujitsu - - Yes Hitachi - - Yes Hitachi Hokkai Semiconductor - - Yes Matsushita 3.5 125-200 Yes NEC - - Yes Oki - - Yes Seiko Epson - - Yes Sharp - - Yes Shinko - - Yes Sony - - Yes Toshiba - - Yes Table 5 Ball-Attach Bumping: IDM and Wafer-Bumping Service Providers Country/Company Capacity (Wafers/Month) Diameter (mm) Flip Chip Assembly Japan Matsushita - - Yes NEC - - Yes Nippon Steel 3,000 125-200 No As seen from these tables, many SATS providers have established their own wafer-bumping technological base, either through licensing or in-house development, to provide a turnkey solution from wafer bumping to flip-chip packaging. Five years ago, the Flip-Chip Division of Kulicke & Soffa (formerly Flip Chip Technology) and Unitive were leading waferbumping service and related intellectual property (IP) providers. In addition, wafer-bumping service was available from only a handful of companies, including Fujitsu Tohoku Electronics, Citizen Watch and Casio Micronics. Today, the community has grown to as many as 30, including those at R&D level. At the same time, wafer-bumping service providers have been pouring money into capacity expansion on the basis of their own technologies. Notably, in the plating Au-bumping market, as the mainstream of PC display shifted from CRT to LCD in the past few years, capacity for LCD driver packaging continues to be in short supply. The market attracted several new entrants in alliance with LCD vendors, such as MicroScale of South Korea, Chipbond Technology and Megic of Taiwan, and MicroFab Technology of Singapore. Established plating Au wafer-bumping providers are also expanding production capacity, which is accelerating cost reduction. As for plating solder bumping, Unitive expanded its alliances on the strength of its proprietary technology for 300-mm wafer processes, in addition to leading SATS providers such as Amkor and ASE. Other wafer-

bumping service providers raised their capacity utilization rates with the steady growth of flip-chip packaging demand. Furthermore, foundries such as Taiwan Semiconductor Manufacturing Company (TSMC) and United Microelectronics (UMC) will likely find a source of additional value in plating solder-bumping technology and will make inroads into the SATS-dominated market. As they establish their presence, they will be able to offer "fab pack" services, ranging from silicon foundry services to wafer bumping as well as assembly and testing, thereby creating a "onestop shopping" service in the field of flip-chip packaging. This means standardization of flip-chip technology and customization for individual customers will progress simultaneously. The outcome will be cost reduction driven by scales of economy, which will lead to bottom-up expansion of the flip-chip packaging market. In fact, TSMC has already started wafer-bumping processes using plating and printing solder-bumping methods, while UMC deploys value-added business by contracting wafer-bumping service to Advanced Semiconductor Engineering (ASE), Silicon Precision Industries (SPIL) and Unitive in Taiwan, with a view to having its own wafer-bumping capability through licensing. It should be noted, however, that, although the market expands steadily (on both a value and unit basis) with the growing flip-chip packaging demand, wafer-bumping service is susceptible to deterioration of profitability because the number of wafers processed declines as larger-diameter wafers become pervasive to produce more dies per wafer. Thus, most wafer-bumping service providers are eyeing comprehensive services, including package assembly and foundry. Here, they have to differentiate themselves from others in terms of a turnkey solution that covers flip-chip packaging, not to mention creation of a higher valueadded service. Because flip-chip packaging is increasingly in demand in the next-generation emerging market in addition to the advanced market, capital spending related to wafer-bumping service is rising. This includes spending for advanced-packaging lithography equipment and flip-chip bonders, despite the sluggish semiconductor investment during the economic recession. In 2001, the advanced-packaging lithography equipment market grew 22.5 percent and reached US$76 million, and it is expected to record a 23 percent CAGR from 2002 through 2007. The flip-chip bonder market registered 1.5 percent growth and reached US$68 million in 2001, with a 20 percent CAGR projected for 2002-2007. Thus, the flip-chip packaging infrastructure will likely be established with the aid of active capital spending in packaging equipment. However, there is a caveat for IDMs that intend to build up the wafer-bumping business from scratch. While the process is much less costly than the fab process about 100 times less expensive the wafer-bumping process including the flip-chip line at about US$10 million must be amortized and can be a financial risk if overcapacity occurs and the operating rate declines substantially. Also, to enter the wafer-bumping service business, an IDM's own brand becomes a barrier to competing IDMs or original equipment manufacturers that need to outsource wafer-bumping service. For them, it 9

10 Flip-Chip Bumping Services: Driving Value-Added Businesses is important to offer outsourcing service to wafer-bumping service providers. Gartner Dataquest Perspective Wafer-bumping services are diversifying with the evolution of flip-chip packaging technology. In particular, the markets in which SATS's business prospers, such as Japan, Taiwan, South Korea and Singapore, provide spawning grounds for wafer-bumping service, which grows rapidly with increased outsourcing of assembly and testing activities. Intel effectively initiated application of flip-chip packaging to volume production by using flip-chip in package for its MPUs, which became widespread in the industry in 2002. At the same time, leading SATS providers, including Amkor and ASE, have been increasingly providing wafer level packaging capability by applying the plating based wafer-bumping process to redistribution of wafers. They are relying on the business model that targets customized SOC demand, which represents the advanced market, by leveraging economies of scale from plating-solder and leadfree-bumping solutions. In contrast, IDMs appear to focus on stud Au-bumping technology in an attempt to standardize their solution for the promising SIP market, which is highly cost sensitive. While the two markets are polarized and have little opportunity to merge, the multifunction mobile electronic equipment market based on high-speed data communication will demand that these markets move toward further standardization and convergence. Key Issue Who are the major players in the markets that define the manufacturing infrastructure? This document has been published to the following Marketplace codes: SEMC-WW-DP-0191 For More Information... In North America and Latin America: +1-203-316-1111 In Europe, the Middle East and Africa: +44-1784-268819 In Asia/Pacific: +61-7-3405-2582 In Japan: +81-3-3481-3670 Worldwide via gartner.com: www.gartner.com Entire contents 2002 Gartner, Inc. All rights reserved. Reproduction of this publication in any form without prior written permission is forbidden. The information contained herein has been obtained from sources believed to be reliable. Gartner disclaims all warranties as to the accuracy, completeness or adequacy of such information. Gartner shall have no liability for errors, omissions or inadequacies in the information contained herein or for interpretations thereof. The reader assumes sole responsibility for the selection of these materials to achieve its intended results. The opinions expressed herein are subject to change without notice. 110460