PROFET BTS 736 2 Smar igh-side Power Swich Two Channels: 2 x 40mΩ Saus Feedback Produc Summary Package Operaing olage bb(on) 4.75...41 Acive channels one wo parallel On-sae Resisance R ON 40mΩ 20mΩ Nominal load curren (NOM) 4.8A 7.3A Curren limiaion (SCr) 30A 30A P-DSO-20-9 General Descripion N channel verical power MOSFET wih charge pump, ground referenced CMOS compaible inpu and diagnosic feedback, monolihically inegraed in Smar SPMOS echnology. Providing embedded proecive funcions Applicaions µc compaible high-side power swich wih diagnosic feedback for 5, 12 and 24 grounded loads All ypes of resisive, inducive and capacive loads Mos suiable for loads wih high inrush currens, so as lamps Replaces elecromechanical relays, fuses and discree circuis Basic Funcions ery low sandby curren CMOS compaible inpu Fas demagneizaion of inducive loads Sable behaviour a undervolage Wide operaing volage range ogic ground independen from load ground Proecion Funcions Shor circui proecion Overload proecion Curren limiaion Thermal shudown Overvolage proecion (including load dump) wih exernal resisor Reverse baery proecion wih exernal resisor oss of ground and loss of bb proecion Elecrosaic discharge proecion (ESD) Diagnosic Funcion Diagnosic feedback wih open drain oupu Open load deecion in ON-sae Feedback of hermal shudown in ON-sae Block Diagram 1 1 2 2 bb ogic Channel 1 ogic Channel 2 PROFET 1 oad 1 2 oad 2 Semiconducor Group 1 of 14 2003-Oc-01
BTS 736 2 Funcional diagram overvolage proecion inernal volage supply logic gae conrol + charge pump curren limi clamp for inducive load BB 1 1 1 ESD emperaure sensor Open load deecion OAD 1 Channel 1 2 2 2 Conrol and proecion circui of channel 2 PROFET 2 Pin Definiions and Funcions Pin Symbol Funcion 1,10, 11,12, 15,16, 19,20 bb Posiive power supply volage. Design he wiring for he simulaneous max. shor circui currens from channel 1 o 2 and also for low hermal resisance 3 1 npu 1,2, acivaes channel 1,2 in case of 7 2 logic high signal 17,18 1 Oupu 1,2, proeced high-side power oupu 13,14 2 of channel 1,2. Design he wiring for he max. shor circui curren 4 1 Diagnosic feedback 1,2 of channel 1,2, 8 2 open drain, low on failure 2 1 Ground 1 of chip 1 (channel 1) 6 2 Ground 2 of chip 2 (channel 2) 5,9 N.C. No Conneced Pin configuraion (op view) bb 1 20 bb 1 2 19 bb 1 3 18 1 1 4 17 1 N.C. 5 16 bb 2 6 15 bb 2 7 14 2 2 8 13 2 N.C. 9 12 bb bb 10 11 bb Semiconducor Group 2 2003-Oc-01
BTS 736 2 Maximum Raings a T j = 25 C unless oherwise specified Parameer Symbol alues Uni Supply volage (overvolage proecion see page 4) bb 43 Supply volage for full shor circui proecion bb 24 T j,sar = -40...+150 C oad curren (Shor-circui curren, see page 5) self-limied A oad dump proecion 1) oaddump = A + s, A = 13.5 oad dump 3) 60 R 2) = 2 Ω, d = 200 ms; = low or high, each channel loaded wih R = 9.0 Ω, Operaing emperaure range Sorage emperaure range T j T sg -40...+150-55...+150 C Power dissipaion (DC) 4) T a = 25 C: P o 3.8 W (all channels acive) T a = 85 C: 2.0 Maximal swichable inducance, single pulse bb = 12, T j,sar = 150 C 4), = 4.0 A, E AS = 296 mj, 0 Ω one channel: Z 19.0 m = 6.0 A, E AS = 631 mj, 0 Ω wo parallel channels: 17.5 see diagrams on page 9 Elecrosaic discharge capabiliy (ESD) : ESD 1.0 k (uman Body Model) : 4.0 ou o all oher pins shored: 8.0 acc. M-D883D, mehod 3015.7 and ESD assn. sd. S5.1-1993 R=1.5kΩ; C=100pF npu volage (DC) -10... +16 Curren hrough inpu pin (DC) Curren hrough saus pin (DC) ±2.0 ±5.0 ma see inernal circui diagram page 8 Thermal Characerisics Parameer and Condiions Symbol alues Uni min yp Max Thermal resisance juncion - soldering poin 4),5) each channel: R hjs 12 K/W juncion - ambien 4) one channel acive: all channels acive: R hja 40 33 1) Supply volages higher han bb(az) require an exernal curren limi for he and saus pins (a 150Ω resisor for he connecion is recommended. 2) R = inernal resisance of he load dump es pulse generaor 3) oad dump is seup wihou he DUT conneced o he generaor per SO 7637-1 and D 40839 4) Device on 50mm*50mm*1.5mm epoxy PCB FR4 wih 6cm 2 (one layer, 70µm hick) copper area for bb connecion. PCB is verical wihou blown air. See page 14 5) Soldering poin: upper side of solder edge of device pin 15. See page 14 Semiconducor Group 3 2003-Oc-01
BTS 736 2 Elecrical Characerisics Parameer and Condiions, each of he wo channels Symbol alues Uni a Tj = -40...+150 C, bb = 12 unless oherwise specified min yp Max oad Swiching Capabiliies and Characerisics On-sae resisance ( bb o ); = 2 A, bb 7 each channel, T j = 25 C: T j = 150 C: R ON 36 67 40 75 mω wo parallel channels, T j = 25 C: see diagram, page 10 Nominal load curren one channel acive: wo parallel channels acive: Device on PCB 6), Ta = 85 C, Tj 150 C Oupu curren while disconneced or pulled up 7) ; bb = 30, = 0, see diagram page 8 Turn-on ime 8) o 90% : Turn-off ime o 10% : R = 12 Ω Slew rae on 8) T j = -40 C: 10 o 30%, R = 12 Ω T j = 25 C...150 C: Slew rae off 8) T j = -40 C: 70 o 40%, R = 12 Ω T j = 25 C...150 C: (NOM) 4.4 6.7 18 4.8 7.3 20 A (high) 2 ma on off 50 50 d/d on 0.15 0.15 -d/d off 0.15 0.15 100 120 200 250 µs 1 0.8 /µs 1 0.8 /µs Operaing Parameers Operaing volage Tj=-40 T j =25...150 C: T j =-40 C: T j =25...150 C: T j =-40 C...25 C: T j =150 C: Overvolage proecion 9) bb = 40 ma Sandby curren 10) = 0; see diagram page 10 eakage oupu curren (included in bb(off) ) = 0 Operaing curren 11), = 5, = 1 + 2, one channel on: wo channels on: bb(on) 4.75 bb(az) 41 43 bb(off) 47 10 41 43 52 16 50 µa (off) 1 10 µa 0.8 1.6 1.4 2.8 ma 6) Device on 50mm*50mm*1.5mm epoxy PCB FR4 wih 6cm 2 (one layer, 70µm hick) copper area for bb connecion. PCB is verical wihou blown air. See page 14 7) no subjec o producion es, specified by design 8) See iming diagram on page 11. 9) Supply volages higher han bb(az) require an exernal curren limi for he and saus pins (a 150Ω resisor for he connecion is recommended). See also ON(C) in able of proecion funcions and circui diagram on page 8. 10) Measured wih load; for he whole device; all channels off 11) Add, if > 0 Semiconducor Group 4 2003-Oc-01
BTS 736 2 Parameer and Condiions, each of he wo channels Symbol alues Uni a Tj = -40...+150 C, bb = 12 unless oherwise specified min yp Max Proecion Funcions 12) Curren limi, (see iming diagrams, page 12) Tj =-40 C: Tj =25 C: Tj =+150 C: Repeiive shor circui curren limi, T j = T j each channel wo parallel channels (see iming diagrams, page 12) niial shor circui shudown ime T j,sar =25 C: (see iming diagrams on page 12) Oupu clamp (inducive load swich off) 13) a ON(C) = bb -, = 40 ma Tj =-40 C: Tj =25 C...150 C: (lim) 40 33 23 (SCr) 49 41 29 30 30 60 48 35 off(sc) 1.7 ms ON(C) 41 43 Thermal overload rip emperaure T j 150 C Thermal hyseresis T j 10 K Reverse Baery Reverse baery volage 14) - bb 32 Drain-source diode volage (ou > bb) - ON 600 m = - 4.0 A, Tj = +150 C 47 52 A A 12) negraed proecion funcions are designed o preven C desrucion under faul condiions described in he daa shee. Faul condiions are considered as "ouside" normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. 13) f channels are conneced in parallel, oupu clamp is usually accomplished by he channel wih he lowes ON(C) 14) Requires a 150 Ω resisor in connecion. The reverse load curren hrough he inrinsic drain-source diode has o be limied by he conneced load. Power dissipaion is higher compared o normal operaing condiions due o he volage drop across he drain-source diode. The emperaure proecion is no acive during reverse curren operaion! npu and Saus currens have o be limied (see max. raings page 3 and circui page 8). Semiconducor Group 5 2003-Oc-01
BTS 736 2 Parameer and Condiions, each of he wo channels Symbol alues Uni a Tj = -40...+150 C, bb = 12 unless oherwise specified min yp Max Diagnosic Characerisics Open load deecion curren, (on-condiion) each channel (O)1 100 900 ma npu and Saus Feedback 15) npu resisance R 2.5 3.5 6 kω (see circui page 8) npu urn-on hreshold volage (T+) 1.7 3.2 npu urn-off hreshold volage (T-) 1.5 npu hreshold hyseresis (T) 0.5 Off sae inpu curren = 0.4 : (off) 1 50 µa On sae inpu curren = 5 : (on) 20 50 90 µa Delay ime for saus wih open load afer swich d( O4) 100 520 900 µs off; (see diagram on page 13) Saus invalid afer posiive inpu slope (open load) Saus oupu (open drain) Zener limi volage = +1.6 ma: low volage = +1.6 ma: d() 500 µs (high) (low) 5.4 6.1 0.4 15) f ground resisors R are used, add he volage drop across hese resisors. Semiconducor Group 6 2003-Oc-01
BTS 736 2 Truh Table Channel 1 npu 1 Oupu 1 Saus 1 Channel 2 npu 2 Oupu 2 Saus 2 Normal operaion Open load Overemperaure level level BTS 7362 Z = "ow" evel X = don' care Z = high impedance, poenial depends on exernal circui = "igh" evel Saus signal valid afer he ime delay shown in he iming diagrams Parallel swiching of channel 1 and 2 is easily possible by connecing he inpus and oupus in parallel. The saus oupus 1 and 2 have o be configured as a 'Wired OR' funcion wih a single pull-up resisor. Terms bb bb 1 1 1 1 3 4 1 1 eadframe bb PROFET 1 Chip 1 1 2 1 1 17,18 ON1 1 2 2 2 2 7 8 2 2 eadframe bb PROFET 2 Chip 2 2 6 2 2 13,14 ON2 2 R 1 R 2 eadframe ( bb ) is conneced o pin 1,10,11,12,15,16,19,20 Exernal R opional; wo resisors R 1, R 2 = 150 Ω or a single resisor R = 75 Ω for reverse baery proecion up o he max. operaing volage. Semiconducor Group 7 2003-Oc-01
BTS 736 2 npu circui (ESD proecion), 1 or 2 R ESD-ZD The use of ESD zener diodes as volage clamp a DC condiions is no recommended. Saus oupu, 1 or 2 R (ON) +5 Overvol. and reverse ba. proecion + 5 R R R Z1 ogic R Signal Z2 PROFET + bb R oad oad Z1 = 6.1 yp., Z2 = 47 yp., R = 150 Ω, R = 15 kω, R = 3.5 kω yp. n case of reverse baery he load curren has o be limied by he load. Temperaure proecion is no acive ESD- ZD ESD-Zener diode: 6.1 yp., max 5.0 ma; R (ON) < 375 Ω a 1.6 ma. The use of ESD zener diodes as volage clamp a DC condiions is no recommended. Open-load deecion 1 or 2 ON-sae diagnosic Open load, if ON < R ON (O) ; high + bb nducive and overvolage oupu clamp, 1 or 2 ON ON Z + bb ogic uni Open load deecion ON disconnec ON clamped o ON(C) = 47 yp. Power bb PROFET bb Any kind of load. n case of = high is - (T+). Due o > 0, no = low signal available. Semiconducor Group 8 2003-Oc-01
BTS 736 2 disconnec wih pull up nducive load swich-off energy dissipaion E bb bb E AS bb PROFET = bb PROFET Z { E oad E E R Any kind of load. f > - (T+) device says off Due o > 0, no = low signal available. Energy sored in load inducance: R bb disconnec wih energized inducive load E = 1 /2 2 While demagneizing load inducance, he energy dissipaed in PROFET is high bb E AS = E bb + E - E R = ON(C) i () d, wih an approximae soluion for R > 0 Ω: PROFET E AS = R ( 2 R bb + (C) ) ln (1+ (C) ) bb For inducive load currens up o he limis defined by Z (max. raings and diagram on page 9) each swich is proeced agains loss of bb. Consider a your PCB layou ha in he case of bb disconnecion wih energized inducive load all he load curren flows hrough he connecion. Maximum allowable load inducance for a single swich off (one channel) 4) = f ( ); T j,sar = 150 C, bb = 12, R = 0 Ω Z [m] 1000 100 10 1 2 3 4 5 6 7 8 9 10 11 12 [A] Semiconducor Group 9 2003-Oc-01
BTS 736 2 Typ. on-sae resisance R ON = f ( bb,t j ); = 2 A, = high R ON [mohm] 80 70 Tj = 150 C 60 50 40 30 25 C -40 C 20 10 3 5 7 9 30 40 bb [] Typ. sandby curren bb(off) = f (T j ); bb = 9...34, 1,2 = low bb(off) [µa] 45 40 35 30 25 20 15 10 5 0-50 0 50 100 150 200 T j [ C] Semiconducor Group 10 2003-Oc-01
BTS 736 2 Timing diagrams Boh channels are symmeric and consequenly he diagrams are valid for channel 1 and channel 2 Figure 1a: bb urn on: 1 Figure 2b: Swiching a lamp: 2 bb 1 2 1 open drain 2 open drain Figure 2a: Swiching a resisive load, urn-on/off ime and slew rae definiion: The iniial peak curren should be limied by he lamp and no by he curren limi of he device. Figure 2c: Swiching an inducive load 90% on d/doff 10% d/don off (O) *) if he ime consan of load is oo large, open-load-saus may occur Semiconducor Group 11 2003-Oc-01
BTS 736 2 Figure 3a: Turn on ino shor circui: shu down by overemperaure, resar by cooling 1 oher channel: normal operaion Figure 4a: Overemperaure: Rese if T j <T j 1 (lim) (SCr) off(sc) T J eaing up of he chip may require several milliseconds, depending on exernal condiions Figure 3b: Turn on ino shor circui: shu down by overemperaure, resar by cooling (wo parallel swiched channels 1 and 2) 1/2 Figure 5a: Open load: deecion in ON-sae, open load occurs in on-sae + 1 2 2x (lim) d( O) d( O) (SCr) 1/2 off(sc) normal open normal 1 and 2 have o be configured as a 'Wired OR' funcion 1/2 wih a single pull-up resisor. d( O) = 10 µs yp. Semiconducor Group 12 2003-Oc-01
BTS 736 2 Figure 5b: Open load: urn on/off o open load d(o4) Semiconducor Group 13 2003-Oc-01
BTS 736 2 Package and Ordering Code Sandard: P-DSO-20-9 Sales Code BTS 736 2 Ordering Code Q67060-S7011-A2 All dimensions in millimeres Published by nfineon Technologies AG, S.-Marin-Srasse 53, D-81669 München nfineon Technologies AG 2001 All Righs Reserved. Aenion please! The informaion herein is given o describe cerain componens and shall no be considered as a guaranee of characerisics. Terms of delivery and righs o echnical change reserved. We hereby disclaim any and all warranies, including bu no limied o warranies of non-infringemen, regarding circuis, descripions and chars saed herein. nfineon Technologies is an approved CECC manufacurer. nformaion For furher informaion on echnology, delivery erms and condiions and prices please conac your neares nfineon Technologies Office in Germany or our nfineon Technologies Represenaives worldwide (see address lis). Definiion of soldering poin wih emperaure T s : upper side of solder edge of device pin 15. Pin 15 Prined circui board (FR4, 1.5mm hick, one layer 70µm, 6cm 2 acive heasink area) as a reference for max. power dissipaion P o, nominal load curren (NOM) and hermal resisance R hja Warnings Due o echnical requiremens componens may conain dangerous subsances. For informaion on he ypes in quesion please conac your neares nfineon Technologies Office. nfineon Technologies Componens may only be used in life-suppor devices or sysems wih he express wrien approval of nfineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem, or o affec he safey or effeciveness of ha device or sysem. ife suppor devices or sysems are inended o be implaned in he human body, or o suppor and/or mainain and susain and/or proec human life. f hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered. Semiconducor Group 14 2003-Oc-01