Advances in stacked-die packaging

pg.10-15-carson-art 16/6/03 4:12 pm Page 1 The stacking of die within IC packages, primarily Chip Scale Packages (CSP) Ball Grid Arrays (BGAs) has evolved rapidly over the last few years. The now standard two-die-stack CSP was introduced three years ago and the industry already needs four to six-die-stack in the same or thinner package. Personal electronics such as next generation cell phones with aggressive functionality and time to market requirements are driving the evolution of stacked-die packaging at a feverish pace. This paper demonstrates some of the advances in stacked die packaging technology required to qualify for production of two package types: a 1.4mm maximum thickness 5-die-stack CSP and a 1.2mm maximum 2-die-stack CSP package requiring leadfree solder balls at 0.5mm pitch. Key enabling technologies for future advanced stacked - die packages and trends are briefly discussed. Flynn Carson & Marcos Karnezos ChipPAC Inc. Fremont, CA USA Key words: Stacked die packaging, Wafer thinning, Lead- free, 0.5mm ball pitch Advances in stacked-die packaging Introduction By the end of year 1999 two-die-stack packages, typically including a Flash and SRAM type memory, were qualified and put into production. Many hundreds of millions of these two-diestacks, typically in a 1.4mm maximum package thickness CSP, have been produced to date by several manufacturers. This package has become a commodity product and for good reason: compared to two individual single CSPs, it is smaller, lighter, and has lower cost. The success of this product has driven end users to request more and more of a good thing, meaning more and more die in the same physical package size. The increased memory requirement of next generation cellular phones and other handheld consumer products has driven the need for diestacks with four or more chips. Some of these stacks include die of the same size that require a spacer to enable wire bonding. Wire bond interconnect is still the lowest cost and most flexible method of assembling such stacked-die packages. Advances in die stacking technology have enabled the qualification and production of 4-die + 1-spacer die (5- total die) in 1.4mm maximum package thickness CSPs (see Figure 1). Advancements in die thinning, die attach, and wire bonding processes [2] were required to produce this package type. Another trend in stacked-die packaging is to incorporate device types other than memory into the stacked-die CSP. Memory devices usually have lower I/O and package ballcount. Even CSPs with 4- stacked memory die usually have ballcounts less than 100. Memory devices usually have bond pads and consequently wire bonds on only two sides of the die, however, ASIC or logic devices usually have much higher I/O and bond pads on all four sides of the die. The requirement to provide this higher I/O and ballcount requirement in the same footprint package drives the ball pitch from the 0.8mm standard for most CSPs down to 0.5mm pitch. Figure 2 shows Figure 1: Schematic of 1.4mm max. 4 + 1 die-stack CSP Figure 2: Schematic of 1.2mm max. 2-die-stack CSP with 0.5mm ball pitch a schematic of such a higher ballcount, fine ball pitch 2-diestack CSP. The concern with fine ball pitch stacked-die CSPs is not only the package level reliability but also the board or system level reliability. 0.5mm ball pitch reduces the ball diameter and the collapsed height after it is board mounted compared to 0.8mm pitch. Reduction of the overall package thickness and conversion to lead-free solder balls are techniques that can increase the board and system level reliability with fine ball pitch packages. The stacking of thinner die into thinner packages to meet the seemingly never ending trend toward product miniaturization with increased functionality requires further advancements in die thinning, die attach, and wire bonding/ interconnect technology as well as advancements in mold compound and substrate materials. Methodology of package development The typical methodology employed to develop new packages consists of developing a master plan including some analysis of risk, focusing on the necessary enabling technologies to minimize the risk moving forward, then executing an internal qualification of the package utilizing a test vehicle and proving such a package is reliable. The test vehicle or vehicles should be 10 Global SMT & Packaging March 2003 www.globalsmt.net

pg.10-15-carson-art 16/6/03 4:12 pm Page 2 Figure 4: Effect of polishing after grind on die shear strength (100µm wafer thickness, 200mm wafer) Figure 3: Wafer thinning roadmap for 200mm and 300mm wafers representative of the typical application range. However, due to the fast paced evolution of these stacked-die packages and the short time to market (concept to production is typically less than six months), the approach has been modified to develop, characterize and essentially qualify the enabling technology components (such as 0.10mm die thinning or 0.075mm wire bond loop height) that can be integrated together to immediately qualify a package for mass production. Thus, the qualification of such advanced stacked-die packages can be broken up into the process or material technology that enables it. In the case of the 1.4mm thick 4 + 1 diestack CSP the key enabling technology is wafer thinning, die attach process, materials, and wire bond process. For the 1.2mm thick 0.5mm ball pitch CSP the key enabling technology is 300mm wafer backgrinding, solder ball attach process, lead-free compatible material set, and laminate substrate technology. Wafer thinning The number of die that needs to be stacked within the package and the overall package thickness determine the die thickness required to enable that package. For instance, the first 2-die-stacks in 1.4mm thickness packages required die thickness of about 0.170mm or almost 7 mils. However, 2-die + 1-spacer die stacks (or 3-diestacks) in the same package thickness required about 0.140mm thickness, then putting the same stack in a 1.2mm package thickness drove the die thickness to 0.125mm or 5 mils. 1.4mm thick 3 die + 1 spacer die (or 4-die-stacks) CSPs can be achieved with 5 mil die thickness as well by slightly thickening the mold cap of the package which contains the dice and making the substrate thinner. However, the 4-die + 1-spacer die (or 5-die-stack CSP) requires 0.100mm or 4 mil thick die to make a 1.4mm thick package. Of course, thinner versions of the 2, 3, 4, and 5-die-stack packages mentioned above will require even thinner die. Figure 3 shows the capability trend of wafer thinning to support advanced stacked-die packaging. Although the majority of devices are still produced on 200mm diameter wafers, 300mm diameter wafers are starting to get fabricated especially for ASIC or higher density and performance devices. Stacked die packages with high ballcount and 0.5mm ball pitch with die from 300mm wafers are assembled today and will become more prevalent in the future. Difficulties increase as 200mm wafers are background below 0.125mm thick. Even the best conventional Figure 5: Backside of wafer after polishing backgrind equipment that employ mechanical grinding run into problems below this thickness unless they do wafer polishing. Furthermore, the same equipment cannot handle 300mm wafers. Thinning below 0.125mm for 200mm wafers and below 0.150mm for 300mm wafers requires wafer polishing or an etching process to relieve the stress of mechanical backgrinding otherwise the backside wafer stress and roughness is sufficient to cause wafer or die crack during the assembly process or during reliability stress. Polishing with a slurry is closest to conventional mechanical wafer backgrind and can be integrated into conventional 300mm backgrinders. This has the additional advantage of minimizing the handling of such large, extremely thin wafer. At such thickness wafers sag if not supported properly and mechanical shock can cause improperly supported wafer to break [3]. Competing die thinning technologies that relieve stress such as plasma etch or chemical processing typically do not integrate well with conventional backgrind equipment and also have higher operating cost or involve hazardous chemicals not used in packaging assembly. Therefore, an in-line backgrind, polish, and saw-tape mount was developed and utilized to meet wafer thinning capability roadmap and enable stacked-die packages beyond the limits of conventional mechanical backgrinding equipment. After such equipment was developed, the process to backgrind and saw 4 mil thick wafers (required for 1.4mm 4 + 1 die stack CSP) had to be characterized, qualified, and verified. Die strength test was used to determine the amount of polishing required to relieve stress due to grinding. Figure 4 shows the die strength as ground and then after subsequent polishing removing progressively more material. As ground, the die is weaker if sheared parallel to the grind marks (X-axis) as compared to shear strength normal to the grind direction (Y-axis). After 2µm of polishing the die shear directional dependence is removed and the impact of the grinding induced stress is www.globalsmt.net March 2003 Global SMT & Packaging 11

pg.10-15-carson-art 16/6/03 4:12 pm Page 3 Figure 6: 4 + 1 Die stack CSP showing die edge to bond pad space removed. This is also evident in the pictures of Figure 5. After backgrind and polish of 4 mil thick wafers was characterized, sawing process was verified. 2-step sawing is used for thinner wafers whereby the first cut made into the wafer is with a wider blade and less than 50% of the wafer thickness, then the rest of the wafer thickness is sawn within the first cut using a thinner width blade. This process minimized die backside edge chipping and cracking which can lead to die crack during assembly and reliability test. Sawing process was optimized for 4 mil thick wafer and 300mm diameter by evaluating the impact of sawing feed rate, blade type, and cut depth. Finally, although the process was developed on blank or mechanical die, it was verified using wafers from various customers and device types (such as memory and logic). The result of this verification was positive and no issues were seen. The process for backgrind, polish, and saw of 4 mil thick die was verified and readied for customer qualification and package production. Dia attach The die attach process is one of the most critical to the success of developing advanced stacked-die packages. The die attach must be thin and have tight tolerance in order for the die-stack to fit within the mold cap. Also, which die configurations can be stacked are dependent on the die attach process and controlling the fillet. In addition, the nominal die attach thickness and material must be chosen to allow for highest reliability without damaging the active circuit surface of the lower die in a die-stack. Even for 4 mil thick die, die attach epoxy pastes can be used for die attach. Below this thickness and for very large die (over 12mm on a side) film type die attach is usually recommended since die warpage and epoxy coverage become issues as die gets larger or thinner. The advantages of epoxy paste are that it fits nicely into the current packaging infrastructure (most IC packages use epoxy paste for die attach) and it also has better reliability. Even with 4 + 1 die stack it is possible to achieve preconditioning Level 2 performance with 260 C reflow. This level is more difficult to achieve with die attach films. The epoxy used between die has a special soft filler material which cannot damage the lower die active surface. A disadvantage of paste is that allowance must be made for the epoxy fillet at the edge of the die. This is required to assure adequate coverage of epoxy underneath the die and good reliability. As a result, the standard design rule is that there must be a 0.250mm or 10 mil space between the edge of the top die to the bond pads on the bottom die in a die stack configuration (see Figure 6). However, many customers desire a tighter specification Figure 7: Process used to achieve down to 0.125mm space between die edge to bond pad such that this space can be decreased to 0.125mm or 5 mils. The 4 + 1 die-stack CSP developed for production had a 0.125mm space requirement. To meet this specification a variation of the standard process was implemented. With the standard process, the top-3 die in a stack such as that depicted in Figure 6 would be die attached and then wire bonded in one pass. However, in order to meet tighter specification, the lower die is attached and wire bonded prior to the upper die being attached and wire bonded (see Figure 7). Figure 8 shows a top view in which the 0.125mm space between the edge of the top die and the bond pads of the lower die can be clearly seen. Using this process, the same specification usually acheived using film is met using paste die attach. In order to pass lead-free preconditioning and subsequent package level reliability test, die attach is one of the key factors. The die attach material and process must be able to maintain adhesion and not delaminate during the 260 C reflow after moisture soak. Figure 9 shows the result of lead-free reliability test on a 4 + 1 die stack CSP with the aforementioned die attach process. Preconditioning (MRT) L2 with 260 C reflow passed as well as subsequent package level temperature cycle. This package also passed more comprehensive customer qualification which included preconditioning, biased HAST, high temperature storage, thermal shock, and temperature cycling with larger sample size. Wire bonding Wire bonding, as the preferred low cost interconnect technology, is a key enabler for advanced stacked-die package. In advanced stacked-die packages die thickness, die attach, and wire loops are budgeted to the micrometer in order to fit the stack within the mold cap. Therefore wire Figure 8: Top die of 4 + 1 die stack showing 0.125mm clearance between die edge and bond pad on lower die 12 Global SMT & Packaging March 2003 www.globalsmt.net

pg.10-15-carson-art 16/6/03 4:12 pm Page 4 Figure 11: Characterized wire bonding capability by die thickness and die overhang Figure 9: Reliability data for 4 + 1 die stack CSP Figure 12: Example of bonding on 1.6mm die overhang with 0.125mm thick die. Figure 10: Photo of 4 + 1 die stack CSP showing actual wire bonding and loop formation. loop heights need to be very tightly controlled within nominal heights and as low as possible. Referring to Figure 6, it is clear that minimizing the wire loop height to the top die is critical to fitting the die stack within the mold cap. Reverse bonding or stitch bond-on-ball bonding is utilized to lower wire loop height to about 0.075mm or 3 mils nominal and also create space between the top and the lower wire loops such that the package can be molded without wire shorts due to wire sweep (see Figure 10). Reverse bonding also allows for shorter bond finger pads on the package substrate which is effective in shrinking the size of the package relative to the die (less clearance between die edge and package edge is required). Standard forward bonding can usually be utilized for the lower die, even with bonding in between two dice with a 4 mil thick spacer die in between (4 mil die with die attach material on top and bottom creates at least 6 mil (0.15mm) gap between dice). In most die-stack configurations, the die may be overhanging the die below and also require wire bonding. This overhang is evident in Figure 6 on the 2nd die (above the spacer die) and also in Figure 10 that is an actual photo of the die stack in Figure 6. Therefore, which die configurations can be stacked is determined by how much die overhang can be accommodated during wire bonding. As the die becomes thinner the overhang distance becomes less and it can be a real limiting factor for advanced stacked-die packages. Figure 11 shows the result of characterizing the maximum overhang distance that can be wire bonded based on die thickness. For 0.10mm thick die or thinner reverse bonding requires a shorter overhang due to the double bonding step required by ball and stitch processes. The reliability data shown in Figure 9 are evidence that keeping within the recommended overhang capability limits yields a reliable package. Figure 12 shows a 3 + 1 die stack package (0.125mm or 5 mil thick die) with wire bond on about 1.6mm of die overhang. Expected electrical test yields of this device were achieved and reliability test is underway by the customer. 0.5mm solder ball pitch As mentioned before, higher ball count CSPs with ASIC and memory or other device types stacked within are driving 0.5mm solder ball pitch. There are also some cases of 0.75mm and 0.65mm ball pitch stacked die CSPs since some end users have difficulty routing boards for CSPs with 0.5mm pitch. However, from a package manufacturing standpoint, such 0.5mm pitch can be produced with very high assembly yields. One of the key processes is ball attach. For mass production it is important to have almost no rework or subsequent reflow after first pass solder ball attach reflow. Only one rework reflow is allowed per package and it is an undesirable additional process. No yield loss due to solder ball mount can be tolerated in order to achieve the expected assembly yields of over 99.95%. Therefore, very high yielding first pass solder ball mount yields are a must. The solder ball mount process was evaluated and optimized for 0.5mm ball pitch with a lead-free 0.3mm ball. The leadfree ball requires a higher peak temperature reflow (255 C), which can create more package warpage and ball mount difficulties. Therefore, some characteristics of the flux dotting process had to be www.globalsmt.net March 2003 Global SMT & Packaging 13

pg.10-15-carson-art 16/6/03 4:13 pm Page 5 Figure 13: Optimization of first pass yield for 0.5mm pitch lead-free solder ball attach. Figure 15: 13x13mm 341 ball 1.2mm thick 0.5mm ball pitch 2-diestack CSP package reliability data. Figure 14: Design rule of qualified 0.5mm ball pitch package versus typical 0.8mm pitch package substrate. modified to achieve the highest possible yields (see Figure 13). 0.5mm ball pitch stacked die CSP BGAs typically require more advanced laminate substrate design rules and technology than typical 0.8mm ball pitch CSP applications. The routing of the 0.5mm pitch substrate is difficult and usually on a few ball rows can be routed fan-in or fan-out, even utilizing advanced trace line and space rules as well as small laser vias and capture pads. Depopulated ball rows are usually utilized in order to route 0.5mm ball pitch CSP BGAs cost effectively. Without depopulated ball rows, via-in-pad substrate technology, which is higher cost and less proven, needs to be utilized in order to route. Figure 14 shows the substrate design rules of the 1.2mm thick 0.5mm pitch 2- die stack CSP BGA that was qualified for production compared to typical 0.8mm ball pitch CSP substrate. 0.5mm ball pitch packages can utilize lead-free solder balls to assure acceptable board and system level reliability performance. Regardless if leadfree solder balls are utilized, the package material set needs to be lead-free compatible for future conversion to lead free solder if required. Material sets do exist that can pass even preconditioning Level 1 with 260 C reflow requirement and subsequent package level reliability. The 1.2mm thick 0.5mm ball pitch 2-die-stack package developed for production (13x13mm, 341 ball, 9x9mm bottom die) passed this requirement as can be seen in Figure 15. The above qualified package was also subjected to board level temp cycle, destructive bend test, and drop test. The board to which packages were mounted was 4-layers and 0.031 inches thick (0.765mm). Packages with both 0.21mm substrate / 0.65mm mold cap / 0.30mm ball and 0.26mm substrate / 0.60mm mold cap / 0.30mm ball were mounted to boards. SnAgCu lead-free solder ball was employed. The packages with the thicker substrate and thinner mold cap performed better. The characteristic life (63.2% population failure) for the better performing package structure: 40 to 125 C Temp Cycle = 3263 cycles (first failure >1000 cycles) Destructive Bend Test = 15.8mm Drop Test (6 meters) = 491 cycles Future developments To enable thinner stacked-die packages or more stacked-die within the same package thickness the following processes and technology is being developed: Wafer thinning technology per Figure 3. Film die attach to stabilize die attach thickness and die warpage for very thin die. Alternative die spacer technology using paste or film. Extend wire bond overhang capability. Forward wire bond with 0.075mm loop height. Staggered wire bond with <0.125mm loop height. Lower wire sweep molding compounds and methods to fill smaller gaps without mold voids. Via in pad technology for fine ball pitch. 0.4mm ball pitch capability Higher performance and green laminate materials Very thin core laminate substrates (down to 0.050mm core) 2 to 6- layer Conclusions Advances in stacked die packaging technology have enabled the development and qualification of 4-die + 1- spacer die stack (5-die) CSP packages and 0.5mm solder ball pitch lead-free, high I/O, CSPs. These packages can meet even the most stringent package and board or system level reliability requirements. These packages and others utilizing the same technology are already starting mass production. The key enabling technology pieces that are integrated into these packages are: Wafer thinning in-line process with polishing to relieve stress. Die attach process and 14 Global SMT & Packaging March 2003 www.globalsmt.net

pg.10-15-carson-art 16/6/03 4:13 pm Page 6 materials to enable 0.125mm space from die edge to bond pad edge on die below. Wire bond technology enabling low reverse wire loop and bonding on die overhang. 0.5mm solder ball attach optimization and material set and assembly process that can meet even MSL Level 1 requirement. Future work will be focused on wafer thinning (0.075mm and below) as well as die attach film and other enabling technologies to realize packages such as 1.2mm 4 and 5 die stack packages to meet the demands of fast evolving customer and end user application requirements. Dr. Karnezos, Chief Technology Officer at ChipPAC, has been 24 years in the electronics industry. Served as VP of Technology at ASAT and Signetics in packaging, at Hewlett Packard Labs managed development of x-ray lithography and soft radiation windows, and at National Semiconductor Magnetic Bubble Memory development. He has numerous inventions and publications in the fields of packaging, lithograpghy and bubble memories. Received his PhD from Carnegie Mellon University in Ultra Low Temperature Solid State Physics. Acknowledgements ChipPAC Korea Ltd. Research and Development as well as CSP Production Engineering are primarily responsible for all of the development and implementation of such developments into mass production. Special thanks to Kenny Lee, IS Yoon, Dr. Geunsik Kim, and HC Choi from the R&D Organization as well as HC Han, HK Jin, and DW Son from the Production Engineering group. References [1] Marcos Karnezos et. al, System in a Package (SIP) Benefits and Technical Issues, Proceedings of APEX, San Diego, January 16-18, 2002, pp. S15-1-1 to 6. [2] Flynn Carson et.al, Stacked Die Packaging Interconnect Challenges, Proceedings of K&S Advanced Technology Symposium at Semicon West, July 18, 2002. [3] Flynn Carson and Dr. Geunsik Kim, Die Strength of Very Thin 300mm Wafers, Proceedings Meptec Thin Wafer Handling Conference, February 21, 2002. www.globalsmt.net March 2003 Global SMT & Packaging 15