Design of basic digital circuit blocks based on an OFET device charge model

Vol. 34, No. 5 Journal of Semiconductors May 2013 Design of basic digital circuit blocks based on an OFET device charge model Shen Shu( 沈澍 ) School of Computer Science & Technology, Nanjing University of Posts and Telecommunication, Nanjing 210003, China Abstract: An OFET charge model, as well as its parameter extraction method are presented. The fitting results are also discussed and different OFET model characters are compared. Some basic OFET based digital circuit blocks, including the inverter, NAND, and ring oscillator are also developed, which would be considered to be helpful to the design of relevant applications. Key words: OFET; SPICE; ADS; inverter; NAND; ring oscillator DOI: 10.1088/1674-4926/34/5/055003 EEACC: 2570 1. Introduction In the last decades, both academia and industries focused their interests on the development of electronic devices based on polymers and organic films. Mass printing technologies are promising technologies for the production of inexpensive electronics. Many applications like radio frequency identification (RFID) Œ1 and organic display benefit from the cheaper production costs of printing technologies. To avoid a trial and error strategy which would involve the fabrication of many different printing forms, it is very helpful and useful to use circuit simulation for low-cost organic circuits in the development and optimization of devices and process. Simulations provide relevant performance figures during device optimization without fabricating and measuring real devices. Nevertheless, adequate OFET models, which could accurately represent OFET behavior, are required in circuit simulation in this area. A library using an SPICE and Agilent ADS multiple platform for RFID application has already been presented in previous work Œ2 5. In this paper, a novel OFET model was applied, and at the same time we discuss its relevant basic digital circuit blocks, which will be of use to some applications. 2. The OFET charge model Cerdeira and Estrada et al. Œ6; 7 firstly developed a model which improves the fitting between the model and experiment data for organic thin film transistors. The model is based on hopping transport and is derived from the TFT model for amorphous silicon TFT (a-si TFT). In Ref. [7], it showed some pentacene OFETs can be very accurately modeled using the same expression for mobility as for a-si TFTs. Originally, a-si TFT model was only available in the above-threshold region Œ6. In this paper, this model is modified by considering the drain source current in the leakage region and named OFET charge model in the following context. The drain current in the linear and saturation regions is modeled as:.v GS V T / I D D K Œ1 C RK.V GS V T / V DS.1 C V DS / m 1=m C I leakage ; (1) VDS 1 C V DSSAT where K D C IW, W is the channel width, L is the channel L length, C I is the gate capacitance, V T is the threshold voltage, R is the source plus drain resistance, m and are fitting parameters related to the sharpness of the knee region and to the channel length modulation respectively. is the gate-voltage dependent mobility which is described by a fitting function as: VGS V T D 0 ; (2) V AA where 0 is usually taken as the low-field mobility, and V AA are empirical parameters defining the variation of mobility with V GS. V DSSAT stands for the saturation voltage, which is defined through the saturation modulation parameter : V DSSAT D.V GS V T /: (3) The drain source current in the leakage region I leakage is described by two terms Œ8 : (1) A term representing the intrinsic resistance between the drain and the source; (2) A term with exponential drain source and gate source dependence. 3. Parameter extraction method In this section, the extraction procedure for parameters of the OFET charge model is described. 3.1. Extraction of V T and Parameter V T and could be extracted from the function H.V GS / in the linear region Œ6; 9 : * Project supported by the NAMATECH Project of Regione Piemonte, Italy. Corresponding author. Email: seth.shenshu@gmail.com Received 10 August 2012, revised manuscript received 18 November 2012 2013 Chinese Institute of Electronics 055003-1

H.V GS / D R VGS 0 I D.V GS /dv GS D V GS V T I D.V GS / 2 C : (4) In this case, we could obtain V T from the intercept, and from the slope of the linear region in Eq. (4). 3.2. Extraction of V AA From the experimental data, we could calculate the curve I DS 1=.1C/ versus V GS V T and get its slope S 1. The value of V AA can be extracted by Œ6; 9 : V AA D K 1V DS S 1C 1! 1= ; (5) where K 1 D K 0 D W L C I 0. Up to now, three parameters which determine the effective change of the field effect mobility in Eq. (2) have been extracted by the above procedures. Table 1. Parameters of the OFET charge model. Model parameter Notation Value Channel width W 100 m Channel length L 8 m Gate capacitance C I 3.6 nf/m 2 Threshold voltage V T 1.7 V Low field mobility 0 1.06 cm 2 /(Vs) Source plus drain resistance R 186 k Mobility enhancement 0.96 Voltage overdrive V AA 33 V Channel modulation 7 10 5 V 1 Saturation modulation 0.165 Sharpness of the knee region m 1.72 3.3. Extraction of In the next step, the saturation current characteristics for V DS > V GS V T are used to calculate the slope S 2 in the linear region of I 1=.2C/ DSSAT versus V GS V T. Parameter is obtained by: D S 2C 2 V AA p 2 : (6) K 1 3.4. Extraction of m Then parameter m could be calculated by estimating Eq. (1) at the saturation voltage, neglecting R and Œ7; 10 : m D lg 2= lg 3.5. Extraction of K.V GS V T / Œ1 C K.V GS V T / I DSSAT : (7) The channel length modulation parameter is extracted evaluating the expression for the output current characteristic, Equation (1) at the maximum values of V DS and V GS voltages to fit the slope of the experimental data: m 1=m VDS I DS Œ1 C RK.V GS V T / 1 C V D DSSAT VDS 2 K.V 1 : GS V T / V DS (8) With the steps above, all important parameters in the model are extracted. 4. Results and discussion The OFET charge model can be used for both n and p type devices and provides good behavior in all the concerning linear regions, which is a really important aspect in digital applications. Actually the model is static since no dynamic effects have been involved as a result that only DC data are available, and therefore the identification of the dynamic part of the model could not be accomplished. If data concerning for instance the frequency or transient behavior were available, Fig. 1. Measured (symbols) and modeled (solid lines) output characteristics with V GS from 20:1 to 0:1 V. the model could be completed by inserting the reactive effects, for example extending the capacitance model represented in Refs. [4, 5]. The model was initially implemented only in SPICE Œ11, but was on purpose extended to Agilent ADS Œ12 to exploit its powerful optimization facilities to identify the parameters and fit the device characteristics descending from the given process. Meanwhile, we also use the Matlab program for parameter calculation and optimization. Here we adopted the OFET charge model for fitting the experiment data from an UK research institute. Table 1 resumes the extracted parameters, which allow a really good agreement with the data obtained from the measurement as shown in Figs. 1 and 2, which report comparisons between the modeled and measured data. From those figures, we can see that the fitting between the measurement and model is very promising, both in the output characteristics in Fig. 1 and the transfer characteristics reported in Fig. 2. The calculated mobility of a-si TFTs in Eq. (2) is mostly similar to the mobility calculation for organic FETs, so that comparable results can be expected. Iniguez and his colleagues developed this model further and present a framework of OFET modeling based on assumption that the mobile charge was localized and the charge transport was caused by hopping be- 055003-2

Fig. 3. Zero-V GS load inverter schematic implementation. Fig. 2. Measured (symbols) and modeled (solid lines) transfer characteristics with V DS from 20:1 to 0:1 V. tween localized states Œ7; 9; 13. Approximating the density of state (DOS) by a Gaussian, they found an analytical and explicit expression of the channel current. Moreover, temperature dependence is also taken into account: D 2 T 0 2; (9) T where T is the absolute temperature, and T 0 is the characteristic temperature of the exponential DOS. The OFET charge model mainly describes the behavior in the above-threshold conditions, for subthreshold conditions the current is assumed to have a small constant value I leakage. There is a variation factor for the onset of saturation in the output characteristics I D versus V DS. Seen from Figs. 1 and 2, we could reach a conclusion that the accuracy of the model with respect to pentacene transistors is good. Compared with another OFET model (named the OFET compact DC model to distinguish), which has been introduced in our previous work Œ4; 5 and other literature Œ14; 15, there are some common factors as well as differences. Concerning the common factors for example, the mobility enhancement factor and the low-field mobility 0 as well as the channel length modulation factor are the same in both models. The values for the reference voltages (V in the OFET compact DC model and V AA in the OFET charge model) are proportional Œ14, following: V AA D V. C 2/: (10) Therefore, V AA and V have essentially the same meaning. As for differences, one difference concerns parameter m in the OFET charge model. This parameter is used to control the sharpness of the transition between the linear and saturation region in the OFET charge model, while the OFET compact DC model does not have this parameter. This is mainly because VD m interferes with V D when varying V D, which can cause an unrealistic estimated value for (a negative value for example) Œ7; 15. The second difference is about the contact effects. In an OFET charge model, the source plus drain resistance R is assumed to be nearly constant. In contrast, the contact resistance has a separate model in the OFET compact DC model. Furthermore, in the OFET charge model, fitting parameter is used to reduce the saturation point of V D to less than V G V T, which is not found in the OFET compact DC model Œ7; 14; 15. Lastly, we need to mention that the OFET compact DC model is symmetrical, while the OFET charge model is source referenced and can be used only if the potential of the source terminal is taken as zero potential Œ7; 15. 5. Design of digital circuit blocks We conclude this section reporting a few examples on model usage to design some basic circuits with OFET, oriented to the realization of RFID building blocks, based on the OFET charge model introduced in the above sections. These topics have already been addressed by our research group, in fact, we have already developed a design kit library to support the RFID efforts of the designers putting a set of basic elements/cell models at our disposal Œ2 4. The library is available for users that intend to test the model accuracy and effectiveness. A set of examples with increasing complexity to test the model behavior is hereafter reported. As a first example we present the results obtained simulating an OFET based inverter, then we will deal with the more complex NAND gate, while the last, and more interesting and ambitious example refers to an eleven stage ring oscillator able to generate a square wave signal with a frequency around 2 khz, that could be exploited within a RFID tag to drive all digital and analog operations required. 5.1. Inverter The zero-v GS load architecture is applied to the build inverter because of its lower complexity, which electrical scheme is reported in Fig. 3, which is simulated here by the OFET model above. An input output characteristic is illustrated in Fig. 4. The separation of logic levels mainly depends on the ratio between the width of the load M2 and of the driver transistor M1 if they have the same channel length. In our study, the aspect ratio r w has been optimized using SPICE and the Monte Carlo analysis available in the Agilent ADS suite to obtain the best trade-off between the noise margin and port gain. The final optimized aspect ratio between the load and drive transistors is 15. Figure 5 shows the transient time input and output voltage of a NOT driven with a square wave input between 10 V and 0 V at a 055003-3

Fig. 6. Zero-V GS NAND2 schematic implementation. Fig. 4. Input output static inverter characteristic. Fig. 7. Transient simulation (V SS D 0 V, V DD D 10 V), with two 500 Hz symmetrical square wave inputs with different delays. Fig. 5. Transient simulation (V SS D 0 V, V DD D 10 V ), with a 500 Hz symmetrical square wave at the input. frequency of 500 Hz. 5.2. NAND All the combinational systems based on NAND logic gates, compared with the NOR based approach, allow better performances, especially concerning the noise margin. The NAND architecture is simply derived from the inverter gate adding one or more driver transistors to the high side of a zeroload inverter. The schematic of the NAND2, reported in Fig. 6, is obtained from the NOT scheme paralleling more pull-ups and optimizing the device aspect ratio according to the NAND gate functionalities. The device aspect ratio between the transistors ML and MD (MD1 and MD2 are identical) thus obtained is 20. Figure 7 reports the transient simulation when both inputs are square waves at 500 Hz. 5.3. Ring oscillator A ring oscillator consists of a cascade of an odd number of inverter stages, where the last inverter connects the input of the first, determining the classical ring topology. An RC filter, connected between the input and the output of several inverters, ensures the correct selection of the oscillation frequency, while the odd stage number prevents the system reaching a DC stable operating point. To test the capabilities of our simulation Fig. 8. Ring oscillator electrical scheme. approach, we have set up an 11-stage ring oscillator, using the optimized inverter discussed in the previous section. The output of the multiple inverter ring cannot be directly connected to an external load without compromising its behavior, due to the small current driving capabilities of OFETs. A proper buffer stage expressly conceived to increase the oscillator output current level must be provided; the best trade-off between current level, time delay and power consumption is obtained with a multistage progressive, exponential buffer, with a tapering profile accurately optimized through SPICE and Agilent ADS simulations. The overall circuit is demonstrated in Fig. 8. The simulated oscillation frequency is around 2 khz shown in Fig. 9 and strongly depends on the magnitude of the load capacitances. 055003-4

Fig. 9. Time domain response of the 11-stage ring oscillator with an oscillation frequency around 2 khz. 6. Conclusions In summary, we have presented an OFET charge model, as well as its parameter extraction method. Although this model derived from the TFT model for amorphous silicon TFT, it is very suitable for OFET modeling after comparing modeling and experiment data. We also developed some basic OFET based digital circuit blocks, including an inverter, NAND, and ring oscillator. The design would be considered to be effectively used to design relevant applications such as an RFID transponder. References [1] Cantatore E, Geuns T C T, Gelinck G H, et al. A 13.56 MHz RFID system based on organic transponders. IEEE J Solid-State Circuits, 2007, 42(1): 84 [2] Shen S, Tinivella R, Pirola M, et al. SPICE library for low-cost RFID applications based on pentacene organic FET. Proc 6th International Conference on Wireless Communication, Networking and Mobile Computing, 2010 [3] Tinivella R, Shen S, Pirola M, et al. A device-level analog and digital subsystem SPICE library for the design of low-cost pentacene OFET RFIDs. Proc IMS Conference, 2010: 848 [4] Tinivella R, Camarchia V, Pirola M, et al. Simulation and design of OFET RFIDs through an analog/digital physics-based library. Org Electron, 2011, 12: 1328 [5] Shen S. Low cost RFID system based on all organic technology. PhD Thesis, Politecnico di Torino, Italy, 2012 [6] Cerdeira A, Estrada M, Garcia R, et al. New procedure for the extraction of basic a-si:h TFT model parameters in the linear and saturation regions. Solid-State Electron, 2001, 45: 1077 [7] Estrada M, Cerdeira A, Puigdollers J, et al. Accurate modeling and parameter extraction method for organic TFTs. Solid-State Electron, 2005, 49: 1009 [8] Yasghmaszxasdeh O, Bonnasasasieuzx Y, Saboundji A, et al. A SPICE-like DC model for organic thin-film transistors. Korean Physical Society, 2007, 54(1): 523 [9] Iniguez B, Picos R, Veksler D, et al. Universal compact model for long- and short-channel thin-film transistors. Solid-State Electron, 2008, 52: 400 [10] Estrada M, Cerdeira A, Pallares J, et al. Mobility model for compact device modeling of OTFTs made with different materials. Solid-State Electron, 2008, 52: 787 [11] Spice Freeware online, Available from: http://www.spiceopus.si/ [12] Agilent ADS, Version 2009, Agilent Technol., Palo Alto, CA, 2009 [13] Iniguez B, Pallares J, Marsal L F, et al. Compact modeling of organic thin-film transistors. Proc ICSICT, 2010: 1268 [14] Marinov O, Deen M J, Zschieschang U, et al. Organic thin-film transistors: Part I compact DC modeling. IEEE Trans Electron Devices, 2009, 56: 2952 [15] Deen M J, Marinov O, Zschieschang U, et al. Organic thin-film transistors: Part II parameter extraction. IEEE Trans Electron Devices, 2009, 56: 2962 055003-5