a FEATURES Excellent Sonic Characteristics Low Noise: nv/ Hz Low Distortion:.% High Slew Rate: V/ s Wide Bandwidth: 9 MHz Low Supply Current: ma Low Offset Voltage: mv Low Offset Current: na Unity Gain Stable SOIC- Package APPLICATIONS High Performance Audio Active Filters Fast Amplifiers Integrators GENERAL DESCRIPTION The OP7 is the first amplifier to feature the Butler Amplifier front-end. This new front-end design combines both bipolar and JFET transistors to attain amplifiers with the accuracy and low noise performance of bipolar transistors, and the speed and sound quality of JFETs. Total Harmonic Distortion plus Noise equals that of previous audio amplifiers, but at much lower supply currents. A very low l/f corner of below Hz maintains a flat noise density response. Whether noise is measured at either Hz or khz, it is only nv/ Hz. The JFET portion of the input stage gives the OP7 its high slew rates to keep distortion low, even when large output swings are required, and the V/µs slew rate of the OP7 is the fastest of any standard audio amplifier. Best of all, this low noise and high speed are accomplished using less than ma of supply current, lower than any standard audio amplifier. Dual Bipolar/JFET, Audio Operational Amplifier OP7 PIN CONNECTIONS -Lead Narrow-Body SO -Lead Epoxy DIP (S Suffix) (P Suffix) OUT A IN A 7 OP7 +IN A V V+ OUT B IN B +IN B OUT A IN A +IN A V OP7 7 V+ OUT B IN B +IN B Improved dc performance is also provided with bias and offset currents greatly reduced over purely bipolar designs. Input offset voltage is guaranteed at mv and is typically less than µv. This allows the OP7 to be used in many dc coupled or summing applications without the need for special selections or the added noise of additional offset adjustment circuitry. The output is capable of driving Ω loads to V rms while maintaining low distortion. THD + Noise at V rms is a low.%. The OP7 is specified over the extended industrial ( C to + C) temperature range. OP7s are available in both plastic DIP and SOIC- packages. SOIC- packages are available in piece reels. Many audio amplifiers are not offered in SOIC- surface mount packages for a variety of reasons; however, the OP7 was designed so that it would offer full performance in surface mount packaging. Protected by U.S. Patent No.,,. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Analog Devices, Inc., 99 One Technology Way, P.O. Box 9, Norwood. MA -9, U.S.A. Tel: 7/9-7 Fax: 7/-7
OP7 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Units AUDIO PERFORMANCE THD + Noise = V rms, R L = kω, f = khz. % Voltage Noise Density e n f = Hz 7 nv/ Hz f = khz nv/ Hz Current Noise Density i n f = khz. pa/ Hz Headroom THD + Noise.%, R L = kω, V S = ± V >.9 dbu INPUT CHARACTERISTICS Offset Voltage V OS mv C T A + C. mv Input Bias Current I B V CM = V na V CM = V, C T A + C na Input Offset Current I OS V CM = V na V CM = V, C T A + C na Input Voltage Range V CM. +. V Common-Mode Rejection Ratio CMRR V CM = ±. V, C T A + C db Large Signal Voltage Gain A VO R L = kω V/mV R L = kω, C T A + C 7 V/mV R L = Ω V/mV Offset Voltage Drift V OS / T µv/ C OUTPUT CHARACTERISTICS Output Voltage Swing V O R L = kω. ±.9 +. V R L = kω, C T A + C ±.9 + V R L = Ω, V S = ± V +, V POWER SUPPLY Power Supply Rejection Ratio PSRR V S = ±. V to ± V db V S = ±. V to ± V, C T A + C db Supply Current I SY V S = ±. V to ± V, V O = V, R L =, C T A + C ma V S = ± V, V O = V, R L =, C T A + C. ma Supply Voltage Range V S ±. ± V DYNAMIC PERFORMANCE Slew Rate SR R L = kω V/µs Full-Power Bandwidth BW P khz Gain Bandwidth Product GBP 9 MHz Phase Margin ø m Degrees Overshoot Factor = mv, A V = +, R L = Ω, C L = pf % Specifications subject to change without notice. (@ V S =. V, T A = + C unless otherwise noted)
OP7 WAFER TEST LIMITS (@ V S =. V, T A = + C unless otherwise noted) Parameter Symbol Conditions Limit Units Offset Voltage V OS mv max Input Bias Current I B V CM = V na max Input Offset Current I OS V CM = V na max Input Voltage Range V CM ±. V min Common-Mode Rejection Ratio CMRR V CM = ±. V db min Power Supply Rejection Ratio PSRR V = ±. V to ± V db min Large Signal Voltage Gain A VO R L = kω V/mV min Output Voltage Range V O R L = kω ±. V min Supply Current I SY V O = V, R L = ma max NOTES Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. Guaranteed by CMRR test. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS Supply Voltage................................ ± V Input Voltage................................ ± V Differential Input Voltage....................... ±7. V Output Short-Circuit Duration to GND......... Indefinite Storage Temperature Range P, S Package........................ C to + C Operating Temperature Range OP7G............................ C to + C Junction Temperature Range P, S Package........................ C to + C Lead Temperature Range (Soldering, sec)....... + C ORDERING GUIDE Model Temperature Range Package Option OP7GP C to + C -Pin Plastic DIP OP7GS C to + C -Pin SOIC OP7GSR C to + C SO- Reel, pcs. OP7GBC + C DICE DICE CHARACTERISTICS Package Type θ JA θ JC Units -Pin Plastic DIP (P) C/W -Pin SOIC (S) C/W NOTES Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. For supply voltages greater than ± V, the absolute maximum input voltage is equal to the supply voltage. Shorts to either supply may destroy the device. See data sheet for full details. θ JA is specified for the worst case conditions, i.e., θ JA is specified for device in socket for cerdip, P-DIP, and LCC packages; θ JA is specified for device soldered in circuit board for SOIC package. Die Size.7. in. (7, sq. mils) Substrate is connected to V CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. WARNING! Although the OP7 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE
OP7 Typical Performance Curves OUTPUT VOLTAGE SWING V R L = kω +VOM VOM OPEN-LOOP GAIN V/mV 7 V O = ±V +GAIN R L = Ω +GAIN R L = kω GAIN R L = kω GAIN R L = Ω GAIN db 9 9 PHASE Degrees ± ± ± ± ± SUPPLY VOLTAGE V 7 TEMPERATURE C k k M M Output Voltage Swing vs. Supply Voltage Open-Loop Gain vs. Temperature Closed-Loop Gain and Phase, A V = + GAIN db MARKER 9.9Hz MAG (A/H).dB MARKER 9.Hz PHASE (A/R 9.Deg 9 9 PHASE Degrees CLOSED-LOOP GAIN db A VCL = + A VCL = + A VCL = + IMPEDANCE Ω A VCL = + A VCL = + A VCL = + k k M M k k k M M M k k k M M Open-Loop Gain, Phase vs. Frequency Closed-Loop Gain vs. Frequency Closed-Loop Output Impedance vs. Frequency COMMON-MODE REJECTION db POWER SUPPLY REJECTION db PSRR +PSRR OPEN-LOOP GAIN db GAIN PHASE R L = kω Ø m= 9 7 PHASE Degrees k k k M M Common-Mode Rejection vs. Frequency k k k M Power Supply Rejection vs. Frequency k k k M M M Open-Loop Gain, Phase vs. Frequency
GAIN BANDWIDTH PRODUCT MHz Ø m 9 GBW 7 7 TEMPERATURE C PHASE MARGIN Degrees OVERSHOOT % 9 7 A VCL = + NEGATIVE EDGE A VCL = + POSITIVE EDGE R L = kω = mv p-p LOAD CAPACITANCE pf MAXIMUM OUTPUT SWING V VOM +VOM OP7 k k LOAD RESISTANCE Ω Gain Bandwidth Product, Phase Margin vs. Temperature Small-Signal Overshoot vs. Load Capacitance Maximum Output Voltage vs. Load Resistance. MAXIMUM OUTPUT SWING V A VCL = + R L = kω SUPPLY CURRENT ma... T A = + C T A = C ABSOLUTE OUTPUT CURRENT ma 9 7 SINK SOURCE k k k M M. ± ± ± ± ± SUPPLY VOLTAGE V 7 TEMPERATURE C Maximum Output Swing vs. Frequency Supply Current vs. Supply Voltage Short Circuit Current vs. Temperature INPUT BIAS CURRENT na CURRENT NOISE DENSITY pa/ Hz T A = + C UNITS C to + C BASED ON 9 OP AMPS 7 TEMPERATURE C k k 7 9 TCV OS µv/ C Input Bias Current vs. Temperature Current Noise Density vs. Frequency TCV OS Distribution
OP7 Typical Performance Curves UNITS BASED ON 9 OP AMPS INPUT OFFSET VOLTAGE µv STEP SIZE V +.% +.%.%.% 7 9 SETTLING TIME ns SLEW RATE V/µs SR +SR CAPACITIVE LOAD pf Input Offset (V OS ) Distribution Settling Time vs. Step Size Slew Rate vs. Capacitive Load SLEW RATE V/µs R L = kω SLEW RATE V/µs R L = kω SR +SR..... DIFFERENTIAL INPUT VOLTAGE V Slew Rate vs. Differential Input Voltage 7 TEMPERATURE C Slew Rate vs. Temperature 9 9 % % V ns V ns Negative Slew Rate R L = kω, V S = ± V, A V = + Positive Slew Rate R L = kω, V S = ± V, A V = + CH A:. µv FS MKR:. nv/ Hz. µv/div 9 % mv ns Hz MKR: Hz. khz BW:. MHz Small Signal Response R L = kω, V S = ± V, A V = + Voltage Noise Density vs. Frequency V S = ± V
OP7 APPLICATIONS Short Circuit Protection The OP7 has been designed with inherent short circuit protection to ground. An internal Ω resistor, in series with the output, limits the output current at room temperature to I SC + = ma and I SC = 9 ma, typically, with ± V supplies. However, shorts to either supply may destroy the device when excessive voltages or currents are applied. If it is possible for a user to short an output to a supply, for safe operation, the output current of the OP7 should be design-limited to ± ma, as shown in Figure. Total Harmonic Distortion Total Harmonic Distortion + Noise (THD + N) of the OP7 is well below.% with any load down to Ω. However, this is dependent upon the peak output swing. In Figure it is seen that the THD + Noise with V rms output is below.%. In the following Figure, THD + Noise is below.% for the kω and kω loads but increases to above.% for the Ω load condition. This is a result of the output swing capability of the OP7. Notice the results in Figure, showing THD vs. (V rms). This figure shows that the THD + Noise remains very low until the output reaches 9. volts rms. This performance is similar to competitive products. RFB THD + NOISE %.. V S = ±V R L = Ω.. OUTPUT SWING V rms Figure. Headroom, THD + Noise vs. Output Amplitude (V rms); R LOAD = Ω, V SUP = ± V The output of the OP7 is designed to maintain low harmonic distortion while driving Ω loads. However, driving Ω loads with very high output swings results in higher distortion if clipping occurs. A common example of this is in attempting to drive V rms into any load with ± volt supplies. Clipping will occur and distortion will be very high. To attain low harmonic distortion with large output swings, supply voltages may be increased. Figure shows the performance of the OP7 driving Ω loads with supply voltages varying from ± volts to ± volts. Notice that with ± volt supplies the distortion is fairly high, while with ± volt supplies it is a very low.7%. A RX Ω FEEDBACK. A = / OP7. Figure. Recommended Output Short Circuit Protection. THD %. R L = Ω = Vrms @ khz THD + NOISE %. R L = Ω, k, k = V rms A V = +. ±7 ± ±9 ± ± ± SUPPLY VOLTAGE V. k k k Figure. THD + Noise vs. Frequency vs. R LOAD THD + NOISE %... Ω k A V = + V S = ±V = V rms khz FILTER Figure. THD + Noise vs. Supply Voltage Noise The voltage noise density of the OP7 is below 7 nv/ Hz from Hz. This enables low noise designs to have good performance throughout the full audio range. Figure shows a typical OP7 with a /f corner at. Hz. CH A:. µv FS MKR:. µv/ Hz. µv/div k. k k k Figure. THD + Noise vs. R LOAD ; = V rms, ± V Supplies Hz MKR:. Hz Hz BW:. Hz Figure. /f Noise Corner, V S = ± V, A V = 7
OP7 Noise Testing For audio applications the noise density is usually the most important noise parameter. For characterization the OP7 is tested using an Audio Precision, System One. The input signal to the Audio Precision must be amplified enough to measure it accurately. For the OP7 the noise is gained by approximately using the circuit shown in Figure 7. Any readings on the Audio Precision must then be divided by the gain. In implementing this test fixture, good supply bypassing is essential. Ω 99Ω this effect from occurring in noninverting applications. For these applications, the fix is a simple one and is illustrated in Figure 9. A.9 kω resistor in series with the noninverting input of the OP7 cures the problem. R S.9kΩ R FB IS OPTIONAL R FB R L kω Ω A OP7 B 99Ω OP7 Ω 99Ω OP7.kΩ 9Ω Figure 7. Noise Test Fixture OUTPUT Input Overcurrent Protection The maximum input differential voltage that can be applied to the OP7 is determined by a pair of internal Zener diodes connected across its inputs. They limit the maximum differential input voltage to ± 7. V. This is to prevent emitter-base junction breakdown from occurring in the input stage of the OP7 when very large differential voltages are applied. However, in order to preserve the OP7 s low input noise voltage, internal resistances in series with the inputs were not used to limit the current in the clamp diodes. In small signal applications, this is not an issue; however, in applications where large differential voltages can be inadvertently applied to the device, large transient currents can flow through these diodes. Although these diodes have been designed to carry a current of ± ma, external resistors as shown in Figure should be used in the event that the OP7 s differential voltage were to exceed ± 7. V..kΩ.kΩ + OP7 Figure. Input Overcurrent Protection Output Voltage Phase Reversal Since the OP7 s input stage combines bipolar transistors for low noise and p-channel JFETs for high speed performance, the output voltage of the OP7 may exhibit phase reversal if either of its inputs exceed its negative common-mode input voltage. This might occur in very severe industrial applications where a sensor, or system, fault might apply very large voltages on the inputs of the OP7. Even though the input voltage range of the OP7 is ±. V, an input voltage of approximately. V will cause output voltage phase reversal. In inverting amplifier configurations, the OP7 s internal 7. V input clamping diodes will prevent phase reversal; however, they will not prevent Figure 9. Output Voltage Phase Reversal Fix Overload, or Overdrive, Recovery Overload, or overdrive, recovery time of an operational amplifier is the time required for the output voltage to recover to a rated output voltage from a saturated condition. This recovery time is important in applications where the amplifier must recover quickly after a large abnormal transient event. The circuit shown in Figure was used to evaluate the OP7 s overload recovery time. The OP7 takes approximately. µs to recover to = + V and approximately. µs to recover to = V. V p-p @Hz R kω RS 99Ω A = / OP7 R kω A R L.kΩ Figure. Overload Recovery Time Test Circuit Measuring Settling Time The design of OP7 combines high slew rate and wide gainbandwidth product to produce a fast-settling (t S < µs) amplifier for - and -bit applications. The test circuit designed to measure the settling time of the OP7 is shown in Figure. This test method has advantages over false-sum node techniques in that the actual output of the amplifier is measured, instead of an error voltage at the sum node. Common-mode settling effects are exercised in this circuit in addition to the slew rate and bandwidth effects measured by the false-sum-node method. Of course, a reasonably flat-top pulse is required as the stimulus. The output waveform of the OP7 under test is clamped by Schottky diodes and buffered by the JFET source follower. The signal is amplified by a factor of ten by the OP and then Schottky-clamped at the output to prevent overloading the oscilloscope s input amplifier. The OP is configured as a fast integrator which provides overall dc offset nulling. High Speed Operation As with most high speed amplifiers, care should be taken with supply decoupling, lead dress, and component placement. Recommended circuit configurations for inverting and noninverting applications are shown in Figures and Figure.
OP7 V +.µf V+ DUT R L kω +V N / OPAJ kω D D OUTPUT (TO SCOPE) V D D µf.µf R F kω kω + V kω IC ±V R G Ω NA 7Ω N V kω SCHOTTKY DIODES D D ARE HEWLETT-PACKARD HP- IC IS / OPAJ IC IS PMI OPEJ Figure. OP7 s Settling Time Test Fixture C FB.µF +V µf + R FB.9kΩ µf + / OP7 V.µF R L kω Figure. Unity Gain Follower.99kΩ.µF.µF +V µf + / OP7 V µf + pf.99kω kω R S C S Figure. Compensating the Feedback Pole Attention to Source Impedances Minimizes Distortion Since the OP7 is a very low distortion amplifier, careful attention should be given to source impedances seen by both inputs. As with many FET-type amplifiers, the p-channel JFETs in the OP7 s input stage exhibit a gate-to-source capacitance that varies with the applied input voltage. In an inverting configuration, the inverting input is held at a virtual ground and, as such, does not vary with input voltage. Thus, since the gate-to-source voltage is constant, there is no distortion due to input capacitance modulation. In noninverting applications, however, the gate-to-source voltage is not constant. The resulting capacitance modulation can cause distortion above khz if the input impedance is > kω and unbalanced. Figure shows some guidelines for maximizing the distortion performance of the OP7 in noninverting applications. The best way to prevent unwanted distortion is to ensure that the parallel combination of the feedback and gain setting resistors (R F and R G ) is less than kω. Keeping the values of these resistors small has the added benefits of reducing the thermal noise R G R F C IN Figure. Unity Gain Inverter In inverting and noninverting applications, the feedback resistance forms a pole with the source resistance and capacitance (R S and C S ) and the OP7 s input capacitance (C IN ), as shown in Figure. With R S and R F in the kilohm range, this pole can create excess phase shift and even oscillation. A small capacitor, C FB, in parallel and R FB eliminates this problem. By setting R S (C S + C IN ) = R FB C FB, the effect of the feedback pole is completely removed. R S P7 R S = R G //R F IF R G //R F > kω FOR MINIMUM DISTORTION Figure. Balanced Input Impedance to Minimize Distortion in Noninverting Amplifier Circuits 9
OP7 of the circuit and dc offset errors. If the parallel combination of R F and R G is larger than kω, then an additional resistor, R S, should be used in series with the noninverting input. The value of R S is determined by the parallel combination of R F and R G to maintain the low distortion performance of the OP7. Driving Capacitive Loads The OP7 was designed to drive both resistive loads to Ω and capacitive loads of over pf and maintain stability. While there is a degradation in bandwidth when driving capacitive loads, the designer need not worry about device stability. The graph in Figure shows the db bandwidth of the OP7 with capacitive loads from pf to pf. BANDWIDTH MHz 9 7 C LOAD pf Figure. Bandwidth vs. C LOAD High Speed, Low Noise Differential Line Driver The circuit of Figure 7 is a unique line driver widely used in industrial applications. With ± V supplies, the line driver can deliver a differential signal of V p-p into a. kω load. The high slew rate and wide bandwidth of the OP7 combine to yield a full power bandwidth of khz while the low noise front end produces a referred-to-input noise voltage spectral density of nv/ Hz. R k A R9 V O importance. Like the transformer based design, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of. Other circuit gains can be set according to the equation in the diagram. This allows the design to be easily set to noninverting, inverting, or differential operation. A -Pole, khz Low-Pass Filter The closely matched and uniform ac characteristics of the OP7 make it ideal for use in GIC (Generalized Impedance Converter) and FDNR (Frequency-Dependent Negative Resistor) filter applications. The circuit in Figure illustrates a linear-phase, -pole, khz low-pass filter using an OP7 as an inductance simulator (gyrator). The circuit uses one OP7 (A and A) for the FDNR and one OP7 (A and A) as an input buffer and bias current source for A. Amplifier A is configured in a gain of to set the pass band magnitude response to db. The benefits of this filter topology over classical approaches are that the op amp used in the FDNR is not in the signal path and that the filter s performance is relatively insensitive to component variations. Also, the configuration is such that large signal levels can be handled without overloading any of the the filter s internal nodes. As shown in Figure 9, the OP7 s symmetric slew rate and low distortion produce a clean, wellbehaved transient response. A A R 9.kΩ C pf C pf R.kΩ C pf R.7kΩ R.kΩ R 77Ω R.kΩ C pf 7 A R7 kω R9 kω A A, A = / OP7 A, A = / OP7 R kω 7 A R k R k R7 k R k P k V O V O = Figure. A -Pole, khz Low-Pass Filter R k R k R k A A = / OP7 A, A = / OP7 R GAIN = R SET R, R, R = R AND R, R7, R = R 7 R k R R k V O Vp-p khz 9 % Figure 7. High Speed, Low Noise Differential Line Driver The design is a transformerless, balanced transmission system where output common-mode rejection of noise is of paramount SCALE: VERTICAL V/ DIV HORIZONTAL µs/ DIV Figure 9. Low-Pass Filter Transient Response
OP7 OP7 SPICE Model Node assignments noninverting input inverting input positive supply negative supply output.subckt OP7 99 INPUT STAGE & POLE AT MHz R. R. CIN.7E- CM 9 7.E- CM 9 7.E- C E- I 97 E- IOS E-9 EOS 9 POLY().E- Q 7 QX Q 9 QX R 7.7 R.7 D DZ D DZ EN GN E- GN E- EREF 9 EP 97 99 EM VOLTAGE NOISE SOURCE DN DEN DN DEN VN DC VN DC CURRENT NOISE SOURCE DN DIN DN DIN VN DC VN DC CURRENT NOISE SOURCE DN DIN DN 7 DIN VN DC VN 7 DC GAIN STAGE & DOMINANT POLE AT Hz R7 9.9E C 9.E-9 G 9.7E- V 97 9. V. D 9 DX D DX POLE/ZERO PAIR AT. MHz/.7 MHz R 9 E- R9.E- C 9 7.E- G 9 E- POLE AT MHz R 9 C 9.9E-9 G 9 POLE AT MHz R 9 C 9.9E-9 G 9 COMMON-MODE GAIN NETWORK WITH ZERO AT khz R E C7.9E- R 9 E 9 POLY() 9 9.. POLE AT MHz R 7 9 C 7 9.9E-9 G 9 7 OUTPUT STAGE R 99 E R E C9 E- ISY 99.E- R7 9 99 R 9 L 9 E-9 G 7 9 E- G7 9 7 E- G 9 99 99 7 E- G9 9 7 E- V 9. V 9. F 9 V F 9 V D 7 DX D 7 DX D7 99 DX D 99 DX D9 DY D DY MODELS USED.MODEL QX PNP(BF=E).MODEL DX D(IS=E-).MODEL DY D(IS=E- BV=).MODEL DZ D(IS=E- BV=7.).MODEL DEN D(IS=E- RS=.K KF=.9E- AF=).MODEL DIN D(IS=E- RS= KF=.E- AF=).ENDS
OP7 OUTLINE DIMENSIONS Dimensions shown in inches and (mm).. (.). (.).9 (.). (.) SEATING PLANE -Lead Narrow-Body SOIC (S Suffix).9 (.).9 (.) PIN. (.7) BSC.7 (.).97 (.). (.7). (.).9 (.9). (.).9 (.).7 (.9).9 (.).99 (.) x. (.7). (.). (.). (.). (.9). (.) PIN -Lead Epoxy DIP (P Suffix). (7.). (.). (.). (.). (.) MAX.. (.). (.9)..7 (.77) (.). (.) BSC (.) MIN SEATING PLANE. (.). (7.).9 (.9). (.9). (.). (.) Ca 7/9 PRINTED IN U.S.A.