GaN Transistors for Efficient Power Conversion

Agenda How GaN works Electrical Characteristics Design Basics Design Examples Summary 2 2

How GaN Works 3 3

The Ideal Power Switch Block Infinite Voltage Carry Infinite Current Switch In Zero Time Zero Drive Power Normally Off 4 4

5 Power Switch Wish List Faster Lower Conduction Loss Less Capacitance Smaller Lower Cost

Material Comparison 6 6

GaN + AlGaN Spontaneous Polarization AlGaN GaN 7 7

GaN Magic V AlGaN GaN 2D Electron Gas 8 8

GaN Switch V Applying bias destroys the polarization E Field AlGaN GaN 9 9

GaN Now we Switch have a switch That has high voltage blocking V capability, low on resistance, and is very, very fast. AlGaN GaN Depletion Mode = Normally On 10 10

Device Construction Concept Source Gate AlGaN Protection Dielectric Drain GaN Substrate Early substrate materials: SiC and Sapphire Are expensive and hard to manufacture. Silicon substrates are much lower cost and allow fabrication in a standard CMOS Fab. 11 11

What About Normally Off Devices? True enhancement mode GaN HFETs have been around for years There are various methods for dissipating the electron gas under the gate 12 12

Enhancement Mode A positive voltage from Gate-To-Source establishes an electron gas under the gate 13 13

State of the Art 14 14

Body Diode? A positive voltage from Gate-To-Drain also establishes an electron gas under the gate 15 15

egan FET Reverse Conduction MOSFET + Q RR egan FET + Zero Q RR 16 16

Threshold vs. Temperature 1.2 1.1 Normalized Thershold Voltage 1 0.9 0.8 0.7 egan FET MOSFET A 0.6-50 -25 0 25 50 75 100 125 150 Junction Temperature ( C) 17 17

MOSFET Transfer Characteristics Negative temperature coefficient region of silicon MOSFET Source: www.infineon.com 18 18

egan FET Transfer Characteristics EPC2001 19 19

egan FET Safe Operating Area 1 ms 10 ms 100 ms DC 20

egan FET Safe Operating Area 1 ms 10 ms 100 ms DC 21

egan FET Capacitances C GS C DS GaN Silicon C GD 22 22

Total Gate Charge BSC057N08NS EPC2001 = 100 V, 5.6 mω typ BSC057N08 = 80 V, 4.7 mω typ 23 23

Figure of Merit FOM = Rdson x Qg (100V) 500 400 300 200 100 0 EPC2001 BSC109N10NS3 IRFH5030 SiR870DP FDMS86101 24 24

egan FET Loss Mechanisms Like A MOSFET I²R Conduction Loss Capacitive Switching Losses Gate Drive Losses V I Switching Loss Not Like A MOSFET High Reverse Conduction Loss No Body Diode Reverse Recovery Loss 25 25

Package Wish List Low parasitic resistance Low parasitic inductance Low thermal resistance Small size Low cost 27 27

Flip-Chip LGA Construction egan FET Silicon Solder Bar Copper Trace Printed Circuit Board Absolute minimum lead resistance and inductance! 28

LGA Construction Drain Contacts Interleaving to reduce layout inductance Substrate Gate Source Contacts 29 29

Size Comparison 200 V egan FET D-PAK 5.76 mm² Drawn To Scale 65.3 mm² 30 30

Key Applications Wireless Power Transmission GaN Enabled RF DC-DC Envelope Tracking GaN Enabled RadHard Power Over Ethernet RF Transmission Network and Server Power Supplies Point of Load Modules Energy Efficient Lighting Class D Audio 31 31

Design Basics Agenda Gate Driver Requirements Layout Thermal Management 32 32

E-Mode Gate Drive - Low V GS(ON) Overhead V GS(Max) = 6 V 33 33

Gate Drive Solution No overshoot: R G 4 ( LG + L C GS S ) Minimize inductance Tight gate drive layout BGA and LGA minimizes package inductance Choose correct resistance Separate source and sink transistors allowing for separate drive paths. 34 34

Bootstrap Supply +5V HB VIN LEVEL SHIFT HOH HOL Switch can be node negative during low side diode conduction Regulated high side supply Minimal dead time and slow bootstrap HS 35 35

High Side Regulation LM5113 Bootstrap clamp limits floating (HS) power supply Separate control inputs allow accurate, flexible tuning to minimize dead-time Well matched channel-to-channel propagation delays are critical Optional Schottky in parallel Texas Instruments, Gate Drivers for Enhancement Mode GaN Power FETs 100 V Half-Bridge and Low- Side Drivers Enable Greater Efficiency, Power Density, and Simplicity, SNVB001 36 36

Layout 37 37

Packaging Evolution So-8 LFPAK DirectFET LGA egan Power Loss (W) 2.5 2 1.5 1 0.5 0 Device Loss Breakdown 82% 18% Package Die 73% 27% 47% 53% So-8 LFPAK DirectFET LGA V IN =12V V OUT =1.2V I OUT =20A F S =1MHz 18% 82% Efficiency (%) 90 85 80 75 70 So-8 LFPAK DirectFET egan 65 0.5 1 1.5 2 2.5 3 3.5 Switching Frequency (MHz) 38 38

Generating Kelvin Source Connection Source Return Source R Source C GD Substrate Gate R Series R G C GS R Sink Drain L S Minimize Common Source Inductance 39 39

Buck Converter Parasitics C in T SR L S : Common Source Inductance L Loop : High Frequency Power Loop Inductance Power Loss(W) 5.5 5.25 5 4.75 4.5 4.25 4 3.75 3.5 3.25 3 Power Loss vs Parasitic Inductance Ls L Loop 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 Parasitic Inductance (nh) V IN =12 V, V OUT =1.2 V, F S =1 MHz, I OUT = 20 A 40 40

Layout Impact on Efficiency Efficiency (%) 91 90 89 88 87 86 85 84 83 Measured Efficiency 40V MOSFET 3x3mm LFPAK L Loop 3nH L Loop 0.4nH L Loop 1.0nH L Loop 1.6nH L Loop 2.9nH 2 4 6 8 10 12 14 16 18 20 22 24 Output Current (I OUT ) V IN =12 V, V OUT =1.2 V, F S =1 MHz, L=150 nh Experimental Prototype L LOOP 0.4 nh 41 41

Layout Impact on Peak Voltage L Loop 1.0 nh L Loop 0.4 nh 70% Overshoot 30% Overshoot Switching Node Voltage V IN =12 V V OUT =1.2 V I OUT =20 A F S =1 MHz L=150 nh 42 42

Conventional Lateral Layout Top View Side View 43 43

Conventional Vertical Layout Top View Side View Bottom View 44 44

Optimal Layout Top View Side View Top View Inner Layer 1 45 45

Power Loss Comparison Power Loss (W) 4 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 Lateral Power Loop Optimal Power Loop Vertical Power Loop 3 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 High Frequency Loop Inductance (L LOOP ) V IN =12 V V OUT =1.2 V I OUT =20 A F S =1 MHz L=300 nh T/SR: EPC2015 Driver LM5113 46 46

Efficiency Comparison 91 90 Efficiency (%) 89 88 87 86 85 84 40V MOSFET Design 1 Optimal Design 1 Vertical Design 1 Lateral Design 1 83 2 4 6 8 10 12 14 16 18 20 22 24 26 Output Current (I OUT ) V IN =12 V V OUT =1.2 V F S =1 MHz L=300 nh T/SR: EPC2015 Driver LM5113 47 47

egan FET vs. MOSFET Si MOSFET egan FET V IN =12 V V OUT =1.2 V I OUT =20 A F S =1 MHz L=300 nh egan FET T/SR: EPC2015 MOSFET T:BSZ097N04LS SR:BSZ040N04LS 48

Layout Summary egan FETs improve performance in high switching frequency converters CSI is a critical component for maximizing switching performance Gate drive loop inductance limits switching speed Optimizing power loop inductance improves efficiency and minimizes voltage overshoot Current measurements affect performance Voltage measurements are bandwidth limited Reduced ringing reduces EMI 49 49

Thermal Management 50 50

Thermal Management Heat Is Generated In GaN Material Essentially On The Surface Of The Die Silicon Substrate Active GaN Device Region Solder Bars Copper Traces Printed Circuit Board 51 51

Thermal Management Silicon Substrate R ƟJC Active GaN Device Region Solder Bars R ƟJB Copper Traces Printed Circuit Board Two Paths For Heat: Through The Back Of The Die Or Through The Solder Contacts Into The PCB 52 52

Thermal Resistance with Heat Sink Silicon Substrate Active GaN Device Region R ƟJC Solder Bars R ƟJB Copper Traces Printed Circuit Board 53 53

Thermal Resistance with Heat Sink 2 22 Printed Circuit Board 1 Thermal Interface Material on sides of die too 54 54

Thermal Model with Heat Sink Back of Die temperature Heatsink R θtim R θha R θtim Ambient Temperature Junction temperature R θjc R θjc R θjb R θjb Other PCB losses Device 1 Power dissipation R θspread R θpcba Ambient Temperature Device 2 Power dissipation 55 55

Thermal Results Possible to remove up to 5 W from small EPC die with double sided cooling 56

Design Example Agenda Hard Switched Circuits Buck Converter Isolated Full Bridge Envelope Tracking Resonant Circuits Intermediate Bus Converter 57 57

Buck Converters 58

High Frequency Buck Converters D. Reusch, D. Gilham, Y. Su, and F.C. Lee, C, Gallium Nitride Based 3D Integrated Non-Isolated Point of Load Module, APEC 2012 59

EPC9107 Optimal Layout Buck Module Switching Node Voltage V IN =28 V I OUT =15 A EPC9107 Demonstration Board V IN =12-28 V V OUT =3.3 V I OUT =15 A F S =1 MHz 2 x EPC2015 5 V/ div 60

EPC9107 Demonstration Board Efficiency (%) 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 12 V IN 19 V IN 24 V IN 28 V IN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Output Current (Io) V OUT =3.3 V F S =1 MHz GaN T/SR: EPC2015 Driver LM5113 61

Isolated Full Bridge 62

100 V Hard Switching FOM 160 FOM=(Q GD +Q GS2 )*R DSON (nc*ω) 140 120 100 80 60 40 20 0 Q GS2 Q GS2 Q GS2 Q Q GS2 GD Q GD Q GS2 Q GD Q GD Q GD 100V egan FET 80V MOSFET 1 80V MOSFET 2 80V MOSFET 3 80V MOSFET 4 V DS =0.5*V DS, I DS = 15 A 63 63

Regulated Full Bridge Converter EPC9102 Demo board Full Bridge, 36-60 Vin, 12 V, 200 W, 375 khz 64 64

Efficiency Comparison 375 khz egan FET 250 khz MOSFET Regulated 12 V Output 65 65

Brick Converter Summary Topologies varied Optimization as important as device selection Efficiency is key to power density Maximum power loss is fixed. Good comparison requires identical designs Given topology, egan FETs will outperform MOSFETs based on superior FOM 66 66

Overview of Envelope Tracking World of Radio Frequency Power Amplifiers (RFPA) is changing. Increased efficiency driven by: Improved battery life Reduced cooling Reduced size Lower cost of operation 67

Peak to Average Power Ratio Same average Normalized to same peak Ref: Nujira.com website 68

Effect of PAPR Average Power Peak Power Fixed supply PAPR = 0dB Peak efficiency up to 65% Average efficiency only 25 % Increasing PAPR Output Probability Output Power (dbm) 69

Effect of Envelope Tracking Average efficiency > 50 % (incl. ET) Only 1/3 the losses Envelope Tracking Output Probability Average Power Output Power (dbm) 70

RFPA Standards* Up to 20 MHz Carrier bandwidth required Required ET supply BW up to 5x higher if linear control *Ref: www.open-et.org website 71

Envelope Tracking Supply ET power supply topologies vary Open loop boost full BW required Closed loop linear-assisted Buck* Buck ~ 10% Bandwidth ~ 90% Power Linear AMP ~ 10% Power Highest 90% of Bandwidth *V. Yousefzadeh, et. Al, Efficiency optimization in linear-assisted switching power converters for envelope tracking in RF power amplifiers, ISCAS 2005 72

egan FET based Buck(s) for ET 1300 W DVB* 8 MHz BW and 8 db PAPR Linear-assisted Buck for ET 4 phase x 1 MHz Buck with up to 800 khz band width 45 V IN, 22 V OUT / 15 A OUT (Avg) Pure Buck option for ET (Push frequency) 10 phase x 4 MHz Buck with up to 8 MHz band width 45 V IN, 22 V OUT / 6 A OUT (Avg) *Representative of a high power ET buck in HV LDMOS, such as that implemented by ET specialist Nujira. 73

6 A OUT / 4 MHz Single φ Buck Modified an EPC9006 development board 45 V IN Before After Gappad GP1500 60 mil 22 V OUT Common LM5113TE EPC2007 74

Efficiency Results 98% 10x potential bandwidth require 2.5x more phases and 2x losses 16 97% 14 96% 12 Efficiency (%) 95% 94% 93% 4 MHz Efficiency 10 8 6 Power loss (W) 92% 1 MHz Efficiency 4 91% 90% 2 1 MHz Losses 0 0 50 100 150 200 250 300 350 Output Power (W) 4 MHz Losses 75

Loss Breakdown EPC2001 EPC2007 EPC2001 EPC2007 1 MHz EPC9002 4 MHz EPC9006 Future die size optimization possible 76 76

Higher Frequency ET Results* EPC1014 BSC016N04LSG 24 V IN to 12 V OUT Buck 20 to 30 pp improvement! 4 MHz 7 MHz 10 MHz *D. Čučak, et. al, Application of egan FETs for highly efficient Radio Frequency Power Amplifier, CIPS 2012 77

Envelope Tracking Summary egan FETs are an enabling technology for ET Low charge reduces delay and switching times Thermally possible - with double sided cooling Results are representative, but not optimized Improve inductor selection Improve thermal design Reduce high side peak device temp by reducing low side device size to reduce Q OSS losses Power and # of phases application specific 78 78

Resonant Converters 79

100 V Soft Switching FOM 350 FOM=(Q OSS or Q G )*R DSON (nc*ω) 300 250 200 150 100 50 0 Q OSS Q OSS Q OSS Q G Q G Q G 100 V EPC2001 80 V BSC057N08NS3G 80 V BSZ123N08NS3G V DS =48 V 80

egan FET vs. MOSFET 81

ZVS Switching Comparison T ZVS = 42 ns egan FET V DS MOSFET V DS T ZVS = 87 ns MOSFET V GS egan FET V GS F S = 1.2 MHz, V IN = 48 V, and V OUT = 12 V 82

Duty Cycle Comparison D egan FET = 42% D MOSFET = 34% MOSFET V GS egan FET V DS egan FET V GS MOSFET V DS F S = 1.2 MHz, V IN = 48 V, and V OUT = 12 V 83

Efficiency Comparison Efficiency (%) 98 97 96 95 94 93 92 91 1.2 MHz egan FET 1.2 MHz MOSFET 10 W 12 W 14 W Power Loss (W) 24 22 20 18 16 14 12 10 8 6 4 1.2 MHz MOSFET 1.2 MHz egan FET 90 0 5 10 15 20 25 30 35 40 Output Current (I OUT ) 2 0 5 10 15 20 25 30 35 40 Output Current (I OUT ) F S = 1.2 MHz, V IN = 48 V, and V OUT = 12 V 84

Loss Breakdown Power Loss (W) 12 10 8 6 4 Gate Drive Transfomrer Core Conduction + Turn Off 2 0 egan FET I OUT = 2.5 A MOSFET I OUT = 2.5 A egan FET I OUT = 20 A MOSFET I OUT = 20 A F S = 1.2 MHz, V IN = 48 V, and V OUT = 12 V 85

EPC9105 Bus Converter EPC9105 Demonstration Board 36-60 V IN, 12 V OUT, 350 W, 1.2 MHz L IN L K1 2 SR V IN+ C IN Q 1 Q 3 4:1 * * * Q 6, Q 7 V OUT+ L OUT C RES C OUT V IN- Q 2 Q 4 L K2 2 SR Q 5, Q 8 V OUT- 86

Resonant Converter Summary egan FETs improve high frequency resonant converter performance Lower output charge Lower gate charge More power delivery per cycle 87 87

Summary GaN transistors have the potential to replace silicon power MOSFETs in power conversion applications with a low-cost and higher efficiency solution egan FETs are straightforward to use, but care must be taken due to the higher switching speeds compared with power MOSFETs GaN transistors enable exciting new applications such as RF Envelope Tracking 88 88