High Performance Digital Fractional-N Frequency Synthesizers

Why Are Digital Phase-Locked Loops Interesting? PLLs are needed for a wide range of applications - Communication systems (both wireless and wireline) - Digital processors (to achieve GHz clocks) Performance is important - Phase noise can limit wireless transceiver performance - Jitter can be a problem for digital processors The standard analog PLL implementation is problematic in many applications - Analog building blocks on a mostly digital chip pose design and verification challenges - The cost of implementation is becoming too high Can digital phase-locked loops offer excellent performance with a lower cost of implementation? 2

Just Enough PLL Background

What is a Phase-Locked Loop (PLL)? ref(t) ref(t) out(t) out(t) e(t) v(t) e(t) v(t) ref(t) Phase Detect e(t) Analog v(t) out(t) Loop Filter VCO de Bellescize Onde Electr, 1932 VCO efficiently provides oscillating waveform with variable frequency PLL synchronizes VCO frequency to input reference frequency through feedback - Key block is phase detector Realized as digital gates that create pulsed signals 4

Integer-N Frequency Synthesizers ref(t) div(t) e(t) v(t) F out = N F ref ref(t) div(t) Phase Detect e(t) Analog v(t) out(t) Loop Filter Divider VCO Sepe and Johnston US Patent (1968) Use digital counter structure to divide VCO frequency - Constraint: must divide by integer values Use PLL to synchronize reference and divider id output t Output frequency is digitally controlled N 5

Fractional-N Frequency Synthesizers ref(t) div(t) e(t) v(t) Kingsford-Smith US Patent (1974) Wells US Patent (1984) F out = M.F F ref ref(t) div(t) N sd [k] sd[ ] Phase Detect e(t) Analog v(t) out(t) Loop Filter Σ Δ Modulator Divider N[k] VCO Riley US Patent (1989) JSSC 93 M.F Dither divide value to achieve fractional divide values - PLL loop filter smooths the resulting variations Very high frequency resolution is achieved 6

The Issue of Quantization Noise ref(t) div(t) e(t) v(t) F out = M.F F ref ref(t) div(t) Phase Detect e(t) Analog v(t) out(t) Loop Filter Divider VCO N sd [k] Σ Δ Modulator N[k] Limits PLL bandwidth Increases linearity requirements of phase detector M.F Σ Δ Quantization Noise f 7

Striving for a Better PLL Implementation

Analog Phase Detection ref(t) () div(t) 1 reset 1 D Q D Q Reg error(t) phase error ref(t) div(t) error(t) ref(t) Phase Detect Analog Loop Filter out(t) div(t) Divider VCO Pulse width is formed according to phase difference between two signals Average of pulsed waveform is applied to VCO input 9

Tradeoffs of Analog Approach ref(t) div(t) error(t) Phase Detector Signals Average of error(t) Phase Detector Characteristic phase error ref(t) Phase Detect Analog Loop Filter out(t) div(t) Divider VCO Benefit: average of pulsed output is a continuous, linear function of phase error Issue: analog loop filter implementation is undesirable 10

Issues with Analog Loop Filter error(t) Charge Pump I cp V out C int ref(t) Phase Detect Analog Loop Filter out(t) Divider VCO Charge pump: output resistance, mismatch Filter caps: leakage current, large area 11

Going Digital ref(t) Phase Detect Analog Loop Filter out(t) Divider VCO ref(t) Time -to- Digital Digital Loop Filter Divider DCO out(t) Staszewski et. al., TCAS II, Nov 2003 Digital loop filter: compact area, insensitive to leakage Challenges: - Time-to-Digital Converter (TDC) - Digitally-Controlled Oscillator (DCO) 12

Classical Time-to-Digital Converter div(t) ref(t) Delay Delay Delay D Q D Q D Q Reg Reg Reg e[k] Delay div(t) 1 1 1 0 0 ref(t) e[k] ref(t) div(t) Time -to- Digital Digital Loop Filter Divider DCO out(t) Resolution set by a Single Delay Chain structure y g y - Phase error is measured with delays and registers Corresponds to a flash architecture 13

Impact of Limited Resolution and Delay Mismatch div(t) 1 1 1 0 0 ref(t) Delay varies due to mismatch e[k] detector output Phase Detector Characteristic phase error ref(t) div(t) Integer-N PLL Time -to- Digital Digital Loop Filter Divider DCO out(t) - Limit cycles due to limited resolution (unless high ref noise) Fractional-N PLL - Fractional spurs due to non-linearity from delay mismatch 14

Examine Noise Performance: Narrow-Bandwidth Case Assumptions: - TDC ΔT= 20ps - carrier freq. = 3.6GHz - reference freq. = 50MHz - PLL BW Total Noise = 50kHz - 3 rd order ΔΣ VCO noise dominates performance everywhere Don t need very high TDC resolution Δ Σ fractional-n quantization noise is not an issue 15

Examine Noise Performance: Wide-Bandwidth Case Assumptions: - TDC ΔT= 20ps - carrier freq. = 3.6GHz - reference freq. = 50MHz - PLL BW = 500kHz - 3 rd order ΔΣ Total Noise Noise dominated by TDC at low frequencies Noise dominated by ΔΣ fractional-n noise at high frequencies 16

To Meet High Performance Applications like GSM. Assumptions: - TDC ΔT = 6ps - carrier freq. = 3.6GHz - reference freq. = 50MHz - PLL BW Total Noise = 500kHz - 3 rd order ΔΣ (20dB lower) Need 6-ps TDC resolution and 20dB cancellation of Δ Σ fractional-n noise to achieve 500kHz bandwidth 17

Can We Improve the Effective Resolution of Time-to-Digital Conversion? 18

Proposed Approach: A Better Time-to-Digital Converter ref(t) Delay Delay Delay out(t) D Q Reg D Q Reg ref(t) () D Q Reg out(t) error[k] ref(t) out(t) S Q R Gated Ring Oscillator enable(t) Straayer, Perrott Logic US Patent in progress ref(t) out(t) enable(t) Oscillator Waveform error[k] This is a simplified view - We will need a few slides to properly explain this 19

Consider Measurement of the Period of a Signal x[0] x[1] x[2] x[3] Ring Oscillator V dd Input Oscillator Reset Counter Count Count Input Register Out Out 3 3 4 3 Use digital logic to count number of oscillator cycles during each input period - Assume that oscillator period is much smaller than that of the input Note: output count per period is not consistent - Depends on starting phase of oscillator within a given measurement period 20

Examine Quantization Error in Measurements x[0] x[1] x[2] x[3] Ring Oscillator V dd Input Oscillator Reset Counter Count Count Input Register Out Out 3 3 4 3 Quantization error varies according to starting phase of the oscillator within a given measurement period - Leads to scrambling of the quantization noise But there is something rather special about the scrambling action 21

A Closer Examination of Quantization Noise x[0] x[1] x[2] x[3] Ring Oscillator V dd Input Oscillator Count Reset Counter q[0] q[1] q[2] q[3] Count Error Input Register -q[0] -q[1] -q[2] -q[3] Out Out 3 3 4 3 Calculate impact of quantization noise in time: Take Z-transform: Quantization noise is first order noise shaped! 22

Relating to Phase Error Between Two Signals x[0] x[1] x[2] x[3] Ring Oscillator V dd Input Oscillator Input Reset Count Counter Count Error q[0] q[1] q[2] q[3] Register -q[0] -q[1] -q[2] -q[3] Out Out 3 3 4 3 Ref PLL Out Time -to- Digital Ref PLL Out Phase Error[0] Gap Phase Error[1] Measurement of phase error between two signals requires gaps between measurements - What is the implication of such gaps? Gap 23

The Impact of Non-Consecutive Measurements x[0] x[2] Ring Oscillator V dd Input Oscillator Input Reset Count Counter Count Error q[0] q[2] Register -q[1] Out Out 3 4 -q[3] Consider measuring input period every other cycle - Analogous to phase measurement between two signals Key observation: - Quantization noise is no longer first order noise shaped! Is there a way to restore noise shaping? 24

Proposed GRO TDC Structure

A Gated Ring Oscillator (GRO) TDC Ring Oscillator Enable div(t) ref(t) Osc(t) Phase Error[1] Phase Error[2] ref(t) div(t) Reset Logic Counter Register Count[k] e[k] Count[k] Quant. q[1] q[2] Error[k] -q[0] -q[1] e[k] 3 4 Enable ring oscillator only during measurement intervals - Hold the state of the oscillator between measurements Quantization error becomes first order noise shaped! - e[k] = Phase Error[k] + q[k] q[k-1] - Averaging dramatically improves resolution! 26

Simple gated ring oscillator inverter-based core Enabled Ring Oscillator Disabled Ring Oscillator (a) Gate the oscillator by switching the inverter cores to the power supply (b) Enable Delay Element Enable Vo n-1 Vo M 3 n Vo5 Vo i-1 Vo i M 4 Vo 4 Vo 1 M 2 Vo 3 Vo 2 Enable M1

Improve Resolution By Using All Oscillator Phases Phase Error[1] Phase Error[2] Ring Oscillator Enable div(t) ref(t) ref(t) Reset Counters Osc. Phases(t) Logic div(t) Register Count[k] e[k] Helal, Straayer, Wei, Perrott VLSI 2007 Count[k] Quant. Error[k] q[1] -q[0] -q[1] e[k] 11 10 Raw resolution is set by inverter delay Effective resolution is dramatically improved by averaging 28 q[2]

GRO TDC Also Shapes Delay Mismatch Measurement 1 Enable Measurement 2 Enable Measurement 3 Enable Measurement 4 Enable Barrel shifting occurs through delay elements across different measurements - Mismatch between delay elements is first order shaped! 29

First Generation GRO Prototype Variable Delay 15 Stage Gated Ring Oscillator S Q R enable(t) enable enable e Logic error[k] GRO implemented as a custom 013 0.13u CMOSIC External setup consists of signal source and variable delay - Test issue: variable delay is nonlinear 30

Measured GRO Results Confirm Noise Shaping Variable Delay 15 Stage Gated Ring Oscillator S Q R enable(t) enable enable 40 30 20 Input variable delay signal Harmonics due to nonlinearity of variable delay Logic error[k] Amplitude (db) 10 0-10 -20 Noise shaped quant. noise -30 0.01 0.1 1 10 100 Frequency (MHz) 31

Next Generation GRO: Multi-path oscillator concept Single Input Single Output Multiple Inputs Single Output Use multiple inputs for each delay element instead of one Allow each stage to optimally begin its transition based on information from the entire GRO phase state t Key design issue is to ensure primary mode of oscillation 32

Multi-path inverter core Lee, Kim, Lee JSSC 1997 Mohan, et. al., CICC 2005

Proposed Multi-Path Gated Ring Oscillator TDC Hsu, Straayer, Perrott ISSCC 2008 Oscillation frequency near 2GHz with 47 stages Reduces effective delay yper stage by a factor of 5-6! Represents a factor of 2-3 improvement compared to previous multi-path oscillators 34

Prototype 0.13μm CMOS Multi-Path GRO-TDC Start Stop Timing Generation Enable 47-stage Gated Ring Oscillator Start Stop Enable CLK Z 1-47 State Register 1 2 3 4 5 6 7 Measurement Cells CLK Adder Out Two implemented versions: - 8-bit, 500Msps Straayer, Perrott VLSI 2008-11-bit, 100Msps version 2-21mW power consumption depending on input duty cycle

Measured noise-shaping of multi-path GRO Power Spec ctral Density (db ps 2 /Hz) -40-50 -60-70 -80-90 65,536 pt. FFT (Hanning window + 20x averaging) Input of 1.2ps pp Noise of 80fs rms in 1MHz BW Ideal variance of 50-Msps quantizer with 1ps steps Filtered TD DC Output 279.2 279.0 278.8-100 278.6 10 4 10 5 10 6 10 7 Frequency (Hz) (a) TDC Output after 1MHz LPF 1.2ps 0 40 80 120 160 200 Time (µs) Data collected at 50Msps More than 20dB of noise-shaping benefit 80fs rms integrated error from 2kHz-1MHz Floor primarily limited by 1/f noise (up to 0.5-1MHz) (b) 36

Can We Reduce Sigma-Delta Quantization Noise Caused by Divider Dithering? 37

The Nature of the Quantization Noise Problem Ref PFD Loop Filter Out Div N/N+1 Frequency M-bit Selection ΔΣ Modulator 1-bit Frequency Selection Quantization Noise Spectrum Output Spectrum Noise F out ΔΣ PLL dynamics Increasing PLL bandwidth increases impact of ΔΣ fractional-n noise - Cancellation offers a way out! 38

Previous Analog Quantization Noise Cancellation Phase error due to ΔΣ is predicted by accumulating ΔΣ quantization error Gain matching between PFD and D/A must be precise Matching in analog domain limits performance 39

Proposed All-digital Quantization Noise Cancellation Hsu, Straayer, Perrott ISSCC 2008 Scale factor determined by simple digital correlation Analog non-idealities such as DC offset are completely eliminated 40

Details of Proposed Quantization Noise Cancellation Correlator out is accumulated and filtered to achieve scale factor - Settling time chosen to be around 10 us See analog version of this technique in Swaminathan et.al., ISSCC 2007 41

Proposed Digital Wide BW Synthesizer Gated-ring-oscillator (GRO) TDC achieves low in-band noise All-digital quantization noise cancellation achieves low out-of-band noise Design goals: - 3.6-GHz carrier, 500-kHz bandwidth - <-100dBc/Hz in-band, <-150 dbc/hz at 20 MHz offset 42

Overall Synthesizer Architecture Note: Detailed behavioral simulation model available at http://www.cppsim.com 43

Dual-Port LC VCO Frequency tuning: - Use a small 1X varactor to minimize noise sensitivity - Use another 16X varactor to provide moderate range - Use a four-bit capacitor array to achieve 3.3-4.1 GHz range 44

Digitally-Controlled Oscillator with Passive DAC Goals of 10-bit DAC - Monotonic 1X varactor minimizes noise sensitivity 16X varactor provides moderate range Af four-bit capacitor array covers 3.3-4.1GHz - Minimal active circuitry and no transistor bias currents - Full-supply output range 45

Operation of 10-bit Passive DAC (Step 1) 5-bit resistor ladder; 5-bit switch-capacitor array Step 1: Capacitors Charged - Resistor ladder forms V L = M/32 V DD and V H = (M+1)/32 V DD, where M ranges from 0 to 31 where M ranges from 0 to 31 - N unit capacitors charged to V H, and (32-N) unit capacitors charged to V L 46

Operation of 10-bit Passive DAC (Step 2) Step 2: Disconnect Capacitors from Resistors, Then Connect Together - Achieves DAC output with first-order filtering - Bandwidth = 32 C u /(2π C load ) 50MHz Determined by capacitor ratio Easily changed by using different C load 47

Now Let s Examine Divider Issues: - GRO range must span entire reference period during initial lock-in 48

Proposed Divider Structure Divide value =N 0 +N 1 +N 2 +N 3 Resample reference with 4x division frequency - Lowers GRO range to one fourth of the reference period 49

Proposed Divider Structure (cont d) Place ΔΣ dithered edge away from GRO edge - Prevents extra jitter due to divide-value dependent delay 50

Dual-Path Loop Filter Step 1: reset Step 2: frequency acquisition - V c (t) varies - V f (t) is held at midpoint Step 3: steady-state lock conditions - V c (t) is frozen to take quantization noise away - ΔΣ quantization noise cancellation is enabled 51

Fine-Path Loop Filter Equivalent to an analog lead-lag filter - Set zero (62.5kHz) and first pole (1.1MHz) digitally - Set second pole (3.1MHz) by capacitor ratio First-order ΔΣ reduces in-band quantization noise 52

Linearized Model of PLL Under Fine-Tune Operation Gain K 2 first-order IIR 1-α 1-αz -1 Accumulator 1 1z 1-z -1 Gain K 1 Φ ref [k] Φ div [k] T 2π TDC Gain 1 Δt del e[k] Loop Filter H(z) z=e j2πft divider 1 N nom ΔΣ 1 DAC Gain V 2 B DT-CT T CT-DT VCO 2πK v s s=j2πf Φ out (t) Standard d lead-lag ag filter topology ogy but implemented e in digital domain - Consists of accumulator plus feedforward path 1 T 53

Same Technique Poses Problems for Coarse-Tune DAC thermal noise impacts performance due to the higher coarse VCO gain - Can we somehow lower the DAC bandwidth? 54

Fix: Leverage the Divider as a Signal Path Bypass to divider for feed- forward path allows coarse DAC bandwidth to be dramatically reduced! 55

Linearized Model of PLL Under Coarse-Tune Operation Φ ref [k] Φ div [k] TDC first-order DAC Gain IIR Accum. Gain DT-CT VCO T 1 e[k] 1-α 1 1 V 2πK vc 4 T 2π Δt del 1-αz -1 1-z -1 64 2 B s K -1 c 2π z 1-z -1 Divider CT-DT 1 T s=j2πf Φ out (t) 1 N nom Routing of signal path into Sigma-Delta controlling the divider yields a feedforward path - Adds to accumulator path as both signals pass back through the divider - Allows reduction of coarse DAC bandwidth Noise impact of coarse DAC on VCO is substantially lowered 56

Die Photo 0.13-μm CMOS Active area: 0.95 mm 2 Chip area: 1.96 mm 2 V DD : 1.5V Current: - 26mA (Core) - 7mA (VCO output buffer at 1.1V) GRO-TDC: - 2.3mA - 157X252 um 2 57

Power Distribution of Prototype IC Divider DAC 1.4mW (3%) 2.8mW (6%) 3.0mW (7%) 3.4mW (7%) 21.0mW VCO (46%) 6.8mW (15%) 7.7mW (17%) Ref. Buffer GRO-TDC Digital VCO Pad Buffer Total Power: 46.1mW Notice GRO and digital quantization noise cancellation have only minor impact on power (and area) 58

Measured Phase Noise at 3.67GHz Suppresses quantization noise by more than 15 db Achieves 204 fs (0.27 degree) integrated noise (jitter) Reference spur: -65dBc 59

Calculation of Phase Noise Components dbc/hz 40 60 80 100 120 VCO Noise Finepath ΣΔ Quantization Noise Fine tune DAC Thermal Coarse tune DAC Thermal Divider Noise (1% left) GRO Noise Ref Noise Close loop Noise 140 160 180 10 3 10 4 10 5 10 6 10 7 f offset See wideband digital synthesizer tutorial available at http://www.cppsim.com 60

Measured Worst Spurs over Fifty Channels -50 Integer boundary -55 (50MHz 73) (dbc) -60 Spur -65-70 16.2us -75 3.62 3.63 3.64 3.65 3.66 3.67 frequency (GHz) Tested from 3.620 GHz to 3.670 GHz at intervals of 1 MHz - Worst spurs observed close to integer-n boundary (multiples of 50 MHz) -42dBc worst spur observed at 400kHz offset from boundary 61

Conclusions Digital Phase-Locked Loops look extremely promising for future applications - Very amenable to future CMOS processes - Excellent performance can be achieved A low-noise, wide-bandwidth digital ΔΣ fractional-n frequency synthesizer is achieved with - High performance noise-shapingshaping GRO TDC - Quantization noise cancellation in digital domain Key result: < 250 fs integrated noise with 500 khz bandwidth Innovation of future digital PLLs will involve joint circuit/algorithm development 62