Frequency Synthesizers for RF Transceivers Domine Leenaerts Philips Research Labs.
Purpose Overview of synthesizer architectures for RF transceivers Discuss the most challenging RF building blocks Technology requirements to achieve optimal performance in RF synthesizers
Outline Basic concept RF synthesizer System architectures & design Dual loop PLL Fractional-N PLL Critical RF building blocks Oscillator Frequency divider High performance synthesizers Concluding remarks
Basic concept synthesizer ADC DEMOD BPF vco synthesizer DAC MOD
Basic concept synthesizer Provide a stable, clean, and programmable local oscillator (LO) signal Indirect method: phase-locking LO output to reference signal Phase-locked Loop (PLL) Invented in 1932 by Bellescize (for synchronous demodulation)
Basic concept synthesizer To RF mixers F out vco K VCO Main Div N F F DIV θ div out PFD K pd = N F ref = N F Ref Div R xtal R F ref F xtal LPF CP θ ref Z f (s) i = pd K pd ( ) θ θ ref div
Basic concept synthesizer Design trade-offs Bandwidth large for optimal dynamic performance (settling time,..) Small for attenuation of unwanted spurs Reference frequency High to reduce main division factor and therefore in-band noise Low to obtain high frequency resolution
Outline Basic concept RF synthesizer System architectures & design Dual loop PLL Fractional-N PLL Critical RF building blocks Oscillator Frequency divider High performance synthesizers Concluding remarks
System Architectures & Design Double Loop PLL F out wide band loop filter PFD1 Div N band vco1 CP1 LPF1 Loop 1 vco2 Div N channel PFD2 Ref Div R LPF2 CP2 F ref F xtal Loop 2 Small band loop filter
System Architectures & Design Fractional-N PLL F out 2 m m F N frac = accumulator N + F 2 m F VCO F DIV vco Div N/N+1 PFD Ref Div R F ref F xtal LPF CP
System Architectures & Design Example: design a Bluetooth synthesizer 1MHz channel spacing GFSK modulation, f = 115kHz t lock = 200 µs for 80MHz step Frequency accuracy: 30 ppm Keep design simple Integer-N architecture Allow near zero-if receiver architecture Reference frequency: 500kHz
System Architectures & Design 2402-2480 MHz 500kHz VCO 2/3 divider PFD 128 C 2 R C 1 64MHz 2/3 divider (12 stages) max 2 n+1-1 (8191) min 2 n (4096)
System Architectures & Design Loop bandwidth (f c ) settling time (t set ) f c then t set and phase noise f c then residual FM f c = t set ζ 1 e ln step ( ) φ f m error f ϕ m = 50 degrees for minimal t set ζ e (ϕ m ) = 2.2 f error = 5 ppm f c = 20kHz
System Architectures & Design R(M Ω ) 4.5M f c = 20kHz C (pf) 4.5 40 450 450.0p 4.0 4.0M 400 400.0p 3.5 3.5M 350 350.0p 3.0 10 2.5 3.0M 2.5M 2.0 2.0M R 1 C 1 300 300.0p 250 250.0p 200 200.0p 1.5 1.5M 150 150.0p 1.0M 500.0k 1.0 0.5 1.0 0.0 0.0 0.0 1.0u 10 100.0u 10.0u I cp = 8 µa R 1 =634 kω, C 1 =34.5 pf, C 2 =5.3 pf C 2 100 100.0p 50 50.0p 0.0 I cp ( µ A)
System Architectures & Design Residual FM spectral density [Hz/sqrt(Hz)] 30.0 30 total 10.0 10 from PLL from loop lter filter 1.0 from VCO 100.0m 0.1 1.0k 10.0k 100.0k 1.0 10 100 1000 Residual FM : 8 khz 1.0M 2.0M 2000 f m (khz)
System Architectures & Design System level design synthesizer done Loop filter Charge pump Gain values of PFD, VCO Focus on critical RF building blocks
Outline Basic concept RF synthesizer System architectures & design Dual loop PLL Fractional-N PLL Critical RF building blocks Oscillator Frequency divider High performance synthesizers Concluding remarks
Critical RF building blocks Voltage Controlled Oscillator High frequency Large tuning range Low phase noise RF Frequency divider Same frequency as VCO Large signal swing
Oscillator VCC V out High-Q inductor Spiral track resistance thick top metal, Al Cu Eddy currents in substrate substrate ρ >= 10 Ωcm Capacitive currents in substrate patterned ground shield, deep trench isolation High-Q varactor Large Cmax/Cmin Large swing: AC coupling collector-base of crosscoupled pair
Oscillator at low frequency the current takes the path of least resistance at high frequency the current takes the path of least inductance this reduces the Q-factor Tiemeijer et al., IEEE Electon Device Let. 2003
Oscillator solution: divide the inductor into several parallel tracks of equal resistance and inductance symmetry is essential!
Oscillator 20 4 // paths 2 // paths Quality factor Q 15 10 5 1 // path 0 0.1 1 10 Frequency, GHz
Oscillator -gm/2 V out Negative admittance is function of technology parameters and frequency ω + T 0.5 1 j ω f Y = limit Veenstra et al., ESSCIRC 03 ω ( ) T R b + Re j + Re ω gm = f T 1 gm 1 + R e ( R + R ) b e
Oscillator For high performance RF oscillators we need: Process with high f T Low base resistance Low emitter resistance Good back-end high performance passives
Oscillator 12 GHz LC VCO 13.5 13 12.5 VCAP VCAP+MIM Oscillation frequency GHz Frequency (GHz) 12 11.5 11 10.5 10 9.5 0 0.5 1 1.5 2 2.5 3 Reverse tuning voltage (V) Ivcc = 10 ma @ 2.5V L(f) = - 85 dbc/hz @ 100kHz SiGe BiCMOS (f T = 65 GHz)
Oscillator 10 GHz LC VCO z H G yc n e u q er F 11 10.8 10.6 10.4 10.2 Bin= 000 Bin= 001 Bin= 010 Bin= 011 Bin= 100 Bin= 101 10 Bin= 110 Bin= 111 0 0.25 0.5 0.75 1 1.25 1.5 1.75 VctrlV Ivcc = 8 ma @ 1.8V L(f) = - 80 dbc/hz @ 100kHz CMOS 0.18um (f T = 70 GHz)
Oscillator I/Q by direct and cross-coupling of 2 identical VCOs In+ VCO 1 Out + In+ VCO Out + Qout+ In- Out- In- 2 Out- Qout- Iout- Iout+ +90 φ Q(α) f osc α -90 f -90 0 +90 α [Degrees]
Oscillator Add zero in transfer function of coupling circuit to enforce α = 0 degrees Common source amplifier with C c 90 degrees phase shift between V gate and I drain In+ Out+ Iout+ VCO1 Qout- Iout- Qout+ In- Out- R c R c C c C c
Oscillator Iout+ Qout- Iout- cross coupling L L L L Qout+ direct coupling Thermometer decoder
Oscillator 0.18 µm CMOS 6 metal layers die area 0.55 mm 2 LQFP package 4 ma @ 1.8 V (7.2 mw) VCO core @ 1.4 V 2.7 f max 2.6 2.5 BThigh 2.4 BTlow 2.3 f min Leenaerts et al., RFIC 2002 2.2 0 5 10 15 20 25 30 35 Digital code word
Oscillator LC-oscillator Good phase noise performance Moderate power dissipation Small tuning range RC-oscillator Moderate phase noise performance High power dissipation Large tuning range
Oscillator VCC R tune Vout R tune R L R L inductance gm L Vin+ Vin- gm A Gain stage I level C: device and interconnect parasitic
Oscillator VCC R tune Vout I R tune R tune Vout Q R tune R L R L R L R L gm L gm L gm A gm A I level I level Quadrature RC oscillator Van der Tang et al., JSSC, 2002
Oscillator 0.5µm BiCMOS (f T 30 GHz) Vdd : 2.7V Pdiss : 230 mw (75 mw VCO core) area :1.5 x 1.5 mm 2
Oscillator 12.0 100 11.5 98 frequency [GHz] 11.0 10.5 10.0 96 94 CNR (2 MHz) [dbc/hz] 9.5 9.0 frequency CNR -1.8-1.2-0.6 0.0 0.6 1.2 Differential Vtune [V] 16% tuning range @ 10GHz 92 90 PN better than -94dBc @ 2MHz
Frequency divider First few stages in main divider are fixed frequency dividers High speed prescaler Rest of main divider is programmable Dual-modulus division (2/3) VCO DIV-2 DIV- 2/3 DIV- 2/3 To PFD Division from F vco /8 to F vco /14
Frequency divider D-latch1 D-latch2 D Q D Q f div Parasitic capacitances limit high frequency operation C par ck Gate pair D ck Q Latch pair I bias
Frequency divider less parasitic capacitances Gate pair smaller transistors Q D ck I gate I latch Vaucher et al., RFIC, 2002 smaller bias current
Frequency divider Supply voltage 2.7 V Current: 1 st divider cell 4 ma 2 nd and 3 rd cells 4 ma input amplifier 4 ma output amplifier 8 ma total 20 ma Power dissipation 1 st cell 11 mw total 57 mw Active size 90 x 390 µm 2 BiCMOS: f T = 37 GHz, f max = 50-90 GHz double-poly, shallow- and deep-trench isolation
Frequency divider Sensitivity as a function of the latch current Minimum Input Power (dbm) 10 5 0-5 -10-15 -20-25 -30-35 -40 I latch = 1.2 ma I latch = 400 ua Il=400uA Il=600uA Il=850uA Il=1.2mA 0 5 10 15 20 Input Frequency (GHz)
Frequency divider 2/3 CELL prescaler logic P=0: divide-by-2 2/3 Dlatch 1 D Q Dlatch 2 D Q P=1: divide-by-3 ck ck Q F o F in mod out Dlatch 3 Q D Q ck Dlatch 4 Q Q D ck end-of-cycle logic mod in Mod in : end-ofcycle p
Outline Basic concept RF synthesizer System architectures & design Dual loop PLL Fractional-N PLL Critical RF building blocks Oscillator Frequency divider High performance synthesizers Concluding remarks
High Performance RF Synthesizers Most RF synthesizers operate in the 1-5 GHz range Cellular (GSM, PCS, WCDMA,..) Wireless data (11b, 11a, Bluetooth, UWB) High performance in Spectral purity Noise performance Power dissipation Often used architecture: Fractional-N Sigma-Delta synthesizer
High Performance RF Synthesizers Fractional-N Sigma-Delta synthesizer large bandwidth and high frequency resolution large bandwidth enables full integration of LFP large bandwidth allows fast frequency switching high reference frequency leads to lower division factors, thus low in-band noise Direct-modulation of VCO in constant-amplitude modulation systems: GFSK/GMSK
High Performance RF Synthesizers 5GHz vco I/Q 2.5GHz Sigma-delta modulator 1/2 1 2 5 5 stages div-2/3 CP PFD 10MHz 2-15 counter F xtal 10bits SDM gives 10kHz resolution
High Performance RF Synthesizers For high speed reasons, the div-2 stages are in differential CML bipolar SDM and counter are in CMOS Consequently, we need CML-to-digital converters CP and PFD in CMOS low frequency small die area
High Performance RF Synthesizers I/Q 2.5GHz coder vco 1 2 12 12 stages div-2/3 CP PFD 500kHz 128 Leenaerts et al., JSSC 2003 64MHz F xtal
High Performance RF Synthesizers 0.18 µm CMOS 6 metal layers die area 1.1 mm 2 LQFP package 8.2 ma @ 1.8 V (15 mw) FR-4 PCB
High Performance RF Synthesizers closed-loop f c = 20 khz reference breakthrough: -30 dbc @ 500 khz offset Spec: -18 dbc
High Performance RF Synthesizers Residual FM (HP3048A) I/Q Measurement (R&S FSIQ) Gain error : < 0.4 db Phase error : < 1.2 degrees IRR: > 20 db Residual FM is 7.5 khz up to 500 khz
Conclusion Integer-N and fractional-n synthesizers most often used architectures Critical RF blocks: VCO and frequency divider New technologies allow for high performance synthesizers IC design of microwave applications satellite @ 30 GHz; car radar @ 24 GHz