RF, HIL and Radar Test Abhay Samant Marketing Manager India, Russia and Arabia
RF Hardware In The Loop Complex Radio Environment Components of RF HIL Communication Modems Channel Simulation GPS Simulation 2
Complex Radio Environment Navigational Aids Radiation pattern Channel Interference Amplifier Analog Tx Chain Platform Dynamics Amplifier Analog Rx Chain Processor DUT Transmitter v x Platform Trajectory Topography Processor DUT Receiver 3
Modeling Navigation Signals Interference Navigation Signals Tx Antenna Model Platform Dynamics Channel Topography Rx Antenna Model Amplifier Analog Tx Chain Processor DUT Transmitter Channel Model Amplifier Analog Tx Chain Processor DUT Receiver 4
Hardware-in Loop System Navigation Signals Channel Interference Navigation Signals Switch Switch Amplifier Analog Tx Chain Processor Golden Transmitter Message Signal (Raw Data) Golden Receiver Measurements Amplifier Analog Tx Chain Processor DUT Transmitter Demodulated data DUT Receiver 5
Hardware in-loop Subsystem level Amplifier RF Analog Tx Chain RF Test System Processor IF Digital 6
Receiver in-loop Modulated RF BPSK Modulation Rate ½ Convolution Code Input PN Sequence Data rate 2 Mbps Bandwidth 4 MHz Frequency range up to 6GHz Channel Simulator Rayleigh fading Rician fading AWGN IQ Gain Imbalance Phase Imbalance Receiver (VSA) Channel (FPGA) IF path path Transmitter (VSG) RF path Channel Distorted Modulated RF path Modem (FPGA) Modulation Simulator RF Tx+Rx (VSA + VSG) BERT + Modulation Measurements (FPGA DIO) DUT DUT IF DUT RF DUT DUT RF Frontend Demodulated bits and Clock 2Mbps 7
Channel Modeling FPGA Channel Models 8
Standard Channel Implementation Rician Rayleigh AWGN 9 Multitone
Generic models Case Study : octofade System Architecture Emulator Applications GUI 802.11n/ac Profile API GSM Profile API WCDMA Profile API LTE Profile API CDMA Profile API WiMAX Profile API Emulator API NI VST Note: greyed out profiles (802.11n/ac, CDMA and WiMAX) will be integrated in the future; 802.11n/ac logic currently available in software Altera FPGA board 3GPP Compliant Channel Fader 10 VST = vector signal transceiver
Complex Channel Modeling Channel Modeling Antenna Model Platform Dynamics Topography/ Terrain Model Atmospheric Model Motion Trajectory User Inputs Scenarios 3 rd -party Modeling Software IQ File Streaming through Generator Software Modeling Hardware 11
NI GPS Simulator Generate 24 hours of up to 12 satellite C/A codes (L1) Achieve automatic satellite simulation from almanac and ephemeris files Define custom motion trajectories for mobile simulation Adjust individual satellite power levels for scenario-specific test Take advantage of manual control of satellite pseudo-range, Doppler, and power-level information Generate WAAS satellites 12
Specifications Output Frequency L1 1575.42 MHz C/A code Signal Quality Phase Noise: -82 dbc at 100 Hz offset Spurious 2 nd Harmonic: -40dBC max Output 3 rd order distortion: -75dBC typical Power Output -145 dbm to 10 dbm 13
Modern Architecture of RADAR Analog RF Section T R M Receiver Front End Transmitter Front End ADC DAC DDC Signal Processing DBF ADBF MTI MTD PC Data Processing MW RWC CFAR Tracker 2B filter KF EKF PF Active Phased Array Antenna Beamsteering Control Weveforms Generation RADAR Console 14
RADAR Design, Test and Validation 15
Components IF Mixer Filters RF Mixer Power Amplifier Antenna Modulator T/R Switch STALO COHO Limiter processing Video 16
Parametric Measurements Modulator Measurements VSWR Isolation Insertion Loss Max Power Switching Time Antenna T/R Switch STALO COHO Limiter processing Video Measurements Sensitivity Selectivity Dynamic range Noise Floor Pulse Mx 17 Measurements VSWR Noise Figure Bandwidth Gain Linearity 1dB Compression IMD/ ToI