Benefits l Ultra-Low Gate Impedance l Very Low RDS(on) at 4.5V V GS l Fully Characterized Avalanche Voltage and Current Absolute Maximum Ratings SMPS MOSFET Applications l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use l High Frequency Buck Converters for Server Processor Power Synchronous FET l Optimized for Synchronous Buck Converters Including Capacitive Induced Turn-on Immunity l Lead-Free IRF3709PbF IRF3709SPbF IRF3709LPBF HEXFET Power MOSFET V DSS R DS(on) max I D 30V 9.0mΩ 90A TO-220AB IRF3709 D 2 Pak IRF3709S PD - 95495 TO-262 IRF3709L Symbol Parameter Max. Units V DS Drain-Source Voltage 30 V V GS Gate-to-Source Voltage ± 20 V I D @ T C = 25 C Continuous Drain Current, V GS @ 10V 90 I D @ T C = 100 C Continuous Drain Current, V GS @ 10V 57 A I DM Pulsed Drain Current 360 P D @T C = 25 C Maximum Power Dissipationƒ 120 W P D @T A = 25 C Maximum Power Dissipation 3.1 W Linear Derating Factor 0.96 mw/ C T J, T STG Junction and Storage Temperature Range -55 to 150 C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.04 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 R θja Junction-to-Ambient (PCB mount) 40 Notes through are on page 11 www.irf.com 1 07/01/04
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 30 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.029 V/ C Reference to 25 C, I D = 1mA 6.4 9.0 V GS = 10V, I D = 15A ƒ R DS(on) Static Drain-to-Source On-Resistance mω 7.4 10.5 V GS = 4.5V, I D = 12A ƒ V GS(th) Gate Threshold Voltage 1.0 3.0 V V DS = V GS, I D = 250µA 20 V µa DS = 24V, V GS = 0V I DSS Drain-to-Source Leakage Current 100 V DS = 24V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage 200 V GS = 16V na Gate-to-Source Reverse Leakage -200 V GS = -16V Dynamic @ T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 53 S V DS = 15V, I D = 30A Q g Total Gate Charge 27 41 I D = 15A Q gs Gate-to-Source Charge 6.7 nc V DS = 16V Q gd Gate-to-Drain ("Miller") Charge 9.7 V GS = 5.0V ƒ Q oss Output Gate Charge 22 V GS = 0V, V DS = 10V t d(on) Turn-On Delay Time 11 V DD = 15V t r Rise Time 171 I ns D = 30A t d(off) Turn-Off Delay Time 21 R G = 1.8Ω t f Fall Time 9.2 V GS = 4.5V ƒ C iss Input Capacitance 2672 V GS = 0V C oss Output Capacitance 1064 pf V DS = 16V C rss Reverse Transfer Capacitance 109 ƒ = 1.0MHz Avalanche Characteristics Symbol Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 382 mj I AR Avalanche Current 30 A Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 90 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 360 (Body Diode) p-n junction diode. S 0.88 1.3 V T J = 25 C, I S = 30A, V GS = 0V ƒ V SD Diode Forward Voltage 0.82 T J = 125 C, I S = 30A, V GS = 0V ƒ t rr Reverse Recovery Time 48 72 ns T J = 25 C, I F = 30A, V R =15V Q rr Reverse Recovery Charge 46 69 nc di/dt = 100A/µs ƒ t rr Reverse Recovery Time 48 72 ns T J = 125 C, I F = 30A, V R =15V Q rr Reverse Recovery Charge 52 78 nc di/dt = 100A/µs ƒ 2 www.irf.com
I D, Drain-to-Source Current (A) 100 10 VGS TOP 15V 10V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM2.7V 2.7V I D, Drain-to-Source Current (A) 100 10 VGS TOP 15V 10V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM2.7V 2.7V 20µs PULSE WIDTH T J = 25 C 1 0.1 1 10 100 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH 1 T J = 150 C 0.1 1 10 100 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 100 T J = 25 C T J = 150 C V DS= 15V 20µs PULSE WIDTH 10 2.0 3.0 4.0 5.0 6.0 7.0 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.0 I D = 90A 1.5 1.0 0.5 V GS= 10V 0.0-60 -40-20 0 20 40 60 80 100 120 140 160 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance (pf) 4000 3000 2000 VGS = 0V, f = 1MHz Ciss = Cgs Cgd, C ds Crss = Cgd Coss = Cds Cgd C iss C oss SHORTED V GS, Gate-to-Source Voltage (V) 6 5 4 3 2 1 I D = 30A V DS= 24V V DS= 15V V DS= 6V C rss 0 1 10 100 V DS, Drain-to-Source Voltage (V) 0 0 5 10 15 20 25 30 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 100 10 1 T J = 150 C T J = 25 C V GS = 0 V 0.1 0.2 0.8 1.4 2.0 2.6 V SD,Source-to-Drain Voltage (V) 0 I D, Drain Current (A) 100 OPERATION IN THIS AREA LIMITED BY R DS(on) 10us 100us 1ms 10 10ms TC = 25 C TJ = 150 C Single Pulse 1 1 10 100 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
100 LIMITED BY PACKAGE V DS R D 80 R G V GS D.U.T. I D, Drain Current (A) 60 40 V GS Pulse Width 1 µs Duty Factor 0.1 % Fig 10a. Switching Time Test Circuit - V DD 20 V DS 90% 0 25 50 75 100 125 150 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% V GS t d(on) t r t d(off) t f Fig 10b. Switching Time Waveforms 10 Thermal Response(Z thjc ) 1 0.1 D = 0.50 0.20 0.10 0.05 0.02 SINGLE PULSE t2 0.01 (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 0.01 2. Peak T J=P DM x Z thjc TC 0.00001 0.0001 0.001 0.01 0.1 1 t 1, Rectangular Pulse Duration (sec) PDM t1 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
R G V DS 20V tp Fig 12a. Unclamped Inductive Test Circuit tp L D.U.T IAS 0.01Ω 15V V (BR)DSS DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) 1200 800 600 400 200 TOP BOTTOM I D 13A 19A 30A 0 25 50 75 100 125 150 Starting T, Junction Temperature( J C) I AS Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF V GS Q GS Q GD D.U.T. V - DS V GS V G 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =10V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET Power MOSFETs www.irf.com 7
TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) - A - 4.69 (.185) 4.20 (.165) - B - 1.32 (.052) 1.22 (.048) 15.24 (.600) 14.84 (.584) 14.09 (.555) 13.47 (.530) 1 2 3 4 6.47 (.255) 6.10 (.240) 1.15 (.045) MIN 4.06 (.160) 3.55 (.140) LEAD ASSIGNMENTS LEAD ASSIGNMENTS HEXFET IGBTs, CoPACK 1 - GATE 1- GATE 2 - DRAIN 1- GATE 2- DRAIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRAIN 3- EMITTER 4- DRAIN 4- COLLECTOR 3X 1.40 (.055) 1.15 (.045) 3X 0.93 (.037) 0.69 (.027) 0.36 (.014) M B A M 3X 2.92 (.115) 2.64 (.104) 0.55 (.022) 0.46 (.018) 2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: T HIS IS AN IRF1010 LOT CODE 1789 AS S EMB LE D ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INT E R NAT IONAL R E CT IF IE R LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C 8 www.irf.com
D 2 Pak Package Outline Dimensions are shown in millimeters (inches) D 2 Pak Part Marking Information T HIS IS AN IRF530S WITH LOT CODE 8024 AS S EMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" Note: "P" in ass embly line position indicates "Lead-Free" OR INTERNAT IONAL RECT IFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L INT ERNATIONAL RECTIFIER LOGO AS S E MBL Y LOT CODE F530S PART NUMBER DATE CODE P = DESIGNAT ES LEAD-FREE PRODUCT (OPTIONAL) YEAR 0 = 2000 WEEK 02 A = ASSEMBLY SITE CODE www.irf.com 9
TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" OR INTERNATIONAL RECT IF IER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C INTERNATIONAL RECT IF IER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = ASSEMBLY SITE CODE 10 www.irf.com
D 2 Pak Tape & Reel Information Dimensions are shown in millimeters (inches) IRF3709/S/LPbF TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065) 10.90 (.429) 10.70 (.421) 11.60 (.457) 11.40 (.449) 16.10 (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.85mH R G = 25Ω, I AS = 30A. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 ƒ Pulse width 400µs; duty cycle 2%. This is only applied to TO-220AB package This is applied to D 2 Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.07/04 www.irf.com 11
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/