P-Channel 3-V (D-S) MOSFET These miniature surface mount MOSFETs utilize a high cell density trench process to provide low r DS(on) and to ensure minimal power loss and heat dissipation. Typical applications are DC-DC converters and power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. PRODUCT SUMMARY V DS (V) r DS(on) m(ω) I D (A) 3 @ V GS = -V -.5-3 9 @ V GS = -4.5V -9.3 Low r DS(on) provides higher efficiency and extends battery life Low thermal impedance copper leadframe SOIC-8 saves board space Fast switching speed High performance trench technology 8 7 3 6 4 5 ABSOLUTE MAXIMUM RATINGS (T A = 5 o C UNLESS OTHERWISE NOTED) Symbol Maximum Units Drain-Source Voltage V DS -3 V Gate-Source Voltage V GS ±5 T A =5 o C -.5 Continuous Drain Current a I T A =7 o D C -9.3 A Pulsed Drain Current b Continuous Source Current (Diode Conduction) a Power Dissipation a I DM ±5 I S -. A T A =5 o C 3. T A =7 o C.3 Operating Junction and Storage Temperature Range T J, T stg -55 to 5 P D W o C THERMAL RESISTANCE RATINGS Notes a. Surface Mounted on x FR4 Board. b. Pulse width limited by maximum junction temperature Symbol Maximum Units Maximum Junction-to-Case a t <= 5 sec R θjc 5 o C/W Maximum Junction-to-Ambient a t <= 5 sec R θja 5 o C/W
SPECIFICATIONS (T A = 5 o C UNLESS OTHERWISE NOTED) Symbol Test Conditions Limits Min Typ Max Unit Static Drain-Source Breakdown Voltage V (BR)DSS V GS = V, I D = -5 ua -3 Gate-Threshold Voltage V GS(th) V DS = V GS, I D = -5 ua - V Gate-Body Leakage I GSS V DS = V, V GS = ±5 V ± na Zero Gate Voltage Drain Current I DSS V DS = -4 V, V GS = V - V DS = -4 V, V GS = V, T J = 55 o C -5 ua On-State Drain Current A I D(on) V DS = -5 V, V GS = - V -5 A Drain-Source On-Resistance A r DS(on) V GS = - V, I D = -.5 A 3 V GS = -4.5 V, I D = -9.3 A 9. mω Forward Tranconductance A g fs V DS = -5 V, I D = -.5 A 9 S Diode Forward Voltage V SD I S =.5 A, V GS = V -.8 V Dynamic b Total Gate Charge Q g 64 V DS = -5 V, V GS = - V, Gate-Source Charge Q gs I D = -.5 A Gate-Drain Charge Q gd 7 Input Capacitance C iss 3 Output Capacitance C oss V DS =-5V, V GS =V, f=mhz 6 Reverse Transfer Capacitance C rss 3 Turn-On Delay Time t d(on) 5 Rise Time t r V DD = -5 V, R L = 6 Ω, ID 3 Turn-Off Delay Time t d(off) = - A, VGEN = - V Fall-Time t f 54 nc pf ns Notes a. Pulse test: PW <= 3us duty cycle <= %. b. Guaranteed by design, not subject to production testing. Analog Power (APL) reserves the right to make changes without further notice to any products herein. APL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does APL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in APL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. APL does not convey any license under its patent rights nor the rights of others. APL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the APL product could create a situation where personal injury or death may occur. Should Buyer purchase or use APL products for any such unintended or unauthorized application, Buyer shall indemnify and hold APL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that APL was negligent regarding the design or manufacture of the part. APL is an Equal Opportunity/Affirmative Action Employer.
Typical Electrical Characteristics (P-Channel) -5-4 4V thru v 3.5 V.3.6-3 - - 3 V.5 V R (Ω)..8.4 Vgs = 4.5V Vgs = V - - VDS - Drain to Source Voltage (V) Figure. On-Region Characteristics -3. -4-8 - -6 ID - Drain Current (A) Figure. On-Resistance Variation with Drain Current and Gate Voltage - Normalized RDS (on).6.5.4.3....9.8.7.6 V GS = V I D =.5 A -5-5 5 5 75 5 5 T J - Juncation Temperature (ºC) Figure 3. On-Resistance Variation with Temperature R (Ω).5.4.3 ID =.5a.. Figure 6. Body Diode Forward 4 Voltage 6 Variation 8 with Source VGS Current - Gate and to Temperature Source Voltage (V) Figure 4. On-Resistance with Gate to Source Voltage -5 5C IS - Source Current (A) TJ = 5 C TJ = 5 C I - Drain Current (A) -4-3 - - -55C 5C...4.6.8. VSD - Source to Drain Current (V) Figure 5. Transfer Characteristics - - -3-4 -5 VGS - Gate to Source Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature 3
Typical Electrical Characteristics (P-Channel) V GS Gate to Source Voltage (V) 8 6 4 V DS = V 3 4 5 Capacitance (pf) 4 3-5 CISS CRSS COSS - -5 - Q GS, Total Gate Charge (nc) V DS (V) Figure 7. Gate Charge Characteristics Figure 8. Capacitance Characteristics V Variance (V).8.6.4. -. -.4-5 -5 5 5 75 5 5 T J - Juncation Temperature (ºC) Power (W) 5 45 4 35 3 5 5 5.. Figure 9. Maximum Safe Operating Area Pulse Time (S) Figure. Single Pulse Maximum Power Dissipation.5 Normalized Thermal Transient Junction to Ambient.. PDM..5 t t. Single Pulse. Duty Cycal D = t/t. Per Unit Base RθJA =7C/W 3. TJM - TA = PDM Zθjc 4. Sureface Mounted..... Square Wave Pulse Duration (S) Figure. Transient Thermal Response Curve 4
Package Information SO-8: 8LEAD H x 45 5