High Speed 8 MHz Bandwidth (G =, 3 db) V/µs Slew Rate -ns Settling Time (.%) High Output Drive, I O = 5 ma (typ) Excellent Video Performance 75 MHz. db Bandwidth (G = ).2% Differential Gain.2 Differential Phase Very Low Distortion THD = 72 dbc at f = MHz Wide Range of Power Supplies V CC = ±5 V to ±5 V Available in Standard SOIC or MSOP PowerPAD Package Evaluation Module Available THS6 D AND DGN PACKAGE (TOP VIEW) NULL IN IN V CC THS62 D AND DGN PACKAGE (TOP VIEW) OUT IN IN V CC 2 3 2 3 8 7 6 5 8 7 6 5 NULL V CC OUT NC NC No internal connection V CC 2OUT 2IN 2IN description The THS6 and THS62 are generalpurpose, single/dual, high-speed voltage feedback amplifiers ideal for a wide range of applications including video, communication, and imaging. The devices offer very good ac performance with 8-MHz bandwidth, -V/µs slew rate, and -ns settling time (.% ). The THS6/2 are stable at all gains for both inverting and noninverting configurations. These amplifiers have a high output drive capability of 5 ma and draw only 7.8 ma supply current per channel. Excellent professional video results can be obtained with the low differential gain/phase errors of.2%/.2 and wide. db flatness to 75 MHz. For applications requiring low distortion, the THS6/2 is ideally suited with total harmonic distortion of 72 dbc at f = MHz. VI 2 kω _ This product is in the product preview stage of development. For information on availability, contact the local TI sales office. THS6 2 kω 75 Ω LINE DRIVER (G = 2) 75 Ω VO 75 Ω DEVICE ARCH. SUPPLY VOLTAGE VFB CFB 5 V ±5 V ±5 V HIGH-SPEED AMPLIFIER FAMILY BW (MHz) SR (V/µs) THD f = MHz (db) ts.% (ns) DIFF. DIFF. Vn GAIN PHASE (nv/ Hz) THS3 2 65 96.%.2.6 THS 27 72.%.5 2.5 THS3/32 72 6.2%.3.6 THS6/62 8 72.2%.2.5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Insruments Incorporated. This document contains information on products in more than one phase of development. The status of each device is indicated on the page(s) specifying its electrical characteristics. Copyright 999, Texas Instruments Incorporated POST OFFICE BOX 65533 DALLAS, TEXAS 75265
TA C to7 C NUMBER OF CHANNELS AVAILABLE OPTIONS PLASTIC SMALL OUTLINE (D) PACKAGED DEVICES PLASTIC MSOP (DGN) MSOP SYMBOL EVALUATION MODULES THS6CD THS6CDGN TIABS THS6EVM 2 THS62CD THS62CDGN TIABM THS62EVM THS6ID THS6IDGN TIABT C to85 C 2 THS62ID THS62IDGN TIABN The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS6CDGNR). This product is in the product preview stage of development. For information on availability, contact the local TI sales office. functional block diagram Null IN IN 2 3 8 6 OUT Figure. THS6 Single Channel VCC IN IN 2 3 8 OUT 2IN 2IN 6 5 7 2OUT VCC Figure 2. THS62 Dual Channel CAUTION: The THS6 and THS62 provide ESD protection circuitry. However, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss of functionality 2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, V CC to V CC.............................................................. 33 V Input voltage, V I.......................................................................... ±V CC Output current, I O....................................................................... 5 ma Differential input voltage, V IO................................................................ ± V Continuous total power dissipation..................................... See Dissipation Rating Table Maximum junction temperature, T J......................................................... 5 C Operating free-air temperature, T A : C-suffix........................................... C to 7 C I-suffix.......................................... C to 85 C Storage temperature, T stg......................................................... 65 C to 5 C Lead temperature,,6 mm (/6 inch) from case for seconds............................... 3 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PACKAGE DISSIPATION RATING TABLE TA 25 C DERATING FACTOR TA = 7 C TA = 85 C POWER RATING ABOVE TA = 25 C POWER RATING POWER RATING D 7 mw 6 mw/ C 75 mw 385 mw DGN 2. W 7. mw/ C.37 W. W The DGN package incorporates a PowerPAD on the underside of the device. This acts as a heatsink and must be connected to a thermal dissipation plane for proper power dissipation. Failure to do so can result in exceeding the maximum specified junction temperature, which could permanently damage the device. recommended operating conditions Supply voltage, VCC and VCC Operating free-air temperature, TA MIN NOM MAX UNIT Dual supply ±.5 ±6 Single supply 9 32 V C-suffix 7 I-suffix 85 C POST OFFICE BOX 65533 DALLAS, TEXAS 75265 3
electrical characteristics at T A = 25 C, V CC = ±5 V, R L = 5 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dual supply ±.5 ±6.5 VCC Supply voltage operating range V Single supply 9 33 7.8.5 ICC Quiescent current (per amplifier) TA = full range 7.3 RL = 25 Ω ±.5 ±2.5 VO Output voltage swing IO Output current RL = 5 Ω ±3.2 ±3.5 ma V ±3 ±3.5 RL =kω ±3.5 ±3.7 V 8 5 RL =2Ω Ω 5 75 ma ISC Short-circuit current 5 ma 8 Gain = Dynamic performance small-signal 8 MHz BW bandwidth ( 3 db) 5 Gain = 5 MHz Bandwidth for. db flatness 75 Gain = 2 MHz VOS Input offset voltage or ±5 V 2.5 8 mv TA = full range Offset drift or ±5 V 5 µv/ C IIB Input bias current or ±5 V TA = full range 3 6 µa IOS Input offset current or ±5 V TA = full range 75 25 na Offset current drift TA = full range.3 na/ C CMRR Common mode rejection ratio, VICR = ±2 V 7 TA = full range, VICR = ±2.5 V 7 95 db PSRR Power supply rejection ratio or ±5 V TA = 25 C 7 78 TA = full range 68 db VICR Common-mode mode input voltage range ±3.8 ±. ±3.8 ±.3 V RI Input resistance MΩ Ci Input capacitance 2 pf RO Output resistance Open loop 2 Ω Channel-to-channel crosstalk (THS62 only) or ±5 V, f = MHz 65 db Full range = C to 7 C for C suffix and C to 85 C for I suffix POST OFFICE BOX 65533 DALLAS, TEXAS 75265
operating characteristics at T A = 25 C, V CC = ±5 V, R L = 5 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Slew rate Gain = 35 V/µs ts Settling time to.%, 5-V step ( V to 5 V) Gain =, VO = 2.5 V to 2.5 V, ns Settling time to.% %, 5-V step ( V to 5 V) Gain =, VO = 2.5 V to 2.5 V, 5 ns THD Total harmonic distortion f = MHz 72 dbc Differential gain error Gain = 2, NTSC, IRE Modulation.2%.2% Differential phase error Gain = 2, NTSC, IRE Modulation.2.6 Open loop gain TA = 25 C 5 5, VO = ± V, RL =kω V/mV TA = full range TA = 25 C 2.5 8, VO=±25V ±2.5 V, RL=kΩ V/mV TA = full range 2 Vn Input voltage noise f = khz, or ±5 V.5 nv/ Hz In Input current noise f = khz, or ±5 V.6 pa/ Hz Full range = C to 7 C for C suffix and C to 85 C for I suffix TYPICAL CHARACTERISTICS Table of Graphs FIGURE IIB Input bias current Free-air temperature 3 VIO Input offset voltage Free-air temperature Open-loop gain Frequency 5 Phase Frequency 5 Differential gain Number of loads 6, 8 Differential phase Number of loads 7, 9 Closed-loop gain Frequency, Output Amplitude Frequency 2, 3 CMRR Common-mode rejection ratio Frequency PSRR Power-supply rejection ratio Frequency 5 Free-air temperature 6 VO(PP) Output voltage swing Supply voltage 7 ICC Supply current Free-air temperature 8 Env Noise spectral density Frequency 9 THD Total harmonic distortion Frequency 2, 2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 5
TYPICAL CHARACTERISTICS INPUT BIAS CURRENT FREE-AIR TEMPERATURE INPUT OFFSET VOLTAGE FREE-AIR TEMPERATURE, ±5 V.5 IIB Input Bias Current µ A 3.5 3 2.5 VIO Input Offset Voltage mv.5 2 2.5 3 2 2 2 6 8 TA Free-Air Temperature C Figure 3 3.5 2 2 6 8 TA Free-Air Temperature C Figure OPEN-LOOP GAIN AND PHASE 9 8 7 Open-Loop Gain db 6 5 3 Phase 5 9 Phase 2 35 k k k M M M f Frequency Hz 8 G Figure 5 6 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS.%.2% DIFFERENTIAL GAIN LOADING Gain = 2 RF = 68 Ω IRE NTSC Worst Case ± IRE Ramp.7.6 DIFFERENTIAL PHASE LOADING Gain = 2 RF = 68 Ω IRE NTSC Worst Case ± IRE Ramp.%.5 Differential Gain.8%.6%.% VCC = ±5 Gain VCC = ±5 Gain Differential Phase..3.2 VCC = ± 5 Phase VCC = ± 5 Phase.2%. % 2 3 2 3 Number of 5 Ω Loads Number of 5 Ω Loads Figure 6 Figure 7.2% DIFFERENTIAL GAIN LOADING DIFFERENTIAL PHASE LOADING.8%.6% Gain = 2 RF = 68 Ω IRE PAL Worst Case ± IRE Ramp.9.8 Gain = 2 RF = 68 Ω IRE PAL Worst Case ± IRE Ramp Differential Gain.%.2%.%.8%.6%.% VCC = ±5 Gain VCC = ±5 Gain Differential Phase.7.6.5..3.2 VCC = ±5 Phase VCC = ±5 Phase.2%. % 2 3 2 3 Number of 5 Ω Loads Number of 5 Ω Loads Figure 8 Figure 9 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 7
TYPICAL CHARACTERISTICS 2 CLOSED-LOOP GAIN 5 CLOSED-LOOP GAIN Closed-Loop Gain db 2 6 8 Gain = 2 RF = 27 Ω RL = 5 Ω k M M M f Frequency Hz Figure G Closed-Loop Gain db 5 5 2 k, ±5 V Gain = RF = 5 Ω RL = 5 Ω M M M f Frequency Hz Figure G OUTPUT AMPLITUDE 2 OUTPUT AMPLITUDE 2 RF = kω RF = 5 Ω Output Amplitude db 2 RF = 27 Ω RF = 2 Ω Output Amplitude db 2 6 RF = 3 kω 6 Gain = RL = 5 Ω 8 k M M M G f Frequency Hz Figure 2 8 Gain = RL = 5 Ω k M M M G f Frequency Hz Figure 3 8 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS CMRR Common-Mode Rejection Ratio db 2 8 6 2 COMMON-MODE REJECTION RATIO, ±5 V k k M M M f Frequency Hz Figure PSRR Power Supply Rejection Ratio db 8 7 6 5 3 2 POWER SUPPLY REJECTION RATIO, ±5 V k k k M M M f Frequency Hz Figure 5 9 POWER SUPPLY REJECTION RATIO FREE-AIR TEMPERATURE 3 OUTPUT VOLTAGE SWING SUPPLY VOLTAGE PSRR Power Supply Rejection Ratio db 88 86 8 82 8 78 76 7 VCC = 5 V VCC = 5 V VO(PP) Output Voltage Swing V 25 2 5 5 RL = kω RL = 5 Ω 72 2 2 6 8 TA Free-Air Temperature C Figure 6 ± ±6 ±8 ± ±2 ± ±6 VCC Supply Voltage V Figure 7 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 9
TYPICAL CHARACTERISTICS ICC Supply Current ma 9 8 7 6 5 SUPPLY CURRENT FREE-AIR TEMPERATURE Env Noise Spectral Density nv/ Hz 8 6 2 8 6 2 TA = 25 C NOISE SPECTRAL DENSITY 2 2 6 8 TA Free-Air Temperature C Figure 8 k k f Frequency Hz Figure 9 k THD Total Harmonic Distortion db 5 6 7 8 9 TOTAL HARMONIC DISTORTION Gain = 2 RL = 5 Ω 2nd Harmonic 3rd Harmonic THD Total Harmonic Distortion db 5 6 7 8 9 TOTAL HARMONIC DISTORTION Gain = 2 RL = 5 Ω 2nd Harmonic 3rd Harmonic k M f Frequency MHz Figure 2 M k M f Frequency MHz Figure 2 M POST OFFICE BOX 65533 DALLAS, TEXAS 75265
APPLICATION INFORMATION theory of operation The THS6x is a high speed, operational amplifier configured in a voltage feedback architecture. It is built using a 3-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing f T s of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 22. (7) VCC IN (2) (6) OUT IN (3) () VCC NULL () NULL (8) Figure 22. THS6 Simplified Schematic POST OFFICE BOX 65533 DALLAS, TEXAS 75265
offset nulling APPLICATION INFORMATION The THS6 has very low input offset voltage for a high-speed amplifier. However, if additional correction is required, an offset nulling function has been provided. By placing a potentiometer between terminals and 8 and tying the wiper to the negative supply, the input offset can be adjusted. This is shown in Figure 23. VCC. µf THS6 _ kω. µf VCC Figure 23. Offset Nulling Schematic optimizing unity gain response Internal frequency compensation of the THS6x was selected to provide very wideband performance yet still maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated in this manner there is usually peaking in the closed loop response and some ringing in the step response for very fast input edges, depending upon the application. This is because a minimum phase margin is maintained for the G= configuration. For optimum settling time and minimum ringing, a feedback resistor of 27 Ω should be used as shown in Figure 2. Additional capacitance can also be used in parallel with the feedback resistance if even finer optimization is required. Input THS6x _ Output 27 Ω Figure 2. Noninverting, Unity Gain Schematic 2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
APPLICATION INFORMATION driving a capacitive load Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS6x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than pf, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 25. A minimum value of 2 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. 5 Ω Input 5 Ω _ THS6x 2 Ω CLOAD Output Figure 25. Driving a Capacitive Load circuit layout considerations In order to achieve the levels of high frequency performance of the THS6x, it is essential that proper printed-circuit board high frequency design techniques be followed. A general set of guidelines is given below. In addition, a THS6x evaluation board is available to use as a guide for layout or for evaluating the device performance. Ground planes It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. Proper power supply decoupling Use a 6.8-µF tantalum capacitor in parallel with a.-µf ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a.-µf ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the.-µf capacitor should be placed as close as possible to the supply terminal. As this distances increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than. inches between the device power terminals and the ceramic capacitors. Sockets Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. Short trace runs/compact part placements Optimum high frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. POST OFFICE BOX 65533 DALLAS, TEXAS 75265 3
APPLICATION INFORMATION circuit layout considerations (continued) Surface-mount passive components Using surface-mount passive components is recommended for high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact, layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. evaluation board An evaluation board is available for the THS6 (literature number SLOP226) and THS62 (literaure number SLOP235). This board has been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the evaluation board is shown in Figure 26. The circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration. To order the evaluation board contact your local TI sales office or distributor. For more detailed information, refer to the THS6 EVM User s Manual (literature number SLOU38) or the THS62 EVM User s Manual (literature number SLOU) VCC C3. µf C2 6.8 µf R kω NULL IN R3 9.9 Ω THS6 _ R5 9.9 Ω OUT NULL R2 kω C. µf C 6.8 µf IN R 9.9 Ω VCC Figure 26. THS6 Evaluation Board Schematic POST OFFICE BOX 65533 DALLAS, TEXAS 75265
D (R-PDSO-G**) PIN SHOWN MECHANICAL INFORMATION PLASTIC SMALL-OUTLINE PACKAGE.5 (,27).2 (,5). (,35) 8. (,25) M PINS ** DIM A MAX A MIN 8.97 (5,).89 (,8).3 (8,75).337 (8,55) 6.39 (,).386 (9,8).57 (,).5 (3,8).2 (6,2).228 (5,8).8 (,2) NOM 7 Gage Plane A. (,25) 8. (,2).6 (,) Seating Plane.69 (,75) MAX. (,25). (,). (,) 7/ D /96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed.6 (,5). D. Falls within JEDEC MS-2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 5
DGN (S-PDSO-G8) MECHANICAL INFORMATION PowerPAD PLASTIC SMALL-OUTLINE PACKAGE,38,65,25 M,25 8 5 Thermal Pad (See Note D) 3,5 2,95,98,78,5 NOM Gage Plane,25 3,5 2,95 6,69,,7 MAX,5,5 Seating Plane, 7327/A /98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions include mold flash or protrusions. D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-87 PowerPAD is a trademark of Texas Instruments Incorporated. 6 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 999, Texas Instruments Incorporated