A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors

LETTER IEICE Electronics Express, Vol.14, No.2, 1 12 A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors Tongxi Wang a), Min-Woong Seo b), Keita Yasutomi c), and Shoji Kawahito d) Research Institute of Electronics, Shizuoka University, 3 5 1 Johoku, Nakaku, Hamamatsu, Shizuoka 432 8011, Japan a) wang@idl.rie.shizuoka.ac.jp b) mwseo@idl.rie.shizuoka.ac.jp c) kyasu@idl.rie.shizuoka.ac.jp d) kawahito@idl.rie.shizuoka.ac.jp Abstract: A high-resolution column-parallel folding-integration/cyclic cascaded (FICC) ADC with a pre-charging technique for CMOS image sensors is presented in this paper. To achieve high-resolution data conversion with multiple sampling, a pre-charging technique is applied to the sampling circuits of the FICC ADC to reduce the influence of incomplete discharging of historical previous samples. This technique effectively reduces differential nonlinearity of the ADC. The prototype chip with 1504 columns FICC ADC array has been implemented and fabricated in 110 nm CMOS technology. The measured DNL of column-parallel FICC ADC with 128 times multiple sampling is 1/4.73 LSBs in sampling speed of 13 KS/s and 19-bit resolution. Keywords: CMOS image sensors, column-parallel ADCs, folding-integration ADC, cyclic ADC, high-resolution, pre-charge technique Classification: Integrated circuits References [1] S. Yoshihara, et al.: A 1/1.8-inch 6.4 Mpixel 60 frame/s CMOS image sensor with seamless mode change, IEEE J. Solid-State Circuits 41 (2006) 2998 (DOI: 10.1109/JSSC.2006.884868). [2] S. Okura, et al.: A 3.7 M-Pixel 1300-fps CMOS image sensor with 5.0 G-Pixel/s high-speed readout circuit, IEEE J. Solid-State Circuits 50 (2015) 1016 (DOI: 10.1109/JSSC.2014.2387201). [3] S. Matsuo, et al.: 8.9-Megapixel video image sensor with 14-b columnparallel SA-ADC, IEEE Trans. Electron Devices 56 (2009) 2380 (DOI: 10. 1109/TED.2009.2030649). [4] R. Funatsu, et al.: 133 Mpixel 60 fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs, ISSCC Dig. Tech. Papers 1

(2015) 112 (DOI: 10.1109/ISSCC.2015.7062951). [5] J. H. Park, et al.: A high-speed low-noise CMOS image sensor with 13-b column-parallel single-ended cyclic ADCs, IEEE Trans. Electron Devices 56 (2009) 2414 (DOI: 10.1109/TED.2009.2030635). [6] K. Kitamura, et al.: A 33-Megapixel 120-frame-per-second 2.5-Watt CMOS image sensor with column-parallel two-stage cyclic analog-to-digital converters, IEEE Trans. Electron Devices 59 (2012) 3426 (DOI: 10.1109/TED. 2012.2220364). [7] Y. Chae, et al.: A 2.1 M Pixels, 120 Frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture, IEEE J. Solid-State Circuits 46 (2011) 236 (DOI: 10.1109/JSSC.2010.2085910). [8] Y. Oike and A. E. Gamal: CMOS image sensor with per-column ΣΔ ADC and programmable compressed sensing, IEEE J. Solid-State Circuits 48 (2013) 318 (DOI: 10.1109/JSSC.2012.2214851). [9] M. W. Seo, et al.: A low-noise high intrascene dynamic range CMOS image sensor with a 13 to 19 b variable-resolution column-parallel foldingintegration/cyclic ADC, IEEE J. Solid-State Circuits 47 (2012) 272 (DOI: 10.1109/JSSC.2011.2164298). [10] J. Kim, et al.: A 14 b extended counting ADC implemented in a 24 MPixel APS-C CMOS image sensor, ISSCC Dig. Tech. Papers (2012) 390 (DOI: 10. 1109/ISSCC.2012.6177060). [11] F. Tang, et al.: Low-power CMOS image sensor based on column-parallel single-slope/sar quantization scheme, IEEE Trans. Electron Devices 60 (2013) 2561 (DOI: 10.1109/TED.2013.2268207). [12] T. Arai, et al.: A 1.1 µm 33 Mpixel 240 fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters, ISSCC Dig. Tech. Papers (2016) 126 (DOI: 10.1109/ISSCC.2016.7417939). [13] P. Rombouts, et al.: A 13.5-b 1.2-V micropower extended counting A/D converter, IEEE J. Solid-State Circuits 36 (2001) 176 (DOI: 10.1109/ 4.902758). [14] T. Wang, et al.: A digital calibration technique for folding-integration/cyclic cascaded ADCs, IEEE proc. MWSCAS (2015) 41 (DOI: 10.1109/MWSCAS. 2015.7282020). [15] M. W. Seo, et al.: A 0.27e-rms read noise 220-µV/e-conversion gain resetgate-less CMOS image sensor with 0.11-µm CIS process, IEEE Electron Device Lett. 36 (2015) 1344 (DOI: 10.1109/LED.2015.2496359). 1 Introduction CMOS image sensors (CISs) have a capability of high-speed low-noise readout due to integrated column-parallel ADCs. Various architectures of column-parallel ADCs are investigated and implemented for CISs, such as single-slope ADC [1, 2], successive approximation (SA) ADC [3, 4], cyclic ADC [5, 6], delta-sigma ADC [7, 8], folding-integration/cyclic cascaded (FICC) ADC [9, 10] and other hybrid ADCs [11, 12]. As low noise, high resolution and high speed are required simultaneously for CISs in scientific, industrial and medical applications, the FICC ADC with multiple-sampling capability is a superior qualified candidate compared with other architectures of ADCs. However, the multiple sampling of the FICC ADC requires high-speed response of the input sampling circuits in order to make the local linearity to be good enough for avoiding visible noises due to the 2

differential non-linearity (DNL) of the ADC. Since the high-speed response in the sampling circuits leads to the increase of power consumption of the analog circuits in the input stage, particularly, source-follower amplifiers in each pixel, novel techniques are required for a column-parallel ADC with better DNL while not increasing power consumption. In this paper, a FICC ADC architecture for an improved DNL is proposed. A pre-charging technique has been introduced in folding-integration (FI) operation to reduce the incomplete-settling related local non-linearity without increasing power consumption. A small DNL at 19-bit resolution is experimentally confirmed by the proposed FICC ADC integrated at the column of a CIS chip. The rest part of this paper is organized as follows. The principle of the precharging technique is described in section 2. Section 3 introduces the design of the FICC ADC with the pre-charging technique. Measurement results are shown in the section 4. Section 5 delivers conclusion. 2 Principle of the pre-charging technique in the FICC ADC The sampling and charge transfer phases of the conventional folding integration (FI) part of the FICC ADC are shown in Fig. 1 [9, 13]. V RH and V RL are reference voltages of 1-bit digital-to-analog converter (DAC). In the worst case, the sampling capacitor C S is set to V RL firstly by the DAC during the previous charge transfer phase when the previous 1-bit sub-adc output (Dði 1Þ) takes the code of 0 and then it has to be set to V RH when the present input signal takes the largest analog level, i.e., V RH. This case requires the largest settling time and introduces a settling error related to the previous 1-bit ADC code, if the sampling time is not sufficient. This code-dependent error causes the degradation of the local non-linearity (or differential non-linearity (DNL)), and global non-linearity (or integral non-linearity (INL)). In the application of the ADC for CMOS image sensors, the local nonlinearity (DNL) error is more important to be controlled to a small level so that the error does not cause additional noise. To address this issue, the pre-charging technique is proposed and implemented in the FI operation of FICC ADC. The principle of the pre-charging technique is described in Fig. 2. The conventional sampling of the FI operation is equivalent to the circuits shown in Fig. 2(a). The sampling capacitor has to be charged from full scale between V RL and V RH in the worst case, and on the other hand, no charging is required in the sampling capacitor for the best case. This difference causes a code-dependent non-linearity. In the FI operation with pre-charging, the initial voltage of the capacitor C before the input signal sampling is always pre-charged to the middle of the two reference levels, V RM, which is equal to ðv RH þ V RL Þ=2, independent of the previous digital code, as shown in Fig. 2(b). This technique has two advantages compared with the conventional FI operation. One is that the amplitude for charging of the sampling capacitor is halved compared to the worst case of the conventional FI operation, and the other is that the incomplete settling during the input signal sampling is independent of the digital code (1-bit ADC output) of the previous cycle of the FI operation. Therefore, the code-dependent error due to the incomplete settling during the input signal sampling does not occur any more. Furthermore, as 3

(a) (b) Fig. 1. Conventional sampling (a) and charge transfer (b) phases of FI operation. (a) (b) Fig. 2. Equivalent circuits of conventional FI operation (a) and proposed FI operation with pre-charge technique (b). described in the next section, this middle-level voltage is generated with the local switching circuits at the column instead of using additional reference generators and signal lines for pre-charging to V RM, resulting in very small time of precharging, few nanoseconds, which is good enough to keep the time budget of sampling period. 3 Architecture of the FICC ADC with the pre-charging technique Architecture of the FICC ADC with the pre-charging technique is shown in Fig. 3(a), which includes an analog core of switch-capacitor circuits, a 1/1.5-bit reconfigurable sub-adc for the FI/cyclic operation, respectively, logic block, digital counter for the FI operation, and register for the cyclic ADC operation. The m-bit most significant bits (MSBs) are generated from the FI operation after 2 m -times multiple sampling and counting, then n-bit least significant bits (LSBs) are generated from the cascaded cyclic ADC operation by further converting the final analog residue of the FI operation. The final digital code of the FICC ADC 4

(a) (b) Fig. 3. Schematic of proposed FICC ADC (a) and its analog core circuits (b). is (m þ n 1)-bit, where m ¼ 7 and n ¼ 13 in this design, considering the 1-bit redundancy of the FI operation. The detail of analog core circuits is shown in Fig. 3(b). The common levels, V CM D and V CM S are connected together outside of the column array to V CM which is the common level of the entire chip. Switches are implemented with CMOS switches and some of them are together with dummy transistors to reduce the charge injection. To perform half gain during the FI operation, two input capacitors C 1a and C 1b are set to the half of C 2 and C 1a ¼ C 1b ¼ 250 ff. The timing of the FICC ADC operation is illustrated in Fig. 4(a). The time of one conversion (1C) cycle is expressed as T 1C ¼ T FI þ T CYC : where T FI (¼ 68:2 µs) is the time for multiple sampling of the FI operation that also determines the sampling speed of the FICC ADC together with T CYC ¼ 8:8 µs, which yield a sampling speed of the FICC ADC of 13 KS/s. The behaviors of the FI operation with the pre-charging technique are shown in Fig. 4(b g). In the initial sampling phase, the first input signal, V INð0Þ, is sampled by the capacitor C 1a. Since the DAC takes V RL in the first two cycles of the FI operation, the capacitor C 1b samples V RH in phases of (b) and (c), independent of the 1-bit sub-adc code. Then both terminals of C 1a and C 1b are shorted together by switches of P SS and P 1 to perform the pre-charging within 10 ns and to generate V RM in phase (d). The charging for the second sampling of C 1a is starting from middle-level voltage, V RM, instead of V RH or V RL after the pre-charging in phase (e), which results in the acceleration of the sampling speed by half in the worst case. The voltage of top side (physically bottom plate side) of C 1b remains V RM before ð1þ 5

(a) (b) (c) (d) (e) (f) (g) Fig. 4. Timing of operation of FICC ADC (a) and its behaviors of FI operation with integrated pre-charge technique: initial sampling phase (b), the first charge-transfer phase (c), pre-charge phase (d), the second sampling phase (e), # of i-th charge transfer in case of D(i 1) = 0 (f ), and # of i-th charge-transfer in case of D(i 1) = 1 (g). setting to an updated value by the DAC. The operations of the charge transfer phase for the i-th cycle is shown in Fig. 4(f) and (g) for the cases of D(i 1) = 0 and D(i 1) = 1, respectively. To eliminate the code-dependent error due to the charge of the previous cycle, C 1b is pre-charged to V RH in the case of D(i 1) = 0 and V RL in the case of D(i 1) = 1. In the phase of Fig. 4(d) during ði þ 1Þ-th cycle, both terminals of C 1a and C 1b are shorted together again before the signal sampling phase, and the input sampling capacitor C 1a is surely pre-charged to V RM one more time, independent of starting from either phases of Fig. 4(f) or (g). In the following FI operations with the pre-charging, the cycle of Fig. 4(e), Fig. 4(f )/(g), 6

(a) (b) Fig. 5. Circuit schematic of the OTA (a), the comparator (b) for FICC ADC. and Fig. 4(d) is repeated by the next (2 m 2) times to perform the multiplesampling of FI operation for the FICC ADC. A single-stage telescopic OTA is employed in this design for the FICC ADC as shown in Fig. 5(a). To reduce the bias-voltage variation across large column array, the OTA is biased in local column except the one for a current source, V BN. The current consumption of the OTA is 52.6 µa. According to simulation results under 3.3 V analog power supply in the typical corner with 27 C, the OTA has the openloop DC gain of 78.7 db, unit-gain bandwidth (UGB) of 143 MHz with a 0.25 pf load capacitor, and phase margin of 52.9 degree. The OTA also has 1.4 V (0.9 V 2.3 V) output swing with the large DC gain of over 78 db. The comparator circuits are shown in Fig. 5(b). The static bias current for the first stage preamplifier is 1 µa. The sampling in the comparator is controlled by P CMPR.A regeneration strong-arm latch is followed as the second stage. 4 Simulation and measurement results The effectiveness of the proposed pre-charging technique for the 19-bit FICC ADC is verified by behavioral-level simulation firstly. The detail introduction of the model of the FICC ADC is described in [14]. The additional incomplete settling error and historical code dependent model, the principle of which has been described in previous section 2, have been added into the model of the FICC ADC to evaluate and simulate the effectiveness of the pre-charging technique. To observe the advantage of the pre-charging technique in simulation, a 0.1% of 7

(a) (b) Fig. 6. The simulated DNL results of 19-bit FICC ADC: (a) without pre-charging technique and (b) with pre-charging technique. Fig. 7. The photograph of prototype chip with 1504 columns ADC array. settling error is applied for calculation with pre-charging and without pre-charging technique. The simulated DNL results of 19-bit FICC ADC with and without precharging technique are shown in Fig. 6. The simulated DNL of the ADC without 8

pre-charging technique is 0:5=4:5 LSBs in 19-bit resolution as shown in Fig. 6(a). However, the simulated DNL of the 19-bit FICC ADC is reduced to 0:5=1:5 LSBs after applying the pre-charging technique as shown in Fig. 6(b). The simulation results show that the pre-charging technique is able to improve the local nonlinearity (DNL) of the FICC ADC by suppressing the memory effect from historical code dependency during high-speed operation with an incomplete settling error. In order to demonstrate the proposed FICC ADC, a prototype chip with 1504 column ADCs is implemented and fabricated in 110 nm CMOS technology as shown in Fig. 7. The column pitch is 5.6 µm for the FICC ADC. The area of the entire FICC ADC array is 2000 m 8600 m. The analog circuits are powersupplied with 3.3 V. The digital parts are power-supplied with 1.5 V. The static power consumption of the FICC ADC per column is 173.6 µw. The entire FICC ADC array consumes 261 mw of static power in total. The control circuits of the FICC ADCs are globally distributed to each column ADC by digital buffers in the left side of array. Reference voltages of V CM, V RH and V RL are supplied from both left and right sides which are generated from off-chip circuits, where V CM ¼ V RH ¼ 2:0 V, and V RL ¼ 1:0 V in this measurement. Threshold voltages of sub- ADC for FI and cyclic operation are generated on-chip by resistor ladders which are also located in the left side of column circuits array. The evaluation of the linearity of the FICC ADC is based on the data from image sensor operation controlled by vertical and horizontal scanners since the ADC array is designed for CMOS image sensors. The testing ramp signal generated from function generator is connected to the common testing input node of the ADC array that connects all of testing inputs of each column-parallel FICC ADC together. The output data of the FICC ADC array is in the format of frame as working for images. The data of one row in one frame is the same sampled and converted digital results for one conversion from 1504 columns of the FICC ADC array. The calculation of the linearity of the specific number of column ADC has to be chosen among 1504 column matrix data. In order to capture large enough data amount to calculate the linearity of 19-bit FICC ADC, a large number of frame data has to be acquired during measurement. The measured linearity results including differential non-linearity (DNL) and integral non-linearity (INL) of the column FICC ADC are shown in Fig. 8. The analog range of the FICC ADC is limited to 0.955 V due to the offsets of the OTA and comparator, while V RH V RL ¼ 1:0 V. This range corresponds to 95.5% of the digital code from 0 to 501,050 in 19 bits. It shows that the FICC ADC with precharging technique has a DNL within 1=4:73 LSBs under 13 KS/s sampling speed and 19-bit resolution with multiple sampling of 128 times resulting in 7-bit MSBs from the FI operation and 13-bit LSBs from the cyclic operation. The INL of the FICC ADC with 19-bit resolution is very large, which is 430=11;020 LSBs. The maximum INL of 11,020 LSBs corresponds to 2.1% of the full scale code (¼ 524;288). The large DNL error in the middle region is caused by the error of the comparator for 1-bit quantizer in FI ADC with 128 times of sampling and integration since the outputs of comparators in all of columns are frequently changed in the middle region. This frequent change introduces errors in the 9

Fig. 8. Measured linearity results of 19-bit FICC ADC with precharging technique. Fig. 9. Measured linearity results of 19-bit FICC ADC between digital code of 9000 211,600. comparator and integrator due to large switching noise from digital circuits and large sampling noise from reference voltages for DACs. In order to further examine the effectiveness of the proposed technique, the DNL and INL of the first 38.6% of ADC full scale [9000 2:116 10 5 ] are plotted as shown in Fig. 9, the maximum DNL and INL are less than 1=2:32 LSBs and 1200=196 LSBs, respectively. The maximum DNL of 2.32 LSBs corresponds to less than 4.4 µv as an analog bin. According to the typical conversion gain of 67 µv/e- for the case of a low-noise wide dynamic range image sensor [9], the error due to the ADC nonlinearity is less than 0.066e-. If the pixel has higher conversion gain like in [15], that is 220 µv/e-, the corresponding error due to the ADC nonlinearity can be less than 0.02e-. The maximum INL of 1,200 LSBs corresponds to 0.57% of the 38.6% of 19-bit full scale code (¼ 211;600). This global non-linearity is acceptable for the application for CMOS image sensors. Though the relatively large errors in the middle region of the ADC 10

Fig. 10. Measured column FPN in 1504 columns 19-bit FICC ADC array. code is left as a future subject to be solved, the very small DNL and acceptable INL have been demonstrated to verify the effectiveness of the FICC ADC with the precharging technique for the application of low noise, high sensitivity, and wide dynamic range CMOS image sensors. The performance of the column parallel FICC ADC with the pre-charging technique is summarized in the Table I. Since this ADC array is designed for applications of CMOS image sensors, the uniformity of the offset as the ADC array is also an important issue. The measured column fixed pattern noise (FPN) within 1504 columns of the 19-bit FICC ADC array is shown in Fig. 10. The peak-to-peak column FPN is less than 150 LSBs with 19-bit FICC ADC which is equal to 0.0286% of overall variation. Table I. Performance of the FICC ADC CMOS Technology 110 nm CMOS Technology Supply Voltage 3.3 V (Analog), 1.5 V (Digital) Size of ADC Array 1504 Columns Size of One Column ADC 2000 m 5:6 m Power Consumption of One Column ADC 173.6 µw Power Consumption of ADC Array 261 mw Sampling Speed of One Column ADC 13 KS/s Sampling Time of One Conversion 128 Resolution of FI ADC 7 bit Resolution of Cyclic ADC 13 bit Resolution of FICC ADC 19 bit Time of FI Operation (T FI ) 68.2µs Time of Cyclic Operation (T CYC ) 8.8µs Dynamic Range of FICC ADC 1.0 V 1.955 V (114 db) DNL of FICC ADC (19-bit) 1=4:73 LSBs Overall Column FPN of ADC Array (19-bit) 0.0286% (p-p) 11

5 Conclusion A 19-bit column-parallel FICC ADC with a pre-charging technique for CMOS image sensors has been introduced in this paper. A prototype chip with 1504- column FICC ADC array has been fabricated in 110 nm CMOS technology. The performance of the FICC ADC used in the image sensor has been tested and evaluated. The measured results show that the FICC ADC has the DNL of less than 1=4:73 LSBs with the dynamic range of 0.955 V thanks to the proposed precharging technique that enhance the FICC ADC operation to achieve expected local linearity. The measured overall peak-to-peak column FPN of 1504-column 19-bit FICC ADC array is 0.0286%. Acknowledgments This paper was supported in part by the Grant-in-Aid for Scientific Research (S) under Grant 25220905 through the Ministry of Education, Culture, Sports, Science and Technology (MEXT), in part by the MEXT/JST COI-STREAM program, and in part by JST A-STEP program. The authors would like to thank M. Fukuda and T. Takasawa for their support during the measurement setup. This work was supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc. and Mentor Graphics, Inc. 12