Introduction to CMC 3D Test Chip Project Robert Mallard CMC Microsystems Apr 20, 2011 1
Overview of today s presentation Introduction to the project objectives CMC Why 3D chip stacking? The key to More than Moore? Test challenges for 3D chip stacking Project approach Chip design Test approach 2
Instructions for participants The webinar video is running in ilinc Use the chat function at the bottom left corner of your browser window, if you d like to submit a written comment/question The audio is running on a Bell teleconference line 866 440 8937 passcode 7169046 The webinar moderator will mute the microphones of all participants during the participation (##) If you d like to interject, raise a question at any time during the webinar, hit *6 and then speak. *6 will re-mute your line 3
Scope of CMC 3D Test Chip Project Develop a reference design mixed signal microelectronic test chip based on a 3D chip stacking architecture/ process: demonstrating the application of a DFT methodology Lowering the barriers to DFT adoption CMC to host regular webinars on 3D, DFT and related topics 3D design and test issues Presentations from leading industrial and academic experts in 3D design and test 4
Objectives of the webinar Introduce CMC 3D Test Project and webinar series Increase awareness among Canadian academic researchers of issues related to 3D integration and test Increase adoption of CMC 3Drelated integration products and services Give CMC subscribers an opportunity to participate more fully in the development of 3D integration tools, including test resources 5
3D Chip Stacking CMC is partnering with Tezzaron, MOSIS and CMP to run a pilot project for Canadian academic research access to a 3D chip stacking process July design submissions CMC and 3 Canadian universities are participating May be a combination of digital, analog logic and memory Through Silicon Via (TSV) 6
3D Chip Stacks: Test issues Is the interconnect reliable? There may be thousands of TSVs <100% manufacturing yield Where is the test point access? Is primary I/O sufficient? How can you test, de-bug and isolate faults? How does your automatic CAD environment cope with functional partitioning between chips Through Silicon Via (TSV) 7
Test access challenges Mature methods that allow test access to complex digital circuits exist: JTAG Significant adoption in industry for production testing Emergence of related methods for analog and memory testing 1149.4 BIST Testing TSV-Based 3D Stacked ICs, Erik Jan Marinissen, IMEC, 3DIC 10 How can CMC help lower the barriers that Canadian researchers who want to test their 3D structures face? 8
Overview of today s presentation Introduction to the project objectives CMC Why 3D chip stacking? The key to More than Moore? Test challenges for 3D chip stacking Project approach Chip design Test approach 9
About CMC Headquartered in Kingston, Ontario, Canada A private not-for-profit corporation since 1984 involving academia, industry and government 17 other national and/or international members 26 industry members 45 universities and 1 college 10
Canada s University-based National Design Network 11
National Design Network >45 Universities 800 researchers initially 1200 by 2015 Integration of electronic, photonic, mechanical and fluidic technologies Multi-disciplinary collaborations Enriched training environment Create a path to commercialization 12
What Does CMC Microsystems Do? Design Make Test Delivers to researchers: Tools and technologies (infrastructure) to investigate microsystems and put them to work Stimulates: Microsystems R&D and technology diffusion 13
Overview of today s presentation Introduction to the project objectives CMC Why 3D chip stacking? The key to More than Moore? Test challenges for 3D chip stacking Project approach Chip design Test approach 14
Why 3D? 15
Why 3D? since 2001, we have reached the point where the horizon of the Roadmap challenges the most optimistic projections for continued scaling of CMOS (for example, MOSFET channel lengths below 9 nm). It is also difficult for most people in the semiconductor industry to imagine how we could continue to afford the historic trends of increase in process equipment and factory costs for another 15 years! Thus, the ITRS must address post- CMOS devices. ITRS Roadmap, 2009 3D-IC is generating a huge amount of interest and exploration because it offers an alternative to traditional scaling for achieving advances in performance, reduced power consumption, cost reduction, and increased functionality in a small package Walden C. Rhines, CEO and chairman of Mentor Graphics 16
Drivers for 3D Anticipation of brick wall for Moore s law, as CMOS dimension shrink <22nm and beyond Performance advantages Reduced parasitics, increased speed, lower transmission power loss due to reduced length of interconnect Opportunity for heterogeneous integration Dissimilar Si processes, other materials MEMS, microfluidics, photonics, other technologies Form factor Especially for packing in fast access to lots of memory 17
Example of 3D Integration Project 18
Overview of today s presentation Introduction to the project objectives CMC Why 3D chip stacking? The key to More than Moore? Test challenges for 3D chip stacking Project approach Chip design Test approach 19
3D test requirements definition What do we want to test? Production pass / fail, yield analysis, product development, design verification, device characterization? Does primary I/O characterization suffice? Might be OK as long as nothing goes wrong, but if it does, then what? What is different about 3D test? Uncertainty over TSV integrity. May not be able to assume good quality interconnect Opportunity to test individual bare die is limited Can one test the actual die that will be used in the final assembly? Are they available to the researcher? what are known good die anyway PGD? Test point access for assembled system. How will the assembled structure be de-bugged? Test vector insertion can your CAD tools handle a 3D stack? What about ATPG? Does it target die-to-die interconnect? 20
CMC 3D test project objectives Adoption of 3D architectures and designs places greater stress on the need to address test access in a rigorous way, and to develop methods that allow for device characterization and de-bug in the face of limited test access Deliver tools to NDN researchers that lower the barriers they face to access and adopt DFT technologies 21
Test Plan Scope Design and fabricate a 3D test chip that invokes a Design For Test (DFT) methodology, enabling: test access interconnect test functional characterization debugging capabilities for a representative mixed signal system This will address: Relevance to industrial design practice in an automated CAD environment Adoption of a design for test mindset in a typical 3D design flow Mixed signal and memory test 22
Overview of today s presentation Introduction to the project objectives CMC Why 3D chip stacking? The key to More than Moore? Test challenges for 3D chip stacking Project approach Chip design Test approach 23
CMC 3D test project deliverables Delivery of tools that will enable CMC clients to adopt and adapt the DFT approach and physically test their chip Design and fabricate the test chip Publication of reference design for the testable chip Publication of associated design flow / test plan Application notes Provision of relevant test hardware and test chip reference design through the CMC test equipment lending pool 24
CMC 3D test project approach What sort of test methods will be addressed? Hierarchical test approach: Includes design for test methodologies relevant to 2D and 3D integrated microelectronic chips JTAG, boundary scan, 1149.1 Analog test elements connected to AT ports supported by 1149.4 Where possible, automated CAD tool use for insertion of boundary scan, test logic and test pattern generation At-speed testing through on-board dedicated test logic Primary I/O The test plan scope is limited at this time to JTAG 1149.1 and 1149.4 (digital, analog) standards. A full mixed signal system DFT implementation would also involve the use of Built-In Self Test, p1500 (embedded core test), and p1687 (ijtag). 25
CMC test chip Boundary scan (JTAG 1149.x) allows you to actively manage on-board logic elements to test internal chip functionality 26
CMC test chip Keep it simple!!! Emphasis is on demonstrating feasibility on a simple structure Chip function not critical Representative of a more complex circuit in terms of design flow, test implementation Can extrapolate concepts and methodologies to more complex chips Functional design of chip consists of simple phase shifter Employing digital, analog and memory circuitry 27
Test Chip Functional Specification The device receives an input sine wave and under user control, directs either the input waveform shifted by ½ a clock cycle or input shifted by 10 clock cycles to the device output. Specs include: 3 bit flash ADC Digitized data stream presented to shift register (S/R) as well as RAM block Mux selects either S/R or RAM based data stream to present to D/A Memory control unit controls all chip functionality Test circuitry included in design but not shown on diagram 28
CMC test chip test point insertion Project status: High level chip functions defined, partitioned between layers Present focus is on defining boundary scan insertion points using 1149.4 Next steps: HDL Code Development and implementing Analog Blocks 29
For more information Next webinar: May 9, 2011, at 12:30 PM EDT: Introduction to JTAG-based testing for 3D integrated systems, Heiko Ehrenberg, Goepel Electronics www.goepel.com/ CMC subscribers may wish to more actively participate in the test chip development project Weekly meetings, Tuesdays at 12:30 Contact Rob Mallard: mallard@cmc.ca 30
Stay in touch with the project For regular updates on upcoming webinars in this series: http://www.cmc.ca/en/newsandevents/events/3dic_webinarseries.aspx Questions and comments? Contact Rob Mallard at mallard@cmc.ca 31
For more information 32
For more information First fab run has a July 1 design submission deadline Second run planned for December 2011 33
CMC 3D Test Team Special thanks to: Hudson An Hsu Ho Feng Liu Jeetendar Narsinghani Jim Quinn Bob Stevenson Thanks for your attention 34