NV2402WF, NV2404WF, NV2408WF, NV2416WF 2 kb, 4 kb, 8 kb and 16 kb I 2 utomotive erial EEROM in Wettable Flank UDFN-8 ackage Description he NV2402/04/08/16 are 2 kb, 4 kb, 8 kb and 16 kb respectively MO erial EEROM devices organized internally as 16/32/64 and 128 pages respectively of 16 bytes each. ll devices support the tandard (100 khz) and Fast (400 khz) I 2 protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a age Write Buffer, and then writing all data to non volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. External address pins make it possible to address up to eight NV2402, four NV2404, two NV2408 and one NV2416 device on the same bus. Features utomotive Grade 1 emperature Range ( 40 to +125 ) upports tandard, Fast and Fast lus I 2 rotocol 2.5 V to 5.5 V upply Voltage Range 16 Byte age Write Buffer Fast Write ime (4 ms max) Hardware Write rotection for Entire Memory chmitt riggers and Noise uppression Filters on I 2 Bus Inputs (L and D) Low power MO echnology More than 1,000,000 rogram/erase ycles 100 Year Data Retention UDFN 8 (2 x 3 mm) Wettable Flank ackage ( 40 to +125 ) hese Devices are b Free, Halogen Free/BFR Free and are RoH ompliant 1 UDFN 8 MUW3 UFFIX E 517DH MRING DIGRM 1 XXXXX WLYW XXXXX = pecific Device ode = ssembly Location WL = Wafer Lot Y = Year W = Work Week = b Free ackage ORDERING INFORMION ee detailed ordering, marking and shipping information on page 9 of this data sheet. IN ONFIGURION NV24 16 / 08 / 04 / 02 N / N / N / 0 1 N / N / 1 / 1 N / 2 / 2 / 2 V V W L D UDFN 8 (op View) emiconductor omponents Industries, LL, 2017 November, 2017 Rev. 1 1 ublication Order Number: NV2402WF/D
NV2402WF, NV2404WF, NV2408WF, NV2416WF V able 1. IN FUNION in Name Function L 0, 1, 2 Device ddress Input D erial Data Input/Output 2, 1, 0 NV24xx D L W erial lock Input Write rotect Input W V ower upply V Ground N No onnect V Figure 1. Functional ymbol able 2. BOLUE MXIMUM RING arameters Ratings Unit torage emperature 65 to +150 Voltage on any pin with respect to Ground (Note 1) 0.5 to +6.5 V tresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. During input transitions, voltage undershoot on any pin should not exceed 1 V for more than 20 ns. Voltage overshoot on pins 0, 1, 2 and W should not exceed V + 1 V for more than 20 ns, while voltage on the I 2 bus pins, L and D, should not exceed the absolute maximum ratings, irrespective of V. able 3. RELIBILIY HRERII ymbol arameter Min Unit N END (Note 2) Endurance 1,000,000 Write ycles (Note 3) DR (Note 2) Data Retention 100 Years 2. = 25 3. Write ycle refers to writing a Byte or a age. able 4. D OERING HRERII (V = 2.5 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol arameter est onditions Min Max Unit I R Read urrent Read 0.3 m 2 m I L I/O in Leakage in at GND or V 2 V IL1 Input Low Voltage 0.5 0.3 V V V IH1 Input High Voltage 0.7 V V + 0.5 V V OL1 Output Low Voltage I OL = 6.0 m 0.4 V roduct parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. roduct performance may not be indicated by the Electrical haracteristics if operated under different conditions. 2
NV2402WF, NV2404WF, NV2408WF, NV2416WF able 5. IN IMEDNE HRERII (V = 2.5 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol arameter onditions Max Unit IN (Note 4) D I/O in apacitance V IN = 0 V 8 pf IN (Note 4) Input apacitance (other pins) V IN = 0 V 6 pf I W, I (Note 5) W Input urrent, ddress Input urrent (0, 1, 2) V IN < V IH, V = 5.5 V 50 V IN < V IH, V = 3.3 V 35 V IN < V IH, V = 2.5 V 25 V IN > V IH 2 4. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 5. When not driven, the W, 0, 1 and 2 pins are pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong; therefore the external driver must be able to supply the pull down current when attempting to drive the input HIGH. o conserve power, as the input level exceeds the trip point of the MO input buffer (~ 0.5 x V ), the strong pull down reverts to a weak current source. able 6. HRERII (V = 2.5 V to 5.5 V, = 40 to +125, unless otherwise specified.) (Note 6) ymbol arameter tandard Fast Min Max Min Max F L lock Frequency 100 400 khz t HD: R ondition Hold ime 4 0.6 s t LOW Low eriod of L lock 4.7 1.3 s t HIGH High eriod of L lock 4 0.6 s t U: R ondition etup ime 4.7 0.6 s t HD:D Data In Hold ime 0 0 s t U:D Data In etup ime 250 100 ns t R (Note 7) D and L Rise ime 1,000 300 ns t F (Note 7) D and L Fall ime 300 300 ns t U:O O ondition etup ime 4 0.6 s t BUF Bus Free ime Between O and R 4.7 1.3 s t L Low to Data Out Valid 3.5 0.9 s t DH (Note 7) Data Out Hold ime 100 100 ns i (Note 7) Noise ulse Filtered at L and D Inputs 50 50 ns t U:W W etup ime 0 0 s t HD:W W Hold ime 2.5 2.5 s t WR Write ycle ime 4 4 ms t U (Notes 7, 8) ower-up to Ready Mode 0.35 0.35 ms 6. est conditions according to.. est onditions table. 7. ested initially and after a design or process change that affects this parameter. 8. t U is the delay between the time V is stable and the device is ready to accept commands. Unit able 7. E ONDIION Input Levels Input Rise and Fall imes Input Reference Levels Output Reference Levels Output Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.3 x V, 0.7 x V urrent ource: I OL = 6 m (V 2.2 V); I OL = 2 m (V < 2.2 V); L = 100 pf 3
NV2402WF, NV2404WF, NV2408WF, NV2416WF ower On Reset (OR) Each NV24xx* incorporates ower On Reset (OR) circuitry which protects the internal logic against powering up in the wrong state. NV24xx device will power up into tandby mode after V exceeds the OR trigger level and will power down into Reset mode when V drops below the OR trigger level. his bi directional OR feature protects the device against brown out failure following a temporary loss of power. *For common features, the NV2402/04/08/16 will be referred to as NV24xx. in Description L: he erial lock input pin accepts the erial lock generated by the Master. D: he erial Data I/O pin receives input data and transmits data stored in EEROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of L. 0, 1 and 2: he ddress inputs set the device address when cascading multiple devices. When not driven, these pins are pulled LOW internally. W: he Write rotect input pin inhibits all write operations, when pulled HIGH. When not driven, this pin is pulled LOW internally. Functional Description he NV24xx supports the Inter Integrated ircuit (I 2 ) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all R and O conditions. he NV24xx acts as a lave device. Master and lave alternate as either transmitter or receiver. I 2 Bus rotocol he I 2 bus consists of two wires, L and D. he two wires are connected to the V supply via pull up resistors. Master and lave devices connect to the 2 wire bus via their respective L and D pins. he transmitting device pulls down the D line to transmit a 0 and releases it to transmit a 1. Data transfer may be initiated only when the bus is not busy (see haracteristics). During data transfer, the D line must remain stable while the L line is high. n D transition while L is high will be interpreted as a R or O condition (Figure 2). he R condition precedes all commands. It consists of a HIGH to LOW transition on D while L is HIGH. he R acts as a wake up call to all receivers. bsent a R, a lave will not respond to commands. he O condition completes all commands. It consists of a LOW to HIGH transition on D while L is HIGH. NOE: he I/O pins of NV24xx do not obstruct the L and D lines if the V supply is switched off. During power up, the L and D pins (connected with pull up resistors to V) will follow the V monotonically from V (0 V) to nominal V value, regardless of pull up resistor value. he delta between the V and the instantaneous voltage levels during power ramping will be determined by the relation between bus time constant (determined by pull up resistance and bus capacitance) and actual V ramp rate. Device ddressing he Master initiates data transfer by creating a R condition on the bus. he Master then broadcasts an 8 bit serial lave address. For normal Read/Write operations, the first 4 bits of the lave address are fixed at 1010 (h). he next 3 bits are used as programmable address bits when cascading multiple devices and/or as internal address bits. he last bit of the slave address, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. he 3 address space extension bits are assigned as illustrated in Figure 3. 2, 1 and 0 must match the state of the external address pins, and a 10, a 9 and a 8 are internal address bits. cknowledge fter processing the lave address, the lave responds with an acknowledge () by pulling down the D line during the 9th clock cycle (Figure 4). he lave will also acknowledge the address byte and every data byte presented in Write mode. In Read mode the lave shifts out a data byte, and then releases the D line during the 9 th clock cycle. s long as the Master acknowledges the data, the lave will continue transmitting. he Master terminates the session by not acknowledging the last data byte (No) and by issuing a O condition. Bus timing is illustrated in Figure 5. 4
NV2402WF, NV2404WF, NV2408WF, NV2416WF L D R ONDIION O ONDIION Figure 2. tart/top iming 1 0 1 0 2 1 0 R/W NV2402 1 0 1 0 2 1 a 8 R/W NV2404 1 0 1 0 2 a 9 a 8 R/W NV2408 1 0 1 0 a 10 a 9 a 8 R/W NV2416 Figure 3. lave ddress Bits L FROM MER BU RELEE DELY (RNMIER) 1 8 9 BU RELEE DELY (REEIVER) D OUU FROM RNMIER D OUU FROM REEIVER R DELY ( t ) Figure 4. cknowledge iming EU ( t U:D ) t F t HIGH t R tlow tlow L t U: t HD: t HD:D t U:D t U:O D IN t t DH t BUF D OU Figure 5. Bus iming 5
NV2402WF, NV2404WF, NV2408WF, NV2416WF WRIE OERION Byte Write In Byte Write mode, the Master sends the R condition and the lave address with the R/W bit set to zero to the lave. fter the lave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the NV24xx. fter receiving another acknowledge from the lave, the Master transmits the data byte to be written into the addressed memory location. he NV24xx device will acknowledge the data byte and the Master generates the O condition, at which time the device begins its internal Write cycle to nonvolatile memory (Figure 6). While this internal cycle is in progress (t WR ), the D output will be tri stated and the NV24xx will not respond to any request from the Master device (Figure 7). age Write he NV24xx writes up to 16 bytes of data in a single write cycle, using the age Write operation (Figure 8). he age Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the data byte is transmitted, the Master is allowed to send up to fifteen additional bytes. fter each byte has been transmitted the NV24xx will respond with an acknowledge and internally increments the four low order address bits. he high order bits that define the page address remain unchanged. If the Master transmits more than sixteen bytes prior to sending the O condition, the address counter wraps around to the beginning of page and previously transmitted data will be overwritten. Once all sixteen bytes are received and the O condition has been sent by the Master, the internal Write cycle begins. t this point all received data is written to the NV24xx in a single write cycle. cknowledge olling he acknowledge () polling routine can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host s write operation, the NV24xx initiates the internal write cycle. he polling can be initiated immediately. his involves issuing the start condition followed by the slave address for a write operation. If the NV24xx is still busy with the write operation, No will be returned. If the NV24xx has completed the internal write operation, an will be returned and the host can then proceed with the next read or write operation. Hardware Write rotection With the W pin held HIGH, the entire memory is protected against Write operations. If the W pin is left floating or is grounded, it has no impact on the operation of the NV24xx. he state of the W pin is strobed on the last falling edge of L immediately preceding the first data byte (Figure 9). If the W pin is HIGH during the strobe interval, the NV24xx will not acknowledge the data byte and the Write request will be rejected. Delivery tate he NV24xx is shipped erased, i.e., all bytes are FFh. BU IVIY: MER R LVE DDRE DDRE D a 7 a 0 d 7 d 0 O LVE Figure 6. Byte Write equence 6
NV2402WF, NV2404WF, NV2408WF, NV2416WF L D 8th Bit Byte n t WR O ONDIION Figure 7. Write ycle iming R ONDIION DDRE BU IVIY: MER R LVE DDRE DDRE D D D n n+1 n+ O LVE n = 1 15 Figure 8. age Write equence DDRE D 1 8 9 1 8 L D a 7 a 0 d 7 d 0 t U:W W t HD:W Figure 9. W iming 7
NV2402WF, NV2404WF, NV2408WF, NV2416WF Immediate Read Upon receiving a lave address with the R/W bit set to 1, the NV24xx will interpret this as a request for data residing at the current byte address in memory. he NV24xx will acknowledge the lave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (No) and then follows up with a O condition (Figure 10), the NV24xx returns to tandby mode. elective Read elective Read operations allow the Master device to select at random any memory location for a read operation. he Master device first performs a dummy write operation by sending the R condition, slave address and byte RED OERION address of the location it wishes to read. fter the NV24xx acknowledges the byte address, the Master device resends the R condition and the slave address, this time with the R/W bit set to one. he NV24xx then responds with its acknowledge and sends the requested data byte. he Master device does not acknowledge the data (No) but will generate a O condition (Figure 11). equential Read If during a Read session, the Master acknowledges the 1 st data byte, then the NV24xx will continue transmitting data residing at subsequent locations until the Master responds with a No, followed by a O (Figure 12). In contrast to age Write, during equential Read the address count will automatically increment to and then wrap around at end of memory (rather than end of page). BU IVIY: N O MER R LVE DDRE O LVE D L 8 9 D 8th Bit D OU NO Figure 10. Immediate Read equence and iming O BU IVIY: MER R LVE DDRE DDRE R LVE DDRE N O O BU IVIY: LVE Figure 11. elective Read equence D N O MER LVE DDRE O LVE D n D n+1 D n+2 D n+x Figure 12. equential Read equence 8
ORDERING INFORMION NV2402WF, NV2404WF, NV2408WF, NV2416WF NV2402WF Ordering Information (roduct in Development) Device Order Number NV2402MUW3VBG (Note 10) pecific Device Marking ackage ype emperature Range hipping BD NV2404WF Ordering Information Device Order Number MUW3 = UDFN 8 (2x3 mm) Wettable Flank V = utomotive Grade 1 ( 40 to +125 ) = ape & Reel, 3,000 Units / Reel pecific Device Marking ackage ype emperature Range hipping NV2404MUW3VBG 2W MUW3 = UDFN 8 (2x3 mm) Wettable Flank NV2408WF Ordering Information Device Order Number V = utomotive Grade 1 ( 40 to +125 ) = ape & Reel, 3,000 Units / Reel pecific Device Marking ackage ype emperature Range hipping NV2408MUW3VBG 3W MUW3 = UDFN 8 (2x3 mm) Wettable Flank NV2416WF Ordering Information Device Order Number V = utomotive Grade 1 ( 40 to +125 ) = ape & Reel, 3,000 Units / Reel pecific Device Marking ackage ype emperature Range hipping NV2416MUW3VBG 4W MUW3 = UDFN 8 (2x3 mm) Wettable Flank V = utomotive Grade 1 ( 40 to +125 ) = ape & Reel, 3,000 Units / Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel ackaging pecifications Brochure, BRD8011/D. 9. ll packages are RoH compliant (b Free, Halogen free). 10. roduct in development 9
NV2402WF, NV2404WF, NV2408WF, NV2416WF GE DIMENION UDFN8 2x3, 0.5 E 517DH IUE O IN ONE INDIOR NOE 4 0.05 0.10 0.08 0.05 D ÇÇ ÇÇ ÇÇ O VIEW DEIL B 1 IDE VIEW B E 3 L1 EXOED u EING LNE L DEIL LERNE ONRUION ÉÉ MOLD MD DEIL B LERNE ONRUION L ÉÉÉ 1 3 NOE: 1. DIMENIONING ND OLERNING ER ME Y14.5M, 1994. 2. ONROLLING DIMENION: MILLIMEER. 3. DIMENION b LIE O LED ERMINL ND I MEURED BEWEEN 0.15 ND 0.25MM FROM HE ERMINL I. 4. OLNRIY LIE O HE EXOED D WELL HE ERMINL. 5. FOR DEVIE ON ONINING W OION, DEIL B LERNE ONRUION I NO LIBLE. MILLIMEER DIM MIN MX 0.45 0.55 1 0.00 0.05 3 0.13 REF b 0.20 0.30 D 2.00 B D2 1.30 1.50 E 3.00 B E2 1.30 1.50 e 0.50 B L 0.30 0.50 L1 0.15 DEIL D2 1 4 L REOMMENDED OLDERING FOORIN* 1.56 E2 8X 0.68 1.55 3.40 8 5 e BOOM VIEW 8X b 0.10 M 0.05 M B NOE 3 1 0.50 IH 8X 0.30 DIMENION: MILLIMEER *For additional information on our b Free strategy and soldering details, please download the ON emiconductor oldering and Mounting echniques Reference Manual, OLDERRM/D. ON emiconductor is licensed by hilips orporation to carry the I 2 Bus rotocol. ON emiconductor and are trademarks of emiconductor omponents Industries, LL dba ON emiconductor or its subsidiaries in the United tates and/or other countries. ON emiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ON emiconductor s product/patent coverage may be accessed at /site/pdf/atent Marking.pdf. ON emiconductor reserves the right to make changes without further notice to any products herein. ON emiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON emiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON emiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON emiconductor. ypical parameters which may be provided in ON emiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ON emiconductor does not convey any license under its patent rights nor the rights of others. ON emiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. hould Buyer purchase or use ON emiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON emiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON emiconductor was negligent regarding the design or manufacture of the part. ON emiconductor is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. UBLIION ORDERING INFORMION LIERURE FULFILLMEN: Literature Distribution enter for ON emiconductor 19521 E. 32nd kwy, urora, olorado 80011 U hone: 303 675 2175 or 800 344 3860 oll Free U/anada Fax: 303 675 2176 or 800 344 3867 oll Free U/anada Email: orderlit@onsemi.com N. merican echnical upport: 800 282 9855 oll Free U/anada Europe, Middle East and frica echnical upport: hone: 421 33 790 2910 Japan ustomer Focus enter hone: 81 3 5817 1050 10 ON emiconductor Website: Order Literature: http:///orderlit For additional information, please contact your local ales Representative NV2402WF/D