PD - 95355A SMPS MOSFET IRFR5N20DPbF IRFU5N20DPbF HEXFET Power MOSFET Applications High frequency DC-DC converters Lead-Free l l V DSS R DS(on) max I D 200V 65Ω 7A Benefits Low Gate-to-Drain Charge to Reduce Switching Losses Fully Characterized Capacitance Including Effective C OSS to Simplify Design, (See App. Note AN0) Fully Characterized Avalanche Voltage and Current l l l D-Pak IRFR5N20D I-Pak IRFU5N20D Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 7 I D @ T C = 0 C Continuous Drain Current, V GS @ V 2 A I DM Pulsed Drain Current 68 P D @T C = 25 C Power Dissipation 40 P D @T A = 25 C Power Dissipation* 3.0 W Linear Derating Factor 0.96 W/ C V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 8.3 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range Soldering Temperature, for seconds 300 (.6mm from case ) C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.04 R θja Junction-to-Ambient (PCB mount)* 50 C/W R θja Junction-to-Ambient Notes through are on page www.irf.com /7/05
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 200 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.26 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 65 Ω V GS = V, I D = A V GS(th) Gate Threshold Voltage 3.0 5.5 V V DS = V GS, I D = 250µA 25 V µa DS = 200V, V GS = 0V I DSS Drain-to-Source Leakage Current 250 V DS = 60V, V GS = 0V, T J = 50 C Gate-to-Source Forward Leakage 0 V GS = 30V I GSS na Gate-to-Source Reverse Leakage -0 V GS = -30V Dynamic @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 4.0 S V DS = 50V, I D = A Q g Total Gate Charge 27 4 I D = A Q gs Gate-to-Source Charge 6.9 nc V DS = 60V Q gd Gate-to-Drain ("Miller") Charge 4 2 V GS = V, t d(on) Turn-On Delay Time 9.7 V DD = 0V t r Rise Time 32 ns I D = A t d(off) Turn-Off Delay Time 7 R G = 6.8Ω t f Fall Time 8.9 V GS = V C iss Input Capacitance 9 V GS = 0V C oss Output Capacitance 70 V DS = 25V C rss Reverse Transfer Capacitance 3 pf ƒ =.0MHz C oss Output Capacitance 380 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 67 V GS = 0V, V DS = 60V, ƒ =.0MHz C oss eff. Effective Output Capacitance 50 V GS = 0V, V DS = 0V to 60V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 260 mj I AR Avalanche Current A E AR Repetitive Avalanche Energy 4 mj Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 7 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 68 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.5 V T J = 25 C, I S = A, V GS = 0V t rr Reverse Recovery Time 30 200 ns T J = 25 C, I F = A Q rr Reverse RecoveryCharge 6 920 nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2 www.irf.com
I D, Drain-to-Source Current (A) 0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0V 20µs PULSE WIDTH 0.0 T J = 25 C 0 V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current (A) 0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0V 20µs PULSE WIDTH T J = 75 C 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 0 T J = 75 C T J = 25 C V DS= 50V 20µs PULSE WIDTH 0.0 5 6 7 8 9 2 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.5 I D = 7A 3.0 2.5 2.0.5.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 0 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
I D, Drain-to-Source Current (A) C, Capacitance(pF) IRFR/U5N20DPbF 000 00 0 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 0 00 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 20 6 2 8 4 I = D A V DS = 60V V DS = 0V V DS = 40V FOR TEST CIRCUIT SEE FIGURE 3 0 0 20 30 40 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 0 T J = 75 C T J = 25 C V GS = 0 V 0.0 0.4 0.8.2.6 2.0 2.4 V SD,Source-to-Drain Voltage (V) 00 0 Tc = 25 C Tj = 75 C Single Pulse OPERATION IN THIS AREA LIMITED BY R DS (on) 0µsec msec msec 0 00 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
20 V DS R D I D, Drain Current (A) 5 5 Fig a. Switching Time Test Circuit V DS 90% R G V GS V GS Pulse Width µs Duty Factor % D.U.T. - V DD 0 25 50 75 0 25 50 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) D = 0.50 0.20 0. 0.05 0.02 SINGLE PULSE t2 0.0 (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 0.0 2. Peak T J = P DM x Z thjc TC 0.0000 0.000 0.00 0.0 t, Rectangular Pulse Duration (sec) PDM t Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
R G V DS 20V V GS tp L D.U.T IAS 0.0Ω Fig 2a. Unclamped Inductive Test Circuit tp 5V DRIVER - V DD A V (BR)DSS E AS, Single Pulse Avalanche Energy (mj) 600 500 400 300 200 0 TOP BOTTOM I D 4.2A 7.2A A 0 25 50 75 0 25 50 75 Starting T, Junction Temperature ( J C) Fig 2c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 2b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF V GS Q GS Q GD D.U.T. V - DS V GS V G 3mA Charge Fig 3a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFET Power MOSFETs www.irf.com 7
D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR20 WIT H AS S EMBLY LOT CODE 234 ASSEMBLED ON WW 6, 999 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 96A 2 34 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 6 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE IRFU20 2 34 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 999 WEEK 6 A = ASSEMBLY SITE CODE 8 www.irf.com
I-Pak (TO-25AA) Package Outline Dimensions are shown in millimeters (inches) IRFR/U5N20DPbF I-Pak (TO-25AA) Part Marking Information EXAMPLE: THIS IS AN IRFU20 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 9, 999 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S E MBL Y LOT CODE IRFU20 99A 56 78 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 9 LINE A OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 56 78 PART NUMBER DATE CODE P = DES IGNAT E S LEAD-F RE E PRODUCT (OPTIONAL) YEAR 9 = 999 WEEK 9 A = ASSEMBLY SITE CODE www.irf.com 9
D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA-54. 3 INCH Notes: NOTES :. OUTLINE CONFORMS TO EIA-48. Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 4.9mH R G = 25Ω, I AS = A. ƒ I SD A, di/dt 70A/µs, V DD V (BR)DSS, T J 75 C 6 mm Pulse width 400µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS * When mounted on " square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information.0/05 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/