Testing Advanced Photovoltaic Inverters Conforming to IEEE Standard 1547 Amendment 1

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < Testing Advanced Photovoltaic Inverters Conforming to IEEE Standard 547 Amendment Anderson Hoke, Student Member, IEEE, Sudipta Chakraborty, Senior Member, IEEE, and Thomas Basso, Senior Member, IEEE Abstract This paper introduces a new test plan and provides results for testing photovoltaic inverters with advanced grid support features including voltage regulation, wider voltage and frequency operating ranges, and voltage and frequency ridethrough, as allowed by IEEE Standard 547-Amendment. The test plan emphasizes testing for interactions between and among advanced inverter features and conventional features (e.g., unintentional islanding), and it includes testing of inverter dynamic response when regulating voltage. Results are included from testing of a single-phase inverter and a three-phase inverter. Index Terms Inverters, photovoltaic, electric power systems, reactive power control, voltage control, IEEE 547, IEEE 547.. W I. INTRODUCTION ith large amounts of distributed energy resources (DERs) such as photovoltaic (PV) systems being deployed, newer DER interconnection functions are required for reliable and efficient operation of electric power systems (EPSs). The IEEE Standards Association has published an amendment to IEEE Standard 547-23 (IEEE 547) []. The amendment, IEEE Standard 547a Amendment (IEEE 547a), updates the 23 published requirements for voltage regulation and response to area EPS abnormal voltage and frequency conditions, and considers whether other changes to IEEE 547 are necessary in response to these updates [2]. IEEE Standard 547.-25 (IEEE 547.) specifies test procedures to confirm whether DERs conform to the original IEEE 547 [3]. New test procedures are needed to verify the conformance of advanced interconnection systems to the new requirements of IEEE 547a. The advanced grid-support features can interact with each other and with conventional inverter features. For example, the wider voltage and frequency trip settings in IEEE 547a could adversely impact the effectiveness of the islanding detection algorithms. Therefore, the new test procedures should verify that interactions between features do not negatively affect grid safety, stability, or power quality. Also, advanced grid-support features operate on a range of time scales from milliseconds This work was supported by the U.S. Department of Energy under Contract No. DE-AC36-8-GO2838 with the National Renewable Energy Laboratory. A. Hoke, S. Chakraborty, and T. Basso are with the National Renewable Energy Laboratory, Golden, CO 84 USA (email: andy.hoke@nrel.gov, sudipta.chakraborty@nrel.gov, thomas.basso@nrel.gov). to many minutes so the new test procedures should also test DER dynamic responses. Several efforts are under way related to advanced inverter test plan development. The SunSpec Alliance is developing standardized communications specifications for smart inverters [3], which are based on work by the Electric Power Research Institute (EPRI), International Electrotechnical Commission (IEC), and others [4] [7]. Sandia National Laboratory is developing a test plan based on the SunSpec specifications [8]. Some utilities have conducted their own testing using internally developed procedures [9]. The California Energy Commission (CEC), U.S. Federal Energy Regulatory Commission (FERC), U.S. National Institute of Standards (NIST), Underwriters Laboratories (UL), and other organizations are also seeking to standardize advanced inverter functions and test procedures [] [2]. Much of this work is in response to the experience of German utilities with high PV penetrations, where inverters have been retrofitted extensively to mitigate high-penetration issues [3] [4]. Successful deployment and standardization of inverters with advanced grid-support features may allow the U.S. to avoid such retrofitting. The National Renewable Energy Laboratory (NREL) developed a preliminary (beta) test plan for grid interconnection systems of advanced inverter-based DERs. This paper is a synopsis of the recently published NREL technical report [5] that provides the beta test procedures for advanced PV inverters. Two advanced PV inverters, one single-phase and one three-phase, were tested under that beta test plan and test results were included in the NREL report [5]. In addition to the test results presented in [5], this paper includes the results of additional tests investigating the impact of advanced grid-support functions on unintentional island detection. The beta test plan was written before the first IEEE working group meeting to develop IEEE Standard 547.-Amendment (IEEE 547.a). The beta test plan is intended to support the IEEE working group standard-development process and provides additional experience beyond standards conformance testing, such as inverter characterization testing. Section II of this paper discusses the NREL-developed beta test plan, including some representative figures showing characteristics of the advanced functions. Sections III and IV give sample test results for the single-phase and three-phase inverters, respectively, tested at NREL. Section V discusses the plan for the future work that includes testing using power

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2 hardware-in-the-loop (PHIL). Finally, Section VI provides conclusions. II. TEST PLAN NREL s beta test plan follows the format and methodology established by IEEE 547., while incorporating () upgraded tests for response to abnormal voltage and frequency including ride-through, (2) a newly developed test for voltage regulation, and (3) modified tests for unintentional islanding, open phase, and harmonics. Although IEEE 547a does not mandate ride-through requirements, its language does allow such functionality, and future revisions may require it. Hence, test procedures for ride-through are included in NREL s test plan. The details of the following test procedures are in [5]. A. Test for Response to Abnormal Voltage Conditions The purpose of this test is to verify that the PV inverter interconnection component or system ceases to energize the area EPS as specified in IEEE 547a with respect to overvoltage and undervoltage conditions. In contrast to the original IEEE 547., the NREL test plan provides a single test procedure to cover both overvoltage and undervoltage. The test procedure consists of two parts: magnitude testing and time testing. Under the magnitude testing, test procedures for three different inverter behaviors are developed to validate that () clearing voltage levels are in compliance with IEEE 547a, (2) adjustable clearing voltage levels and associated times behave as expected (for inverters that implement adjustable clearing voltages), and (3) adjustable must remain connected voltage ride-through magnitude settings behave as expected (if voltage ride-through settings are implemented in the inverter). Voltage ride-through behavior is defined by specifying a range of voltage disturbances and disturbance times for which the inverter must remain connected to the EPS (i.e., must not trip). Voltage trip and ride-through magnitudes are tested by slowly ramping the EPS voltage up (or down) at a rate designed to allow determination of the exact voltage magnitude that causes the inverter to trip. Multiple combinations of operating conditions are tested including tests for various trip settings, phases, ride-through settings, and voltage regulation settings. The allowable voltage trip magnitudes and associated maximum clearing times from IEEE 547a are shown in Fig.. Fig. 2 shows an example inverter configuration with both voltage trip settings and voltage ride-through settings. Similarly to the magnitude tests, the voltage time test procedures verify three different inverter behaviors: () clearing times at various voltage levels are in compliance with IEEE 547a, (2) adjustable clearing times at various voltage levels behave as expected (for inverters with adjustable clearing times), and (3) adjustable must remain connected voltage ride-through time settings behave as specified by the manufacturer (if voltage ride-through settings are implemented in the inverter). Voltage ride-through and trip times are measured using prescribed voltage steps designed to determine the time between the start of an over/undervoltage and the disconnection of the inverter from the EPS. Multiple combinations of operating conditions are tested, as under the magnitude tests. Both the magnitude test and time test include procedures to test that any adjustable ride-through settings cannot be set in a manner that interferes with trip settings. Fig.. Widest allowable voltage trip magnitudes and maximum clearing times from IEEE 547a. (Not to scale) t R4 t R t C5 EUT must remain connected t C V T V T5 V R4 V R EUT must disconnect EUT must disconnect Time Fig. 2. An example of voltage trip and ride-through boundaries. EUT = equipment (inverter) under test. B. Test for Response to Abnormal Frequency Conditions t R3 t C2 The test procedures for abnormal frequency conditions are similar to those for abnormal voltage. They verify that the inverter s response to over- and underfrequency conditions is compliant with IEEE 547a, and that voltage ride-through performs as expected, if implemented. Similarly to the abnormal voltage test, the frequency test includes procedures to verify the frequency magnitudes at which the inverter trips and the time to trip for each frequency level. The description of each test is similar to those for the voltage tests described in the previous section. Fig. 3 shows the default trip frequencies given in IEEE 547a and the associated maximum clearing times for each frequency level. Both the magnitude test and the time test include procedures to test that any adjustable ride-through settings cannot be set in a manner that interferes with trip settings. t C4 V T2 t R2 V R3 t C3 V T4 V R2 V T3

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 3 Fig. 5. Sample test voltage profile. Fig. 3. 547a. Default trip frequencies and maximum clearing times from IEEE C. Test for Voltage Regulation through Volt-VAR Control The purpose of this test is to verify that the PV inverter provides voltage support by producing or absorbing reactive power as specified by the manufacturer. If the inverter is not capable of modifying its power factor or reactive power output, this test shall not be performed. Multiple methods of reactive power support are possible. The NREL beta test plan currently covers provision of reactive power as a function of voltage based on a (V) characteristic [5]. In the test procedure, maximum available reactive power is defined according to the inverter manufacturer s documentation. Test procedures are provided for testing various (V) characteristics including those that include deadband and/or hysteresis. An example (V) characteristic with hysteresis and deadband is shown in Fig. 4. The test plan specifies voltage profiles to test each of these (V) characteristics. An example test voltage profile is shown in Fig. 5. The voltage ramp rate is specified based on the settling time of the inverter s (V) response to be slow enough that the inverter s reactive power is in quasi-steady-state during the ramp; hence, we refer to this test as the quasistatic volt-var test. Fig. 6 shows the pass/fail criteria for measured reactive power during the test. In addition to testing the steady-state (V) characteristic, the test plan also verifies that the inverter s dynamic response to voltage steps while in volt- VAR mode is in line with the manufacturer s stated rise time, settling time, and overshoot value. Fig. 6. Acceptable range of measured reactive power relative to the commanded characteristic, where b = a + n, n is the maximum amplitude of noise in the RMS voltage measurement, a is the manufacturer s stated accuracy of voltage, and a2 is the manufacturer s stated accuracy of reactive power. D. Unintentional Islanding Test Two steps are added to the original IEEE 547. test procedure to ensure that the inverter s island detection system continues to function appropriately in the presence of four advanced grid-support features: () wider voltage operating range, (2) wider frequency operating range, (3) voltage regulation, and (4) frequency response/regulation. The standard islanding test is repeated in the presence of selected combinations of these four advanced features. E. Other Modified Tests The NREL beta test plan also includes modified tests for open phase and harmonics. The open-phase test from IEEE 547. is repeated while performing each of the four advanced grid-support features listed above individually, and while performing all four simultaneously. The harmonics test from IEEE 547. is repeated with voltage regulation running and again with grid-frequency response/regulation running. Fig. 4. (V) characteristic including hysteresis and deadband. III. SINGLE-PHASE INVERTER TEST RESULTS Two inverters were tested at NREL to evaluate the beta test plan. One was a commercially available single-phase 3-kW advanced PV inverter. The other was a prototype three-phase 5-kW inverter developed at NREL. Although the NREL test plan calls for repetition of various tests, most tests were run only one or two times per inverter for evaluation purposes. Selected results from the testing of both inverters are discussed in this section and the next. For complete results,

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 4 see [5]. A simple diagram of the test setup is shown in Fig. 7. It includes a controllable DC supply, a resistive-inductivecapacitive (RLC) load bank, and a controllable AC power supply (grid simulator). For the single-phase tests, the nominal grid voltage was 24 V AC, and the nominal DC voltage was 25 V DC. As in IEEE 547. testing, it is assumed that PV variability will not impact the inverter s interconnection system, so the PV array (or other energy source) is represented by a DC supply for testing purposes. Communication with the inverter was established through RS-485 using the manufacturer s proprietary protocol. Features tested were multi-level voltage trip settings, multi-level frequency trip settings, unintentional islanding, volt-var control (voltage regulation), and high-frequency power curtailment. voltage / current, p.u. 5 2 25 3 35 Fig. 8. Inverter RMS voltage and current during a voltage time test with volt-var control running. voltage / current, p.u..5.5.5.5 Trip time = 2.96 s 3 35 4 45 5 55 Fig. 9. Inverter RMS voltage and current during a voltage time test without volt-var control running. Fig. 7. Advanced inverter test setup single-line diagram. Table shows abnormal voltage trip times for each of the settings tested. The inverter passed all voltage trip time tests, both with and without volt-var running. No evidence was found that volt-var control impacts the trip time or magnitude. In all tests, the inverter tripped within.3 to.6 second of the designated time. The trip magnitude tests were similar in that performing volt-var control did not significantly impact the test results and in that the inverter consistently tripped very close to the designated voltage magnitude. Volt-VAR s TABLE I VOLTAGE TRIP TIME TESTS FOR SINGLE-PHASE INVERTER Voltage Trip (%) Trip Time (s) Measured Trip Time (s) Result Off 6.6.3 Pass 88 9.96 Pass 3 2.94 Pass 2.6.3 Pass On (with deadband) 6.6.3 Pass 88 9.96 Pass 3 2.96 Pass 2.6.3 Pass Fig. 8 shows plots of RMS inverter voltage and current during typical trip time tests at the % voltage level with volt-var control running, and Fig. 9 shows the same test without volt-var control running. No significant difference is evident. Table II shows abnormal voltage trip magnitudes. Again, the inverter passed all tests both with and without volt-var running. Fig. shows the results of an undervoltage magnitude test at the 6% voltage level with volt-var control running. Note that the steep voltage ramp serves to reach the holding voltage prior to the test; the actual test ramp is nearly imperceptible. The same test without volt-var control running was nearly identical. TABLE II VOLTAGE TRIP MAGNITUDE TESTS FOR SINGLE-PHASE INVERTER Volt-VAR Voltage Trip Trip Time Measured Trip Result (%) (s) Voltage (%) Off 6.6 6.32 Pass 6.6 6.2 Pass 88 88.27 Pass 3 9.56 Pass 2.6 9.35 Pass On (with deadband) voltage / current, p.u..5.5 45.6 47. Pass 6.6 6.2 Pass 6.6 6.2 Pass 88 88.2 Pass 3 9.6 Pass 2.6 9.6 Pass 8 9 2 3 4 5 6 Fig.. Inverter RMS voltage and current during a voltage magnitude test without volt-var control running.

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 5 The inverter also passed all frequency tests for both magnitude and time. Table III shows the trip times and Table IV shows the trip frequencies. No evidence was found that high-frequency power curtailment interferes with the inverter s ability to respond correctly to abnormal frequencies. In all frequency magnitude tests, the inverter tripped within.2 Hz of the commanded frequency. In all frequency time tests, the inverter tripped when 9% of the clearing time had passed (minus a few AC line cycles). Frequency Response Off TABLE III FREUENCY TRIP TIME TESTS FOR SINGLE-PHASE INVERTER Volt- VAR On (with deadband) Frequency Trip (Hz) Trip Time (s) Measured Trip Time (s) Result 56 8.99 Pass 58 3 269.9 Pass 62 9 8.96 Pass 64 8.98 Pass Off Off 57.6.2 Pass 6.5.6. Pass 64 2.77 Pass 2% Slope Off 64.6. Pass 4% Slope 56.6.2 Pass 4% Slope 64.6.3 Pass Frequency Response TABLE IV FREUENCY TRIP MAGNITUDE TESTS Volt- VAR Frequency Trip (Hz) Trip Time (s) Measured Trip Freq. (Hz) Result Off Off 56.6 56. Pass 58 58. Pass 62 62.2 Pass 64.6 64. Pass P(f) 2% Slope Off 64.6 64. Pass P(f) 4% Slope 64.6 64. Pass Figs. and 2 show the inverter RMS current and AC frequency during frequency magnitude tests at the 64 Hz level without and with high-frequency power curtailment running, respectively. Measured trip frequencies were identical. In Fig., note that as the frequency ramps up steeply, the inverter current increases. This is unexpected behavior. During this time, the inverter is importing reactive power, apparently due to its grid synchronization controls falling slightly out of sync with the increasing grid frequency, causing the inverter current to lag the voltage. After the steep ramp ends, the inverter recovers synchronization in about 2 s. frequency, Hz 65 6 frequency 55 5 5 2 25 3 35 Fig.. Inverter RMS current and grid frequency during a frequency magnitude test without high-frequency power curtailment running. 2 current, p.u. frequency, Hz 65 6 55 5 5 2 25 3 35 Fig. 2. Inverter RMS current and grid frequency during a frequency magnitude test with high-frequency power curtailment running. Although this inverter does not claim voltage or frequency ride-through capability, its responses to abnormal voltage and frequency are very consistent. Therefore, by setting the trip magnitudes and times slightly outside any desired ride-through boundaries, the inverter could be configured to remain connected during a given set of voltage and frequency deviations. For example, a frequency trip setting of 62 Hz and s could be interpreted to imply that the inverter will ride through any frequency disturbance up to 6.98 Hz and 8.94 seconds. The inverter is capable of adjusting its reactive power output as a function of voltage (volt-var control). It can do so following a (V) characteristic with or without deadband or hysteresis. Various tests were completed with different (V) characteristics chosen to thoroughly verify the inverter s range of volt-var settings. Fig. 3 shows sample results from one volt-var test in which the inverter (V) characteristic was set with deadband. Note that the measured (V) characteristic follows discrete steps. The measured results follow the (V) characteristic well in the deadband regions and near nominal voltage but deviate slightly when voltage goes away from nominal. re a c tiv e p o w e r, V A r 2 frequency -2 2 22 23 24 25 26 27 RMS voltage, V Fig. 3. Inverter reactive power vs. voltage during a test of volt-var control with deadband. Fig. 4 shows an enlarged plot of measured and commanded reactive power during a similar test with a different (V) command. Note that in this test, the measured reactive power exceeds the commanded reactive power for high voltages, whereas in Fig. 3 the measured reactive power is below the command for high voltages. Fig. 4 demonstrates the method used to determine whether the measured reactive power is close enough to the commanded reactive power to pass the test (see Fig. 6). The manufacturer s specified accuracy of reactive power (a2) is not known, but would need to be at least 2 VAR to pass the test. cmd 2 current, p.u.

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 6 reactive power, VAr Fig. 4. Close-up of inverter reactive power vs. voltage during a volt-var test, illustrating how the worst-case deviation between commanded and measured (V) can be used to evaluate whether the inverter meets the test criteria. Fig. 5 shows a sample test of the inverter s dynamic response to voltage steps while in volt-var mode. The reactive power response is nearly critically damped, with no overshoot or ringing, thus passing the test. voltage, p.u -8 - -2-4 -6-2 V.8 5 5 2 25 3 35 P Fig. 5. Inverter reactive power and voltage during a volt-var dynamic test. The original unintentional islanding tests shown in [5] were performed using a PHIL-based method [6]. However, for this paper, additional islanding tests were performed using the standard RLC load method from IEEE 547., and those tests were repeated with advanced grid-support features running. Table V defines three configurations of abnormal voltage and frequency trip settings: 547 uses the original trip settings from IEEE 547; 547a uses the widest trip settings from IEEE 547a; and 547a2 uses the widest voltage trip settings from IEEE 547a, along with the original IEEE 547 frequency trip settings. Table VI shows the trip times for the unintentional islanding tests. TABLE V DISCONNECTION SETTING CONFIGURATIONS FOR ISLANDING TESTS Name Fast Slow Slow Fast Overfreq. Underfreq. Overvolt. Overvolt. Undervolt. Undervolt. 547 2%.6 s % s 88% 2 s 5%.6 s 6.5 Hz.6 s 59.3 Hz,.6 s 547a 2%.6 s % 3 s 6% s 45%.6 s 64 Hz s 56 Hz s 547a2 2%.6 s 247 248 249 25 25 252 253 254 255 256 L-L voltage, % 3 s 6% s 45%.6 s 6.5 Hz.6 s cmd 4 2 VA 59.3 Hz,.6 s TABLE VI ISLAND TRIP TIMES FOR SINGLE-PHASE INVERTER Frequency Volt- Trip Load uality Measured Trip Result Response VAR s Factor Time (s) Off Off 547..259 Pass Off Off 547..277 Pass Off Off 547a2..626 Pass Off Off 547a..655 Pass Off Off 547a..66 Pass Off Off 547a..6 Pass Off Off 547a..626 Pass Off On 547a..66 Pass Off On 547a..68 Pass On On 547a..339 Pass On On 547a..259 Pass Off Off 547 2.5.285 Pass Off Off 547 2.5.36 Pass On On 547a 2.5.272 Pass On On 547a 2.5.277 Pass On On 547a 2.5.335 Pass In all cases, the inverter passes the test by disconnecting in less than 2 seconds. However, note that although the disconnection times are.34 s without advanced gridsupport running, they are.6 s in the tests with advanced grid-support features running. It was generally found to be the case that wide voltage and frequency operating regions extend the island disconnection time to between.6 and.7 seconds, although high-frequency power curtailment actually negates that effect, bringing disconnection time down to between.25 and.35 seconds even with wide voltage and frequency operation ranges. It is not known what type of island detection scheme this inverter uses. Fig. 6 shows an unintentional islanding test without any advanced grid-support features running. Fig. 7 shows the same test with voltage and frequency trip levels and times set to their widest settings, and with volt-var control running. voltage, current, p.u..5 Grid on.6.8 2 2.2 2.4 2.6 2.8 3 Fig. 6. Unintentional islanding test without advanced grid support on. voltage, current, p.u..5 Grid on.6.8 2 2.2 2.4 2.6 2.8 3 Fig. 7. Unintentional islanding test with advanced grid support running.

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 7 Five islanding tests were performed with the quality factor (F) of the resonant load tuned to 2.5 as suggested in IEEE Standard 929-2 [7] (rather than. as prescribed in IEEE 547. and in [5]) to investigate whether a less-damped resonance would lead to longer disconnection times. These tests were performed both with and without advanced gridsupport functions running. Disconnection times in these five tests were similar to the corresponding tests with a F of.; no evidence was found that a F of 2.5 extends islanded disconnection time. IV. THREE-PHASE INVERTER TEST RESULTS The test setup for the three-phase prototype inverter was similar to the single-phase setup (Fig. 7). The nominal DC voltage was 45 V and the nominal AC line-to-line voltage was 28 V RMS in a three-wire delta configuration. Responses to abnormal voltage and frequency were generally similar to those for the single-phase inverter. Tables VII and VIII show voltage trip times and magnitudes, respectively. Both disconnection magnitudes and disconnection times were very close to the commanded magnitudes and times, though disconnection times were typically one to four cycles longer than commanded because this prototype inverter does not account for fixed delays in the disconnection process. Volt-VAR control did not impact disconnection times. Fig. 8 shows a voltage magnitude test at the % voltage level. TABLE VII THREE-PHASE INVERTER VOLTAGE TRIP TIME TESTS Volt-VAR Voltage Trip (%) Trip Time (s) Measured Trip Result Time (s) Off 45.6.234 Pass* 6.28 Pass* 88 2 2.3 Pass* 2 2.43 Pass* 3 3.43 Pass* 3 3.47 Pass* 2.6.87 Pass* On, without deadband or hysteresis 45.6.94 Pass* 6.24 Pass* 88 2 2.3 Pass* 3 3.48 Pass* 2.6.9 Pass* *Trip timer needs adjustment for fixed delays TABLE VIII THREE-PHASE INVERTER VOLTAGE TRIP MAGNITUDE TESTS Volt-VAR Voltage Trip Trip Time Measured Result (%) (s) Trip Time (s) Off 45.6 45.9 Pass 6 2 6.4 Pass 88 2 88.6 Pass 2 9.82 Pass 2.6.72 Pass On, without deadband or hysteresis 45.6 45. Pass 6 2 6. Pass 88 2 88.3 Pass 2 9.6 Pass 2.6.56 Pass voltage and current, p.u..5.5 Trip voltage = 9.6%..2.3.4.5.6.7 Fig. 8. An overvoltage magnitude test with advanced grid support running. Tables IX and X show frequency trip times and magnitudes, respectively. Fig. 9 shows an overfrequency time test at the 64 Hz level with a 6 s disconnection time, without advanced grid support running. The inverter passes the test, but note that the frequency step induces significant ringing in the current waveform, which should be addressed as the prototype is refined. TABLE IX THREE-PHASE INVERTER FREUENCY TRIP TIME TESTS Trip Magnitude Trip Time Measured Trip Result (Hz) (s) Time (s) 56.6.8 Pass* 56 6 6.2 Pass* 59.5 3 299.98 Pass 64 6 6.2 Pass* 64.6.83 Pass* *Trip timer needs adjustment for fixed delays TABLE X THREE-PHASE INVERTER FREUENCY TRIP MAGNITUDE TESTS Trip Magnitude Trip Time Measured Trip Result (Hz) (s) Freq. (Hz) 56.6 55.99 Pass 59.5 6 59.49 Pass 6.5 6 6.5 Pass 64.6 63.99 Pass frequency, Hz 8 6 4 2 frequency 2 3 4 5 6 7 8 9 Fig. 9. An overfrequency time test without advanced grid support running. Fig. 2 shows the measured and commanded (V) characteristic for a quasistatic volt-var test. The measured reactive power matches the command very well. 2.5.5 current, p.u.

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 8 reactive power, VAr 5-5 2 3 4 L-N voltage, Fig. 2. A three-phase quasistatic volt-var test. Fig. 2 shows a dynamic volt-var test. The reactive power resonates significantly following each voltage step, causing corresponding ringing in the point of common coupling (PCC) voltage. Again, this ringing should be addressed by modifying the inverter controls. voltage, p.u.2 Fig. 2. A three-phase dynamic voltage step response test of volt-var. V. FUTURE WORK Future work will investigate other emerging inverter features, including ceasing to export power without disconnecting during transient undervoltage events, returning to service after those events, other methods of voltage support, and methods of frequency support. Inverter test procedures have historically focused on testing a single inverter at a single PCC. However, some advanced inverter functions (such as volt-var) will impact the EPS in which the inverter is connected, requiring dynamic feedback between the inverter test article and the EPS. Significant future work using PHIL is planned for testing the advanced grid-support features under conditions that simulate EPS dynamics for realistic testing of one or more inverters. VI. CONCLUSIONS cmd -.5.8 V - 5 5 2 25 3 Due to the emerging nature of interconnection standards, test procedures for the new interconnection functions such as voltage regulation and wider voltage and frequency operating ranges are not yet fully harmonized. This paper covers the important topic of advanced inverter testing based on a recently published NREL report. The test plan summarized here follows the framework established by IEEE 547. while establishing new and modified tests for the advanced gridsupport features. These test procedures consider not only the individual interconnection functions but also the interactions among various new and existing features. The preliminary test plan was applied to two inverters and worked well for both. Some interesting observations were made from initial testing such as () separate voltage and frequency ride-through settings may not be necessary if the trip test results adhere closely to commanded values, and (2) performing voltage or frequency ride-through (or having a.5 VAR, p.u wide band of operating voltages and frequencies) may prolong the trip time during unintentional-islanding tests. Test results presented here also emphasize the importance of testing inverter dynamic response for functions such as volt-var control. REFERENCES [] IEEE 547: IEEE Standard for Interconnecting Distributed Resources with Electric Power Systems. IEEE Std 547, 23. [2] IEEE 547a: Draft Standard for Interconnecting Distributed Resources with Electric Power Systems, Amendment. IEEE Std 547a, 24. [3] IEEE 547.: IEEE Standard Conformance Test Procedures for Equipment Interconnecting Distributed Resources with Electric Power Systems. IEEE Std 547., 25. [4] Specification for Smart Inverter Interactions with the Electric Grid Using International Electrotechnical Commission 685, EPRI, Palo Alto, CA, 2. [5] DNP3 Profile for Basic Photovoltaic Generation and Storage, DPN3 AN2-, Mar. 2. [6] IEC 685 Object Models for Photovoltaic, Storage and Other DER Inverters, IEC 685-9-7, version 27a, 22. [7] Common Functions for Smart Inverters, Version 3, EPRI, Palo Alto, CA, Feb 24. [8] J. Johnson, S. Gonzalez, M. E. Ralph, A. Ellis, and R. Broderick, Test Protocols for Advanced Inverter Interoperability Functions, Sandia National Laboratories, SAND23-988, Nov. 23. [9] R. Bravo, S. Robles, and R. Yinger, SCE Solar PV Inverter Test Procedure, Southern California Edison, July 23. [] Rule 2 Smart Inverter Working Group Technical Reference Materials, California Energy Commission. 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Coddington, Methods and Implementation of Advanced Unintentional Islanding Testing using Power Hardware-in-the-Loop (PHIL), IEEE Photovoltaic Specialists Conference (PVSC), June 9 3, Tampa Bay, FL, USA. [7] IEEE Std 929-2: IEEE Recommended Practice for Utility Interface of Photovoltaic (PV) Systems. IEEE Std 929-2, 2.