Features n Floating channel designed for bootstrap operation Fully operational to +4V Tolerant to negative transient voltage dv/dt immune n Gate drive supply range from 1 to 2V n Undervoltage lockout for both channels n Separate logic supply range from 5 to 2V Logic and power ground ±5V offset n CMOS Schmitt-triggered inputs with pull-down n Cycle by cycle edge-triggered shutdown logic n Matched propagation delay for both channels n Outputs in phase with inputs Data Sheet No. PD-6.85 HIGH AND W SIDE DRIVER Product Summary VOFFSET IO+/- VOUT ton/off (typ.) Delay Matching Description 4V max. 2A / 2A 1-2V 12 & 94 ns 1 ns The is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 4 volts. Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol Parameter Units V B High Side Floating Supply Voltage -.5 V S + 2 V S High Side Floating Supply Offset Voltage 4 V High Side Floating Output Voltage V S -.5 V B +.5 V CC Low Side Fixed Supply Voltage -.5 2 V Low Side Output Voltage -.5 V CC +.5 V V DD Logic Supply Voltage -.5 V SS + 2 V SS Logic Supply Offset Voltage V CC - 2 V CC +.5 V IN Logic Input Voltage (HIN, LIN & SD) V SS -.5 V DD +.5 dv s /dt Allowable Offset Supply Voltage Transient (Figure 2) V/ns P D Package Power Dissipation @ T A + C 1.6 W R thja Thermal Resistance, Junction to Ambient C/W T J Junction Temperature -55 T S Storage Temperature -55 C T L Lead Temperature (Soldering, 1 seconds) 3 Weight 1.5 (typical) g 2/14/97
Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figures 36 and 37. Symbol Parameter Units VB High Side Floating Supply Absolute Voltage VS + 1 VS + 2 VS High Side Floating Supply Offset Voltage -4 4 V High Side Floating Output Voltage VS VB V CC Low Side Fixed Supply Voltage 1 2 V V Low Side Output Voltage V CC VDD Logic Supply Voltage VSS + 5 VSS + 2 VSS Logic Supply Offset Voltage -5 5 VIN Logic Input Voltage (HIN, LIN & SD) VSS VDD Dynamic Electrical Characteristics VBIAS (VCC, VBS, VDD) = 15V, and VSS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3. Tj = C Tj = -55 to C Symbol Parameter Units Test Conditions t on Turn-On Propagation Delay 12 26 V S = V t off Turn-Off Propagation Delay 94 22 V S = 4V ns t sd Shutdown Propagation Delay 11 14 235 V S = 4V t r Turn-On Rise Time 35 CL = pf t f Turn-Off Fall Time 17 4 CL = pf MT Delay Matching, HS & LS Turn-On/Off 1 Ht on -Lt on / Ht off -Lt off Typical Connection up to V 4 V DD V DD V B HIN SD HIN SD V S TO AD LIN LIN V CC V SS V SS COM V CC
Static Electrical Characteristics VBIAS (VCC, VBS, VDD) = 15V, unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all three logic input pins: HIN, LIN and SD. The VO and IO parameters are referenced to COM or VS and are applicable to the respective output pins: or. Tj = C Tj = -55 to C Symbol Parameter Units Test Conditions V IH Logic 1 Input Voltage 3.1 3.3 VDD = 5V 6.4 6.8 VDD = 1V 9.5 1 V VDD = 15V 12.5 13.3 VDD = 2V V IL Logic Input Voltage 1.8 1.7 VDD = 5V 3.8 3.6 VDD = 1V 6 5.7 V VDD = 15V 8.3 7.9 VDD = 2V V OH High Level Output Voltage, V BIAS - V O.7 1.2 1.5 V IN =V IH, I O = A V OL Low Level Output Voltage, V O.1.1 V IN =V IH, I O = A I LK Offset Supply Leakage Current V B = V S = 4V I QBS Quiescent V BS Supply Current 23 µa V IN =V or V DD I QCC Quiescent V CC Supply Current 18 34 6 V IN =V, or V DD I QDD Quiescent V DD Supply Current 5 3 6 V IN =V, or V DD I IN+ Logic 1 Input Bias Current 15 4 7 V IN = V DD I IN- Logic Input Bias Current 1. 1 V IN = V V BSUV+ V BS Supply Undervoltage Positive 7.5 8.6 9.7 Going Threshold V BSUV- V BS Supply Undervoltage Negative 7. 8.2 9.4 Going Threshold V CCUV+ V CC Supply Undervoltage Positive 7.4 8.5 9.6 V Going Threshold V CCUV- V CC Supply Undervoltage Negative 7. 8.2 9.4 Going Threshold I O+ Output High Short Circuit Pulsed 2. V O = V, V IN = V DD Current A PW 1 µs I O- Output Low Short Circuit Pulsed 2. V O = 15V, V IN = V Current PW 1 µs
HV = 1 to 4V Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit ( to 4V) HIN LIN % % t on t r t off t f 9% 9% 1% 1% Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition HIN LIN % % SD % 1% t sd 9% MT 9% MT Figure 5. Shutdown Waveform Definitions Figure 6. Delay Matching Waveform Definitions
Turn-On Delay Time (ns) Turn-On Delay Time (ns) - - Figure 7A. Turn-On Time vs. Temperature 1 12 14 16 18 2 Figure 7B. Turn-On Time vs. Voltage Turn-Off Delay Time (ns) Turn-Off Delay Time (ns) - - Figure 8A. Turn-Off Time vs. Temperature 1 12 14 16 18 2 Figure 8B. Turn-Off Time vs. Voltage Shutdown Delay Time (ns) Shutdown Delay time (ns) - - Figure 9A. Shutdown Time vs. Temperature 1 12 14 16 18 2 Figure 9B. Shutdown Time vs. Voltage
8 8 Turn-On Rise Time (ns) 6 4 Turn-On Rise Time (ns) 6 4 2 2 - - Figure 1A. Turn-On Rise Time vs. Temperature 1 12 14 16 18 2 Figure 1B. Turn-On Rise Time vs. Voltage 4 4 Turn-Off Fall Time (ns) 3 2 Turn-Off Fall Time (ns) 3 2 1 1 - - Figure 11A. Turn-Off Fall Time vs. Temperature 1 12 14 16 18 2 Figure 11B. Turn-Off Fall Time vs. Voltage 15. 15. 12. 12. Logic "1" Input Threshold (V) 9. 6. Logic "1" Input Threshold (V) 9. 6. 3. 3.. - - Figure 12A. Logic 1 Input Threshold vs. Temperature. 5 7.5 1 12.5 15 17.5 2 VDD Logic Supply Voltage (V) Figure 12B. Logic 1 Input Threshold vs. Voltage
15. 15. 12. 12. Logic "" Input Threshold (V) 9. 6. Logic "" Input Threshold (V) 9. 6. 3. 3.. - - Figure 13A. Logic Input Threshold vs. Temperature. 5 7.5 1 12.5 15 17.5 2 VDD Logic Supply Voltage (V) Figure 13B. Logic Input Threshold vs. Voltage 5. 5. 4. 4. High Level Output Voltage (V) 3. 2. High Level Output Voltage (V) 3. 2. 1. 1.. - - Figure 14A. High Level Output vs. Temperature. 1 12 14 16 18 2 Figure 14B. High Level Output vs. Voltage 1. 15..8 12. Low Level Output Voltage (V).6.4 Logic "1" Input Threshold (V) 9. 6..2 3.. - - Figure 15A. Low Level Output vs. Temperature. 5 7.5 1 12.5 15 17.5 2 VDD Logic Supply Voltage (V) Figure 15B. Low Level Output vs. Voltage
Offset Supply Leakage Current (µa) 4 3 Offset Supply Leakage Current (µa) 4 3 - - 3 4 VB Boost Voltage (V) Figure 16A. Offset Supply Current vs. Temperature Figure 16B. Offset Supply Current vs. Voltage 4 4 V BS Supply Current (µa) 3 V BS Supply Current (µa) 3 - - Figure 17A. V BS Supply Current vs. Temperature 1 12 14 16 18 2 VBS Floating Supply Voltage (V) Figure 17B. V BS Supply Current vs. Voltage 6 6 VCC Supply Current (µa) 3 VCC Supply Current (µa) 3 - - Figure 18A. VCC Supply Current vs. Temperature 1 12 14 16 18 2 VCC Fixed Supply Voltage (V) Figure 18B. VCC Supply Current vs. Voltage
8 8 VDD Supply Current (µa) 6 4 2 VDD Supply Current (µa) 6 4 2 - - Figure 19A. VDD Supply Current vs. Temperature 5 7.5 1 12.5 15 17.5 2 VDD Logic Supply Voltage (V) Figure 19B. VDD Supply Current vs. Voltage Logic "1" Input Bias Current (µa) 8 6 4 2 Logic "1" Input Bias Current (µa) 8 6 4 2 - - Figure 2A. Logic 1 Input Current vs. Temperature 5 7.5 1 12.5 15 17.5 2 VDD Logic Supply Voltage (V) Figure 2B. Logic 1 Input Current vs. Voltage 5. 5. Logic "" Input Bias Current (µa) 4. 3. 2. 1. Logic "" Input Bias Current (µa) 4. 3. 2. 1.. - - Figure 21A. Logic Input Current vs. Temperature. 5 7.5 1 12.5 15 17.5 2 VDD Logic Supply Voltage (V) Figure 21B. Logic Input Current vs. Voltage
11. 11. VBS Undervoltage Lockout + (V) 1. 9. 8. 7. VBS Undervoltage Lockout - (V) 1. 9. 8. 7. 6. - - Figure 22. VBS Undervoltage (+) vs. Temperature 6. - - Figure 23. VBS Undervoltage (-) vs. Temperature 11. 11. VCC Undervoltage Lockout + (V) 1. 9. 8. 7. V CC Undervoltage Lockout - (V) 1. 9. 8. 7. 6. - - Figure 24. V CC Undervoltage (+) vs. Temperature 6. - - Figure. V CC Undervoltage (-) vs. Temperature 5. 5. 4. 4. Output Source Current (A) 3. 2. Output Source Current (A) 3. 2. 1. 1.. - - Figure 26A. Output Source Current vs. Temperature. 1 12 14 16 18 2 Figure 26B. Output Source Current vs. Voltage
5. 5. 4. 4. Output Sink Current (A) 3. 2. Output Sink Current (A) 3. 2. 1. 1.. - - Figure 27A. Output Sink Current vs. Temperature. 1 12 14 16 18 2 Figure 27B. Output Sink Current vs. Voltage 32V 32V 14V Junction 14V 1V Junction 1V Figure 28. IR211L6 T J vs. Frequency (IRFBC2) RGATE = 33W, VCC = 15V Figure 29. IR211L6 T J vs. Frequency (IRFBC3) RGATE = 22W, VCC = 15V 32V 14V 32V 14V Junction 1V Junction 1V Figure 3. IR211L6 TJ vs. Frequency (IRFBC4) RGATE = 15W, VCC = 15V Figure 31. IR211L6 TJ vs. Frequency (IRFPE) RGATE = 1W, VCC = 15V
32V 14V 32V 14V Junction 1V Junction 1V Figure 32. IR211L6S TJ vs. Frequency (IRFBC2) RGATE = 33W, VCC = 15V Figure 33. IR211L6S TJ vs. Frequency (IRFBC3) RGATE = 22W, VCC = 15V 32V 14V 32V 14V 1V 1V Junction Junction Figure 34. IR211L6S T J vs. Frequency (IRFBC4) RGATE = 15W, VCC = 15V Figure 35. IR211L6S T J vs. Frequency (IRFPE) RGATE = 1W, VCC = 15V. 2. VS Offset Supply Voltage (V) -2. -4. -6. -8. VSS Logic Supply Offset Voltage (V) 16. 12. 8. 4. -1. 1 12 14 16 18 2 VBS Floating Supply Voltage (V) Figure 36. Maximum VS Negative Offset vs. VBS Supply Voltage. 1 12 14 16 18 2 VCC Fixed Supply Voltage (V) Figure 37. Maximum VSS Positive Offset vs. VCC Supply Voltage
Functional Block Diagram V B V DD HIN R S Q V DD /V CC LEVEL SHIFT PULSE GEN HV LEVEL SHIFT UV DETECT PULSE FILTER R R S Q V S SD V CC LIN R S Q V DD /V CC LEVEL SHIFT UV DETECT DELAY V SS COM Lead Definitions Lead Symbol Description V DD HIN SD LIN V SS V B V S V CC COM Logic supply Logic input for high side gate driver output (), in phase Logic input for shutdown Logic input for low side gate driver output (), in phase Logic ground High side floating supply High side gate drive output High side floating supply return Low side supply Low side gate drive output Low side return
Case Outline and Dimensions MO-36AB Pin Assignment COM V CC V S V B V SS LIN SD HIN V DD WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, Tel: (31) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 7322 IR CANADA: 7321 Victoria Park Ave., Suite 21, Markham, Ontario L3R 2Z8, Tel: (95) 4 1897 IR GERMANY: Saalburgstrasse 157, 613 Bad Homburg Tel: ++ 49 6172 9659 IR ITALY: Via Liguria 49, 71 Borgaro, Torino Tel: ++ 39 11 451 111 IR FAR EAST: K&H Bldg., 2F, 3-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 86 IR SOUTHEAST ASIA: 315 Outram Road, #1-2 Tan Boon Liat Building, Singapore 316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 2/97