Targe Daa Shee, V1.2, Aug 2006 PROFET Two Channels, 19 mω Auomoive Power Never sop hinking.
Table of Conens Page Produc Summary....................................................3 1Overview.........................................................5 1.1 Block Diagram...................................................5 1.2 Terms.........................................................6 2 Pin Configuraion..................................................7 2.1 Pin Assignmen.......................................7 2.2 Pin Definiions and Funcions.......................................7 3 Elecrical Characerisics............................................8 3.1 Maximum Raings................................................8 4 Block Descripion and Elecrical Characerisics.......................10 4.1 Power Sages..................................................10 4.1.1 Oupu On-Sae Resisance.................................. 10 4.1.2 Inpu Circui............................................... 10 4.1.3 Inducive Oupu Clamp...................................... 11 4.1.4 Elecrical Characerisics.................................... 13 4.2 Proecion Funcions.............................................15 4.2.1 Over Load Proecion........................................ 15 4.2.2 Reverse Polariy Proecion................................... 16 4.2.3 Over Volage Proecion..................................... 16 4.2.4 Loss of Ground Proecion.................................... 17 4.2.5 Elecrical Characerisics.................................... 18 4.3 Diagnosis......................................................21 4.3.1 ON-Sae Diagnosis......................................... 22 4.3.2 OFF-Sae Diagnosis........................................ 24 4.3.3 Elecrical Characerisics.................................... 25 5 Package Oulines......................................27 6 Revision Hisory..................................................28 Targe Daa Shee 2 V1.2, 2006-08-14
PROFET Produc Summary The is a dual channel high-side power swich in PG-DSO-12-9 package providing embedded proecive funcions. The power ransisor is buil by a N-channel verical power MOSFET wih charge pump. The device is monolihically inegraed in Smar SIPMOS echnology. PG-DSO-12-9 Operaing volage V bb(on) 4.5..28V Over volage proecion V bb(az) 41 V On-Sae resisance R DS(ON) 19 mω Nominal load curren (one channel acive) I L(nom) 6A Adjusable curren limiaion I L(LIM) 7 A / 40 A Curren limiaion repeiive I L(SCr) 7 A / 40 A Sandby curren for whole device wih load I bb(off) 7.5 µa Basic Feaures Very low sandby curren 3.3 V and 5 V compaible logic pins Improved elecromagneic compaibiliy (EMC) Sable behavior a under volage Logic ground independen from load ground Secure load urn-off while logic ground disconneced Very low leakage curren from OUT o GND Green produc (RoHS complian) Type Ordering Code Package On reques PG-DSO-12-9 Targe Daa Shee 3 V1.2, 2006-08-14
Proecive Funcions Reverse baery proecion wih exernal resisor Shor circui proecion Overload proecion Muli-sep curren limiaion Adjusable curren limiaion Thermal shudown wih resar Over volage proecion wih exernal resisor Loss of ground and loss of V bb proecion Elecrosaic discharge proecion (ESD) Diagnosic Funcions InelliSense funcionaliy for each channel Proporional load curren sense signal by curren source Open load deecion in ON-sae by load curren sense Open load deecion in OFF-sae by volage source Feedback on over emperaure and curren limiaion in ON-sae Suppressed hermal oggling of faul signal Applicaions µc compaible high-side power swich wih diagnosic feedback for 12 V grounded loads All ypes of resisive, inducive and capaciive loads Mos suiable for loads wih high inrush currens, so as lamps Replaces elecromechanical relays, fuses and discree circuis Targe Daa Shee 4 V1.2, 2006-08-14
Overview 1 Overview The is a dual channel high-side power swich (Two Channels, 19 mω) in PG-DSO-12-9 power package providing embedded proecive funcions. Inegraed resisors a each inpu pin (IN1, IN2, CLA) reduce exernal componens. The load curren limiaion can be adjused in wo seps by he curren limi adjus pin (CLA). The InelliSense pins IS1 and IS2 provide a sophisicaed diagnosic feedback signal including curren sense funcion, open load in off sae and shor circui proecion. The power ransisor is buil by a N-channel verical power MOSFET wih charge pump. The inpus are ground referenced CMOS compaible. The device is monolihically inegraed in Smar SIPMOS echnology. 1.1 Block Diagram channel 1 VBB IN1 IS1 CLA inernal power supply ESD proecion logic load curren sense gae conrol & charge pump open load deecion emperaure sensor clamp for inducive load muli sep load curren limiaion OUT1 IN2 IS2 channel 2 conrol and proecion circui equivalen o channel 1 OUT2 GND Figure 1 Block Diagram Targe Daa Shee 5 V1.2, 2006-08-14
1.2 Terms Following figure shows all erms used in his arge daa shee. Overview V bb I bb I IN1 IN1 VBB V IN1 V IN2 V IS1 V IS2 I IN2 I IS1 I IS2 I CLA IN2 IS1 IS2 CLA GND OUT1 OUT2 I L1 I L2 V DS1 V OUT1 V DS2 V OUT2 V CLA I GND Figure 2 Terms Terms2ch.emf Targe Daa Shee 6 V1.2, 2006-08-14
Pin Configuraion 2 Pin Configuraion 2.1 Pin Assignmen (op view) GND 1 12 VBB IN1 2 11 OUT1 IS1 3 10 OUT1 IS2 4 9 OUT2 IN2 5 8 OUT2 VBB 6 7 CLA hea slug (VBB) Figure 3 Pin Configuraion PG-DSO-12-9 2.2 Pin Definiions and Funcions Pin Symbol I/O OD Funcion 2 IN1 I Inpu signal for channel 1 5 IN2 I Inpu signal for channel 2 3 IS1 O Diagnosis oupu signal channel 1 4 IS2 O Diagnosis oupu signal channel 2 7 CLA I Curren limi adjus inpu for channel 1&2 10,11 OUT1 1) O Proeced high-side power oupu channel 1 8, 9 OUT2 1) O Proeced high-side power oupu channel 2 1 GND - Ground connecion 6,12, hea slug VBB - Posiive power supply for logic supply as well as oupu power supply 1) All oupu pins of each channel have o be shored. Targe Daa Shee 7 V1.2, 2006-08-14
Elecrical Characerisics 3 Elecrical Characerisics 3.1 Maximum Raings Sresses above he ones lised here may cause permanen damage o he device. Exposure o maximum raing condiions for exended periods may affec device reliabiliy. T j = 25 C (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Tes min. max. Condiions Power Supply 3.1.1 Supply volage V bb 18 V 28 100 h 3.1.2 Curren hrough ground pin I GND -150 ma 2min 3.1.3 Supply volage for full shor circui proecion (single pulse) (T j = -40 C.. 150 C) V bb(sc) 0 20 V L = 8 µh R = 0.2 Ω 1) 3.1.4 Volage a power ransisor V DS 52 V 3.1.5 Supply Volage for Load Dump proecion V bb(ld) 40 53 Power Sages 3.1.6 Load curren I L I L(LIM) A 3.1.7 Maximum energy dissipaion E AS 130 mj single pulse V R I = 2 Ω 2) R L = 2.25 Ω R L = 6.8 Ω 3) 4) T j(0) = 150 C I L(0) = 6 A V bb =12V 3.1.8 Power dissipaion (DC) P o 1.4 W 5) T a = 85 C T j 150 C Logic Pins 3.1.9 Volage a inpu pin V IN -5-16 3.1.10 Curren hrough inpu pin I IN -2.0-8.0 19 V 2.0 ma 2min 2min Targe Daa Shee 8 V1.2, 2006-08-14
3.1.11 Volage a curren limi adjus pin 3.1.12 Curren hrough curren limi adjus pin min. V CLA -5-16 I CLA -2.0-8.0 Elecrical Characerisics T j = 25 C (unless oherwise specified) Pos. Parameer Symbol Limi Values max. Uni Tes Condiions 19 V 2.0 ma 3.1.13 Curren hrough sense pin I IS -5 10 ma Temperaures 3.1.14 Juncion emperaure T j -40 150 C 3.1.15 Dynamic emperaure increase T j 60 C while swiching 3.1.16 Sorage emperaure T sg -55 150 C 2min 2min ESD Suscepibiliy 3.1.17 ESD suscepibiliy HBM IN, CLA IS OUT V ESD -1-2 -4 1 2 4 kv according o EIA/JESD 22-A 114B 1) R and L describe he complee circui impedance including line, conac and generaor impedances 2) Load Dump is specified in ISO 7637, R I is he inernal resisance of he Load Dump pulse generaor 3) 4) 5) Curren limiaion is a proecion feaure. Operaion in curren limiaion is considered as ouside normal operaing range. Proecion feaures are no designed for coninuous repeiive operaion. Pulse shape represens inducive swich off: I L () = I L (0) * (1 - / peak ); 0 < < peak. Please see Figure 8 Device mouned on PCB (50 mm x 50 mm x 1.5 mm epoxy, FR4) wih 6 cm 2 copper heasinking area (one layer, 70 µm hick) for V bb connecion. PCB is verical wihou blown air. Targe Daa Shee 9 V1.2, 2006-08-14
Power Sages 4 Block Descripion and Elecrical Characerisics 4.1 Power Sages The power sages are buil by a N-channel verical power MOSFET (DMOS) wih charge pump. 4.1.1 Oupu On-Sae Resisance The on-sae resisance R DS(ON) depends on he supply volage as well as he juncion emperaure T j. Figure 4 shows ha dependencies for he ypical on-sae resisance. The behavior in reverse polariy mode is described in Secion 4.2.2. V bb = 13.5 V T j = 25 C R DS(ON) /mω 35 30 25 20 15 10-50 -25 0 25 50 75 100 125 150 T / C Figure 4 Typical On-Sae Resisance R DS(ON) /mω 140 120 100 80 60 40 20 0 5 10 15 20 25 V bb /V 4.1.2 Inpu Circui Figure 5 shows he inpu circui of he. There is an inegraed inpu resisor ha makes exernal componens obsolee. The curren sink o ground ensures ha he device swiches off in case of open inpu pin. The zener diode proecs he inpu circui agains ESD pulses. IN R IN I IN Figure 5 Inpu Circui (IN1 and IN2) GND Inpu.emf Targe Daa Shee 10 V1.2, 2006-08-14
Power Sages A high signal a he inpu pin causes he power DMOS o swich on wih a dedicaed slope, which is opimized in erms of EMC emission. IN ON OFF V OUT 90% 70% 30% dv / d OFF 40% 10% dv /d ON SwichOn.emf Figure 6 Swiching a Load (resisive) 4.1.3 Inducive Oupu Clamp When swiching off inducive loads wih high-side swiches, he volage V OUT drops below ground poenial, because he inducance inends o coninue driving he curren. V bb VBB I L GND OUT V OUT L, R L OupuClamp.em Figure 7 Oupu Clamp (OUT1 and OUT2) To preven desrucion of he device, here is a volage clamp mechanism implemened ha keeps ha negaive oupu volage a a cerain level (V OUT(CL) ). See Figure 7 and Figure 8 for deails. Neverheless, he maximum allowed load inducance is limied. Targe Daa Shee 11 V1.2, 2006-08-14
Power Sages V OUT V bb IN = 5V IN = 0V V OUT(CL) I L peak InduciveLoad.emf Figure 8 Swiching an Inducance Maximum Load Inducance While demagneizaion of inducive loads, energy has o be dissipaed in he BTS 5246-2L. This energy can be calculaed wih following equaion: E = ( V bb V OUT(CL) ) V OUT(CL) ---------------------- ln 1 R L R L I L ---------------------- V OUT(CL) + I L L ------ R L Following equaion simplifies under he assumpion of R L = 0: E = 1 2 --LI 2 L V bb 1 ---------------------- V OUT(CL) The energy, which is convered ino hea, is limied by he hermal design of he componen. See Figure 9 for he maximum allowed energy dissipaion. To be added afer characerizaion of firs samples Figure 9 Maximum energy dissipaion single pulse, T j,sar = 150 C Targe Daa Shee 12 V1.2, 2006-08-14
Power Sages 4.1.4 Elecrical Characerisics V bb = 9 V o 16 V, T j = -40 C o +150 C (unless oherwise specified) ypical values: V bb = 13.5 V, T j = 25 C Pos. Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. General 4.1.1 Operaing volage V bb 4.5 28 V V IN = HIGH R L = 12 Ω V DS < 0.5 V 4.1.2 Operaing curren one channel all channels 4.1.3 Sandby curren for whole device wih load Oupu characerisics 4.1.4 On-Sae resisance per channel 4.1.5 Oupu volage drop limiaion a small load currens 4.1.6 Nominal load curren per channel one channel acive wo channels acive ISO load curren per channel one channel acive wo channels acive I GND 1.6 3.2 I bb(off) 4 8 5 7.5 7.5 20 ma V IN = 5 V I L =I NOM µa V IN = 0 V V CLA = 0 V V OUT < V OUT(OL) T j = 25 C T j = 105 C 3) T j = 150 C R DS(ON) mω I L = 5 A 35 38 T j = 150 C V DS(NL) 40 mv I L = 0.5 A I L(nom) I L(ISO) 6 4.3 15 15 6,3 4,5 17 17 A T a = 85 C 1) 2) T j 150 C A T c = 85 C V DS = 0.5 V 2) 4.1.7 Oupu clamp V OUT(CL) -24-20 -17 V I L = 40 ma 4.1.8 Oupu leakage I L(OFF) 1.5 8 µa V IN = 0 V curren per channel Targe Daa Shee 13 V1.2, 2006-08-14
Thermal Resisance 4.1.9 Juncion o case R hjc 1.8 K/W 4.1.10 Juncion o ambien one channel on all channels on R hja 40 33 K/W 1) Inpu characerisics 4.1.11 Inpu resisance for pin IN R IN 2.0 3.5 5.5 kω 4.1.12 L-inpu level for pin IN V IN(L) -0.3 1.0 V 4.1.13 H-inpu level for pin IN V IN(H) 2.4 V 4.1.14 Hyseresis for pin IN V IN 0.5 V 3) 4.1.15 L-inpu curren for pin IN 4.1.16 H-inpu curren for pin IN Power Sages V bb = 9 V o 16 V, T j = -40 C o +150 C (unless oherwise specified) ypical values: V bb = 13.5 V, T j = 25 C Pos. Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. I IN(L) 3 40 µa V IN = 0.4 V I IN(H) 20 50 90 µa V IN = 5 V Timings 4.1.17 Turn-on ime o 90% V bb ON 90 250 µs R L = 12 Ω V bb = 13.5 V 4.1.18 Turn-off ime o 10% V bb OFF 100 250 µs R L = 12 Ω V bb = 13.5 V 4.1.19 slew rae 10% o 30% V bb dv/ d ON 0.1 0.25 0.45 V/µs R L = 12 Ω V bb = 13.5 V 4.1.20 slew rae 70% o 40% V bb -dv/ d OFF 0.1 0.25 0.45 V/µs R L = 12 Ω V bb = 13.5 V 1) Device mouned on PCB (50 mm x 50 mm x 1.5 mm epoxy, FR4) wih 6 cm 2 copper heasinking area (one layer, 70 µm hick) for V bb connecion. PCB is verical wihou blown air. 2) No subjec o producion es, parameers are calculaed from R DS(ON) and R h 3) No subjec o producion es, specified by design Noe: Characerisics show he deviaion of parameer a he given supply volage and juncion emperaure. Typical values show he ypical parameers expeced from manufacuring. Targe Daa Shee 14 V1.2, 2006-08-14
4.2 Proecion Funcions Proecion Funcions The device provides embedded proecive funcions. Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he arge daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are neiher designed for coninuous nor repeiive operaion. 4.2.1 Over Load Proecion The load curren I OUT is limied by he device iself in case of over load or shor circui o ground. There are wo seps of curren limiaion. They can be seleced by he CLA pin, bu are addiionally seleced auomaically depending on he volage V DS across he power DMOS. Please noe ha he volage a he OUT pin is V bb - V DS. Please refer o following figure for deails. 40 I L CLA = L 30 20 10 CLA = H 5 10 15 20 25 30 V DS CurrenLimiaion.emf Figure 10 Curren Limiaion (minimum values) Curren limiaion is realized by increasing he resisance of he device which leads o rapid emperaure rise inside. A emperaure sensor for each channel causes an overheaed channel o swich off o preven desrucion. Afer cooling down wih hermal hyseresis, he channel swiches on again. Please refer o Figure 11 for complee picure of he behavior, when.figure 12 skeches a zoom of he firs even and he die emperaure increase and oggling. IN I L I L(LIM) I L(SCr) V IS(faul) I IS OverLoad.emf Figure 11 Shu Down by Over Temperaure Targe Daa Shee 15 V1.2, 2006-08-14
Proecion Funcions The CLA pin circui is similar o he inpu pin. Please refer o Figure 5 for deails. Please noe ha he hresholds for high and low sae differ beween IN and CLA. IN I L I L(LIM) I L(SCr) Tj (SC) T j (SC) Tj OFF(SC) 125 C For beer undersanding, he drawing doesn' respec he scale Thermal mechanism.emf Figure 12 Iniial shor circui shu down. 4.2.2 Reverse Polariy Proecion In case of reverse polariy, he inrinsic body diode causes power dissipaion. Use following fomular for esimaion of oal power dissipaion P diss(rev) in reverse polariy mode. P diss(rev) The reverse curren hrough he power ransisors has o be limied by he conneced loads. The reverse curren hrough he ground connecion has o be limied eiher by a resisor or by a pair of resisor and diode. The curren hrough sense pins IS1 and IS2 has o be limied (please refer o maximum raings on Page 8). The emperaure proecion is no acive during reverse polariy. 4.2.3 Over Volage Proecion = all channels ( V DS(rev) I L ) In addiion o he oupu clamp for inducive loads as described in Secion 4.1.3, here is a clamp mechanism for over volage proecion. The curren hrough he ground connecion has o be limied e.g. by a resisor. Targe Daa Shee 16 V1.2, 2006-08-14
Proecion Funcions As shown in Figure 13, in case of supply volages greaer han V bb(az), he power ransisor opens and he volage across logic par is clamped. As a resul, he ground poenial rises o V bb - V bb(az). Due o he ESD zener diodes, he poenial a pin IN1, IN2 and CLA rises almos o ha poenial, depending on he impedance of he conneced circuiry. IN R IN ZD AZ VBB IS CLA R CLA logic ZD ESD GND OUT V OUT R GND Figure 13 Over Volage Proecion OverVolage.emf 4.2.4 Loss of Ground Proecion In case of complee loss of he device ground connecions, bu conneced load ground, he securely changes o or says in off sae. Targe Daa Shee 17 V1.2, 2006-08-14
4.2.5 Elecrical Characerisics Proecion Funcions V bb = 9 V o 16 V, T j = -40 C o +150 C (unless oherwise specified) ypical values: V bb = 13.5 V, T j = 25 C Pos. Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. Over Load Proecion 4.2.1 Shor circui curren limiaion. 4.2.2 Repeiive shor circui curren limiaion 4.2.3 Iniial shor circui shu down ime I L(LIM) 40 7 50 11 I L(SCr) 40 7 OFF(SC) 0.8 4 4.2.4 Thermal shu down emperaure T j(sc) 150 170 C 4.2.5 Thermal hyseresis T j 10 K 2) 60 14 A V DS > 5V CLA = 0 V CLA = 5 V 1) A T j = T j(sc) 1) 2) CLA = 0 V CLA = 5 V ms T jsar = 25 C 2) CLA = 0 V CLA = 5 V See Figure 12 2) Reverse Baery 4.2.6 Drain-Source diode volage (V OUT >V bb ) Over Volage 4.2.7 Over volage proecion Loss of GND 4.2.8 Oupu curren while GND disconneced Curren Limi Adjus (CLA) 4.2.9 Inpu resisance for pin CLA -V DS(rev) 900 mv I L = -5 A T j =150 C V bb(az) 41 47 52 V I bb = 2 ma I L(GND) 2 ma I IN = 0 I GND = 0 I IS = 0 R CLA 2.0 3.5 5.5 kω 2) 3) Targe Daa Shee 18 V1.2, 2006-08-14
V bb = 9 V o 16 V, T j = -40 C o +150 C (unless oherwise specified) ypical values: V bb = 13.5 V, T j = 25 C Proecion Funcions Pos. Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. 4.2.10 L-inpu level for pin V CLA(L) -0.3 2.0 V CLA 4.2.11 H-inpu level for pin CLA V CLA(H) 4.0 V Targe Daa Shee 19 V1.2, 2006-08-14
V bb = 9 V o 16 V, T j = -40 C o +150 C (unless oherwise specified) ypical values: V bb = 13.5 V, T j = 25 C Proecion Funcions Pos. Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. 4.2.12 L-inpu curren for pin I CLA(L) 3 40 µa V CLA = 0.4 V CLA 4.2.13 H-inpu curren for pin CLA I CLA(H) 20 50 90 µa V CLA = 5 V 1) 2) 3) Mus be limied o 2mn. No subjec o producion es, specified by design no connecion a hese pins Targe Daa Shee 20 V1.2, 2006-08-14
Diagnosis 4.3 Diagnosis For diagnosis purpose, he provides an InelliSense signal a pins IS1 and IS2. This means in deail, he curren sense signal I IS, a proporional signal o he load curren (raio k ILIS = I L / I IS ), is provided as long as no failure mode (see Table 1) occurs. In case of a failure mode, he volage V IS(faul) is fed o he diagnosis pin. S OL VBB R OL IN1 gae conrol I IS1 R IN1 R lim IS1 over emperaure OUT1 over load µc 0 open load @ off 1 V IS(faul) V OUT(OL) channel 1 IN2 gae conrol R IN2 R lim IS2 diagnosis I IS2 R IS1 R IS2 GND channel 2 OUT2 load Sense.emf Figure 14 Block Diagram: Diagnosis Table 1 Truh Table Operaion Mode Inpu Level Oupu Level Diagnosic Oupu Normal Operaion (OFF) L Z Z Shor Circui o GND Z Z Over Temperaure Z Z Shor Circui o V bb V bb V IS = V IS(faul) Open Load < V OUT(OL) Z > V OUT(OL) V IS = V IS(faul) Targe Daa Shee 21 V1.2, 2006-08-14
Diagnosis Table 1 Truh Table Operaion Mode Inpu Level Oupu Level Diagnosic Oupu Normal Operaion (ON) H ~V bb I IS = I L / k ILIS Curren Limiaion < V bb V IS = V IS(faul) Shor Circui o GND ~GND V IS = V IS(faul) Over Temperaure Z V IS = V IS(faul) Shor Circui o V bb V bb I IS < I L / k ILIS Open Load ~V bb Z L = Low Level, H = High Level, Z = high impedance, poenial depends on exernal circui 4.3.1 ON-Sae Diagnosis The sandard diagnosis signal is a curren sense signal proporional o he load curren. The accuracy of he raio (k ILIS = I L / I IS ) depends on he emperaure. Please refer o Figure 15 for deails. Usually a resisor R IS is conneced o he curren sense pin. I is recommended o use sense resisors R IS > 500 Ω. A ypical value is 4.7 kω 7500 7000 6500 6000 k ILIS 5500 5000 4500 4000 0 1 2 3 4 5 6 I L /A Figure 15 Curren sense raio k ILIS 1) 1) The curves show he behavior based on characerizaion daa. The marked poins are guaraneed in his Targe Daa Shee in Secion 4.3.3 (Posiion 4.3.7). Targe Daa Shee 22 V1.2, 2006-08-14
Diagnosis Deails abou imings beween he diagnosis signal I IS and he oupu volgage V OUT and he load curren I L in ON-sae can be found in Figure 16. IN V OUT OFF ON ON normal operaion over load (curren limiaion) I L I IS sis(on) sis(lc) sis(lc) V IS(faul) / R S Figure 16 Timing of Diagnosis Signal in ON-sae SwichOn.emf In case of over-curren as well as over-emperaure, he volage V IS(faul) is fed o he diagnosis pins as long as he according inpu pin is high. This means, even when he device keeps swiching on and off in over-load condiion, he failure signal is consanly available. Please refer o Figure 17 for deails. T j over load (curren limiaion & hermal oggling) normal operaion T j(sc) I L I IS sis( LC) his(otr) Figure 17 V IS(faul) / R S Timing of Diagnosis Signal in Over Load Condiion OverTemp.emf Targe Daa Shee 23 V1.2, 2006-08-14
4.3.2 OFF-Sae Diagnosis Diagnosis Deails abou imings beween he diagnosis signal I IS and he oupu volgage V OUT and he load curren I L in OFF-sae can be found in Figure 18. IN ON OFF V OUT Open Load, pull-up resisor acive d(faul) pull-up resisor inacive s(faul) I IS V IS(faul) / R S Figure 18 Timing of Diagnosis Signal in OFF-sae SwichOff.emf For open load diagnosis in off-sae an exernal oupu pull-up resisor (R OL ) is recommended. For caluclaion of pull-up resisor, he leakage currens and he open load hreshold volage V OUT(OL) has o be aken ino accoun. V R bb(min) V OUT(OL,max) OL = ---------------------------------------------------------- I leakage I leakage defines he leakage curren in he complee sysem including I L(OL) and exernal leakages e.g. due o humidiy. V bb(min) is he minimum supply volage a which he open load diagnosis in off-sae mus be ensured. To reduce he sand-by curren of he sysem, an open load resisor swich (S OL ) is recommended. The sand-by curren of he is minimized, when boh inpu pins (IN1 and IN2) are on low level or lef open and V OUT < V OUT(OL). In case of open load in off sae (V OUT > V OUT(OL) and V IN = 0 V), he faul volage V IS(faul) drives a curren hrough he sense resisor, which causes an increase in supply curren. To reduce he sand-by curren o a minimum, he open load condiion needs o be suppressed. The resisors R lim are recommended o limi he curren hrough he sense pins IS1 and IS2 in case of reverse polariy and over volage. Targe Daa Shee 24 V1.2, 2006-08-14
4.3.3 Elecrical Characerisics Diagnosis V bb = 9 V o 16 V, T j = -40 C o +150 C (unless oherwise specified) ypical values: V bb = 13.5 V, T j = 25 C Pos. Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. Open Load a OFF sae 4.3.1 Open load deecion hreshold volage 4.3.2 Leakage curren ino OUT 4.3.3 Sense signal in case of open load 4.3.4 Sense signal curren limiaion 4.3.5 Sense signal invalid afer negaive inpu slope 4.3.6 Faul signal seling ime V OUT(OL) 2.0 3.2 4.4 V -I L(OL) 1 µa V OUT = 5 V V IS(faul) 5.0 6.2 8 V V IN = 0 V V OUT > V OUT(OL) I IS = 1 ma I IS(LIM) 4 ma V IS = 0 V V IN = 0 V V OUT > V OUT(OL) d(faul) 1.2 ms V IN = 5V o 0V V OUT > V OUT(OL) I IS = 1mA s(faul) 200 µs V IN = 0 V 1) V OUT = 0 V o > V OUT(OL) I IS = 1 ma Load Curren Sense 4.3.7 Curren sense raio k ILIS V IN = 5 V; I L = 0.5 A I L = 3.0 A I L = 6.0 A 4.3.8 Curren sense volage limiaion 4.3.9 Curren sense leakage/offse curren 4.3.10 Curren sense seling ime o I IS saic ±10% afer posiive inpu slope 4450 4750 4900 5800 5400 5350 6960 6050 5800 T j = 150 C; T j = -40 C V IS(LIM) 5.4 6.5 7.5 V I L = 5 A I IS = 0 I IS(LH) 5 µa V IN = 5 V I L = 0 A sis(on) 400 µs V IN = 0V o 5V I L = 5 A 1) Targe Daa Shee 25 V1.2, 2006-08-14
4.3.11 Curren sense seling ime o I IS saic ±10% afer change of load curren 4.3.12 Faul signal hold ime afer hermal resar Diagnosis V bb = 9 V o 16 V, T j = -40 C o +150 C (unless oherwise specified) ypical values: V bb = 13.5 V, T j = 25 C Pos. Parameer Symbol Limi Values Uni Tes Condiions 1) No subjec o producion es, specified by design min. yp. max. sis(lc) 300 µs V IN = 5 V I L = 3A o 5A 1) his(otr) 1.2 ms 1) See Figure 17 Targe Daa Shee 26 V1.2, 2006-08-14
5 Package Oulines Package Oulines PG-DSO-12-9 (Plasic Dual Small Ouline Package) A 6.4 8 ±0.1 1) 7.5 ±0.1 1) 0.1±0.05 3) 0.8 0 +0.1 2) 2.35 ±0.1 0.1 1 0.1 C 12x Seaing Plane 5 x 1 = 5 (1.55) 2.6 MAX. C B 8 +0.075 0.25-0.035 0.7 ±0.15 (0.2) 5 ±3 0.4 +0.13 12 5.1 ±0.1 0.25 M C AB 7 1.6 ±0.1 (1.8) (4.4) 10.3 ±0.3 0.25 B ø0.8 x 0.1-0.05 Deph 4) 1 6 7.8 ±0.1 (Heaslug) 4.2 ±0.1 1) 2) 3) 4) Does no include plasic or meal prorusion of 0.15 max. per side Sand OFF Sand OUT Pin 1 Index Marking; Polish finish All package corners max. R 0.25 To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions he device is available as a green produc. Green producs are RoHS-Complian (i.e Pb-free finish on leads and suiable for Pb-free soldering according o IPC/ JEDEC J-STD-020). Please specify he package needed (e.g. green package) when placing an order. You can find all of our packages, sors of packing and ohers in our Infineon Inerne Page Producs : hp://www.infineon.com/producs. SMD = Surface Mouned Device Dimensions in mm Targe Daa Shee 27 V1.2, 2006-08-14
Revision Hisory 6 Revision Hisory Version Dae Changes V1.2 06-08-14 Creaion of he arge daashee of he BTS5246-2L Dela shee o he grey BTS5246L daashee, version 1.2 of July he 26h 2006. Parameer 3.1.6 changed o 130mJ wih 12V baery Parameer 4.1.7 changed o -24V min, -17V max. Se he Figure 9 o bd. Parameer 4.2.7 : Change in he es condiion o 2mA. Targe Daa Shee 28 V1.2, 2006-08-14
Ediion 2006-08-14 Published by Infineon Technologies AG, S.-Marin-Srasse 53, D-81541 München, Germany Infineon Technologies AG 8/22/06. All Righs Reserved. Aenion please! The informaion herein is given o describe cerain componens and shall no be considered as warraned characerisics. Terms of delivery and righs o echnical change reserved. We hereby disclaim any and all warranies, including bu no limied o warranies of non-infringemen, regarding circuis, descripions and chars saed herein. Infineon Technologies is an approved CECC manufacurer. Informaion For furher informaion on echnology, delivery erms and condiions and prices please conac your neares Infineon Technologies Office in Germany or our Infineon Technologies Represenaives worldwide. Warnings Due o echnical requiremens componens may conain dangerous subsances. For informaion on he ypes in quesion please conac your neares Infineon Technologies Office. Infineon Technologies Componens may only be used in life-suppor devices or sysems wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem, or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body, or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered. Targe Daa Shee 29 V1.2, 2006-08-14
hp://www.infineon.com Published by Infineon Technologies AG