Preprint typeset in JINST style - HYPER VERSION First Results of the Belle II Silicon Vertex Detector Readout System M.Friedl a, T.Bergauer a, F.Buchsteiner a, G.Casarosa b, F.Forti b, K.Hara c, T.Higuchi d, C.Irmler a, R.Itoh c, T.Konno e, J.Lettenbichler a, Z.-A.Liu f, K.R.Nakamura c, M.Nakao c, Z.Natkaniec g, W.Ostrowicz g, E.Paoloni b, T.Schlüter h, M.Schnell i, S.Y.Suzuki c, R.Thalmeier a, T.Tsuboyama c, S.Yamada c, H.Yin a a HEPHY Vienna Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, A-1050 Vienna, Austria b INFN and University of Pisa, L.go B. Pontecorvo 3, 56127 Pisa, Italy c KEK, 1-1 Oho, Tsukuba, Ibaraki 305-0801, Japan d Kavli Institute for Physics and Mathematics of the Universe (WPI), University of Tokyo, 5-1-5 Kashiwanoha, Kashiwa, Chiba 277-8583, Japan e Tokyo Metropolitan University, Department of Physics, 1-1 Minami-Oosawa Hachioji-shi, Tokyo 192-0397, Japan f Institute of High Energy Physics, Experimental Physics Center, Yuquan Road 19(2) Beijing 100049, China g Institute of Nuclear Physics, Division of Particle Physics and Astrophysics, ul. Radzikowskiego 152, 31 342 Krakow, Poland h LMU Munich, Faculty of Physics, Geschwister-Scholl-Platz 1, 80539 Munich, Germany i University of Bonn, Department of Physics and Astronomy, Nussallee 12, 53115 Bonn, Germany E-mail: markus.friedl@oeaw.ac.at ABSTRACT: At the heart of the Belle II experiment at KEK (Japan), there will be a Vertex Detector (VXD) composed of 2 layers of DEPFET pixels (PXD) and 4 layers of double-sided silicon strip detectors (SVD). The latter use the APV25 front-end chip originally developed for CMS which is reading out the inner part of the SVD sensors through the Origami chip-on-sensor concept, including a state-of-the-art two-phase CO 2 cooling. The whole system (including the full DAQ chain) was successfully tested in a beam at DESY in January 2014 and first results are presented here. KEYWORDS: Particle tracking detectors (Solid-state detectors); Data acquisition concepts; Electronic detector readout concepts (solid-state); Analysis and statistical methods. Corresponding author.
Contents 1. Introduction 1 2. Readout Chain 2 3. DESY Beam Test 2014 5 3.1 Overview 5 3.2 Results 5 3.3 Lessons Learned 6 4. Summary and Outlook 8 1. Introduction Belle II [1] will be the only experiment at the SuperKEKB machine [2] colliding electrons and positrons at the KEK laboratory (Tsukuba, Japan). The beam energies will be asymmetric to generate a forward boost which is essential to measure the properties of B and B mesons that are generated mostly at the ϒ(4S) resonance of 10.58GeV. In comparison to the LHC energy, that is three orders of magnitude lower, so particular care has to be taken on the detector side in order to avoid excessive multiple scattering. Belle II and SuperKEKB are presently under construction and physics data taking will start in 2017. The Vertex Detector (VXD) of Belle II will consist of two parts: two cylindrical barrel layers of Pixel Detector (PXD) will surround the beam pipe at radii of 14 and 22mm. The PXD is manufactured in the DEPFET technology [3], a promising monolithic silicon pixel detector concept. Outside of the PXD, there will be four layers of double-sided silicon detectors (DSSDs) called Silicon Vertex Detector (SVD; see figure 1), located at radii of 38, 80, 104 and 135mm, respectively. In order to avoid confusion with the PXD, the full VXD employs a consecutive layer numbering where 1 and 2 denote the PXD and 3 to 6 are for the SVD. While layer 3 is purely cylindrical (albeit composed of planar sensors with a windmill-like overlap, thus not strictly cylindrical), the outer three layers feature a slanted (lantern-shaped) part in the forward side. The sensitive polar angle range of Belle II was defined to be 17...150 (its asymmetry is related to the forward boost mentioned above) and is fully covered by this barrel/slanted design. The smallest unit of the SVD is called ladder and is composed of two to five DSSDs (depending on the layer) with mechanical support ribs and the front-end readout electronics. The two sensors in layer 3 are conventionally read out using PCB boards with the readout chips at the edges of the sensors (and outside of the sensitive volume), connected to the strips by pitch adapters. The same scheme is also applied to the first and last sensors of the layer 4 to 6 ladders. For the inner DSSDs of those layers, however, we use the Origami chip-on-sensor concept [4], where all the 1
Figure 1. Rendering of the SVD with only half of the ladders mounted in each layer, thus revealing the support structure. front-end chips are aligned on top of the sensor and connected to both upper and lower side strips by short pitch adapters, the latter being wrapped around the edge of the sensor. Thanks to the aligned chips, a single thin cooling pipe can be used for CO2 cooling. Further information about the geometry, the sensors and the various components of the readout chain can be found in [5]. 2. Readout Chain A schematic view of the electronic readout chain of the Belle II SVD is shown in figure 2. The primary data flow is from left to right, starting at the front-end detector modules with the APV25 [6] readout chips. 2.5 m of cables connect the front-end to the Junction box which contains connectors to bridge front-end and back-end cables. Secondly, it houses DC/DC converters [7] which are made by CERN for use in radiative environment and magnetic field. Both LV and HV power are delivered directly from the power supply units (which are placed in a different location from the back-end readout electronics) to the Junction box, where the floating low voltages are tied to the high voltage bias potentials, i.e. the local ground of the readout chips of the p-side is connected to the (negative) p-side bias voltage and similarly for the n-side. 2
Figure 2. Belle II SVD readout chain. Consequently, the Belle II SVD powering scheme is completely floating, which means that the amplifier chips are operating at the bias potentials. Figure 3 shows the complete picture of the powering scheme, including the DC/DC converters and the sensors. As mentioned, the n- side bias voltage is tied to the local ground of the converters in the Junction box. In case of the p-side, this is also the default setting, but optionally a small separation voltage can be inserted between p-side bias and local ground. The purpose of this offset is to mitigate potentially harmful pinholes. It is known that in our configuration the APV25 can tolerate four pinholes (among its 128 input channels) but the whole chip becomes impaired above because of a DC current flow into the chip. [8] This problem can only occur on the p-side and can be cured (or at least improved) by shifting the voltage levels of the chip with respect to the sensor, and that is the reason for the optional separation voltage. The FADC boards are the central units which handle all the communication between front-end and high-level back-end. One of their jobs is to translate both the analog signals sent from the APV25 chips as well as the digital control signals for the front-end. This is done using customized capacitor circuits for the analog voltages and commercial digital isolators for the digital signals. The ground-related analog signals are then digitized and sent to a powerful FPGA (Altera Stratix IV GX), which performs some digital data processing in parallel for all the 48 input channels (each being fed by one APV25 chip) of a module. Initially, there is an 8-stage Finite Impulse Response (FIR) filter [9]. The purpose of this filter is to remove the effects of signal distortions arising from the nonlinear frequency-dependent attenuation of the cables and also to eliminate reflections that appear due to non-perfect termination. Thereafter, the strip data are extracted from data frames sent by the APV25 chips and pro- 3
Junction Box 1.25_N Power Supplies Detector R_AC N_SIDE_HYBRID +1.25_HV_N +2.50_HV_N 1.25_N DCDC VOUT REF 2.50_N _RET LVPS_N 10 V C_AC APV25 GND_HV_N 2.50_N DCDC VOUT REF R_POLY 10 MOhm HV_N_BIAS HV_N_RET GND_N HV_N_BIAS HV_N_RET HV_N_BIAS HV_N_RET HV_N 20-100 V Sensor ILeakage R_POLY 10 MOhm R_AC C_AC P_SIDE_HYBRID APV25 HV_P_RET HV_P_BIAS +1.25_HV_P +2.50_HV_P GND_HV_P HV_P_RET HV_P_BIAS 1.25_P 2.50_P 1.25_P DCDC VOUT REF 2.50_P DCDC VOUT REF HV_P_RET HV_P_BIAS _RET HV_P 20-100 V LVPS_P 10 V GND_P V_SEP V_SEP_RET V_SEP 10 V Figure 3. Power distribution scheme of the Belle II SVD. cessed in the usual way: pedestal subtraction, two-pass common mode correction, zero suppression. Finally, we plan to also perform a hit time finding to determine the particle timing with a precision of a few nanoseconds, as shown in numerical fits performed offline, but this functionality is not yet implemented in the firmware. Recent simulations indicate that a neuronal network is capable of performing this task with excellent precision, and in contrast to numerical fitting it can easily be implemented inside an FPGA. A Finesse Transmitter Board (FTB) will be connected to the rear side of each FADC module and acts as an electrical-to-optical interface with two parallel outputs: one sends the data to the common DAQ, where they are further processed in computer farms. The other output sends a copy to the Data Concentrator (DATCON) which is part of the PXD and performs online tracking to find regions of interest (RoI) on the pixel detector planes in order to reduce the amount of data from that subdetector. Due to its nature, the PXD has a huge number of channels about eight million pixels in a very small volume, whereas the SVD features approximately 224,000 strips. Consequently, the latter has a finer timing resolution and thus online tracking using the SVD hits actually helps to reduce the PXD occupancy by at least a factor of ten and thus significantly reduce the overall PXD data bandwidth. PXD and SVD together will make a very powerful device (the VXD): the pixel detector delivers excellent spatial resolution and true 2D hit points, while the SVD provides precise timing information and track points between the PXD and the Central Drift Chamber (CDC). 4
Figure 4. Reconstructed particle tracks in the DESY beam test. Left: Straight track through the four SVD planes (no magnetic field). Right: Bent track through the SVD with projected Regions of Interest (RoI) in the PXD and virtual hit points in the telescope planes (1T magnetic field). 3. DESY Beam Test 2014 3.1 Overview In January 2014, three subsystems of Belle II were put together for the first time: Pixel Detector (PXD), Silicon Vertex Detector (SVD) and Data Acquisition (DAQ). This was done in an electron beam at DESY (Hamburg, Germany) with an energy range between 2 and 6GeV, similar to the Belle II environment. Moreover, a superconducting solenoid, providing a magnetic field of up to 1T, was used to bend the tracks in the same way as in Belle II. In order to test a representative part of the detector, it was decided to model a sector of the VXD with the real geometry, i.e. the final sensors and the correct distances between layers. Unfortunately, only one PXD sensor was available, but four layers of SVD were tested in the beam as planned. The pixel sensor and the four DSSDs were placed at their actual radii from a purely virtual vertex along the beam axis. A so-called small rectangular sensor was used for L3, and the large rectangular type was used for L4, L5 and L6 in the Origami configuration. The Belle II detector stack was put in a sealed and light-tight box which was flushed with dry gas to allow CO 2 cooling at temperatures below the ambient dew point. Three layers of the EUDET reference telescope [10] were placed upstream of the devices under test, and another 3 layers downstream. Finally, scintillator triggers in the very front and rear completed the setup. The principal geometry as well as a straight track (without magnetic field) and a bent one (with magnetic field) are shown in figure 4. Figure 5 shows photos from the actual setup at DESY. As mentioned before, the front-end detector stack was located inside the magnet; the Junction box was mounted on the side of the magnet, while readout electronics, power supplies and the CO 2 cooling plant were located in an adjacent room. It is noteworthy to say that all the tested components from the front-end sensors and amplifiers to the DAQ hard- and software are final prototypes, i.e. apart from minor bugfixes they will be reproduced in larger quantities and installed in the Belle II experiment. 3.2 Results Typical standard distributions for L6 are shown in figure 6. The average cluster width is about 1.7 for both p- (pitch = 75 µm) and n-sides (pitch = 240 µm). The hit map clearly reveals the centered 5
Figure 5. Photos of the DESY beam test setup. Bottom left: front-end detector modules (L3 sensor is exposed, L4 detector module is partly visible). Top left: Junction box located 2.5 m from the front-end. Right: Rack with HV/LV power supplies (center), control PC (bottom) and FADC crate (top). beam spot, and it shows a few noisy strips, but no obvious difference between clusters of different 1 width. This is naturally different for the cluster signal-to-noise, which includes a factor of clwid with equal RMS noise for each strip. On top of that, the n-side with its intermediate p-stops is less efficient than the p-side when it comes to charge sharing. High cluster widths are typically associated with highly energetic delta electrons, and thus also yield a higher signal than the typical minimum ionizing particle. This correlation between pulse height and cluster width is the reason why the distribution for high cluster widths has a most probable value higher than for single-strip hits and it is wider. Additional results, such as a hit efficiency above 99%, as well as trigger dead time calculations and how to minimize them, can be found in [11]. 3.3 Lessons Learned This was the first time that the three subsystems (PXD, SVD, DAQ) were integrated and successfully operated together, which was the primary aim of the enterprise. It was quite hard work to 6
Figure 6. Distributions from a typical run for L6 p- (left) and n-sides (right): Cluster width (top), hit map (center) and signal-to-noise (bottom). The latter two distributions are drawn in different colors depending on the cluster width. establish all the communications, and in fact this task was already started in December 2013, certainly not too early. Still, too little time was available to study system aspects that only appear once the subsystems are brought together. In particular, a noise problem appeared in the L3 of the SVD which was suspected to be caused by the nearby PXD layer, but further study is needed. As such investigations can be done without beam, the next DESY beam test (planned for late 2015) will include extra time 7
in the lab before actually moving the (hopefully then well understood) setup into the beam. At that time, we will use final ladders for each layer and the electronic modules of the final readout system. 4. Summary and Outlook Three subsystems Pixel Detector (PXD), Silicon Vertex Detector (SVD) and Data Acquisition (DAQ) were brought together for the first time in the January 2014 beam test at DESY. Its aim to operate these systems together was fully achieved and data was taken with CO 2 cooling as well as with a magnetic field. Apart from some minor bugfixes, the entire SVD hardware used in the beam test was final and thus has proved to be ready for series production. System aspects like mutual influence of neighboring devices need to be studied in more detail and therefore, the next beam test in late 2015 will have dedicated lab test time before moving the setup into the beam. References [1] Z.Doležal, S.Uno (editors), Belle II Technical Design Report, KEK Report 2010-1, arxiv:1011.0352 [2] Y.Ohnishi et al., Accelerator design at SuperKEKB, Prog. Theor. Exp. Phys. (2013) 03A011 [3] S.Rummel, L.Andricek, The DEPFET active pixel sensor for vertexing at ILC and Super KEKB, Nucl. Instr. and Meth. A 623 (2010) 189 191 [4] M.Friedl et al., Belle II Silicon Vertex Detector, Proceedings of Science (Vertex2011) 022 [5] M.Friedl et al., The Belle II Silicon Vertex Detector Readout Chain, JINST 8 C02037 [6] M.French et al., Design and results from the APV25, a deep sub-micron CMOS front-end chip for the CMS tracker, Nucl. Instr. and Meth. A 466 (2001) 359 365 [7] F.Faccio et al., FEAST2: a Production Grade 10W Radiation Tolerant DC/DC Converter, JINST, this volume [8] M.Raymond, Hips and pinhole effects on APV25, CMS Week, December 2001, http://www.hep.ph.ic.ac.uk/ dmray/pptfiles/cmshipstalk.ppt [9] C.Irmler et al., Efficient Signal Conditioning by an FIR Filter for Analog Signal Transmission over Long Lines, JINST, 7 C01082 [10] I.Rubinskiy, An EUDET/AIDA Pixel Beam Telescope for Detector Development, Physics Procedia 37 (2012) 923 931 [11] K.Nakamura, Development of a Data Acquisition System for the Belle II Silicon Vertex Detector, Proceedings of Science, TIPP 2014 conference, in press 8