Session 3: Solid State Devices. Silicon on Insulator

Similar documents
Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI

Lecture #29. Moore s Law

Silicon on Insulator (SOI) Spring 2018 EE 532 Tao Chen

2.8 - CMOS TECHNOLOGY

Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02

FinFET vs. FD-SOI Key Advantages & Disadvantages

Alternatives to standard MOSFETs. What problems are we really trying to solve?

FinFET-based Design for Robust Nanoscale SRAM

Topic 3. CMOS Fabrication Process

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1

EECS130 Integrated Circuit Devices

A perspective on low-power, low-voltage supervisory circuits implemented with SOI technology.

Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018

Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007

420 Intro to VLSI Design

INTRODUCTION TO MOS TECHNOLOGY

MOSFET & IC Basics - GATE Problems (Part - I)

Chapter 2 : Semiconductor Materials & Devices (II) Feb

FUNDAMENTALS OF MODERN VLSI DEVICES

PHYSICS OF SEMICONDUCTOR DEVICES

Semiconductor Devices

Fundamentals of Power Semiconductor Devices

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.

Semiconductor Physics and Devices

In this lecture we will begin a new topic namely the Metal-Oxide-Semiconductor Field Effect Transistor.

TID Effect in SOI Technology

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.

Design cycle for MEMS

Power MOSFET Zheng Yang (ERF 3017,

SPECIAL REPORT SOI Wafer Technology for CMOS ICs

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

MOSFET short channel effects

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1

Sub-micron technology IC fabrication process trends SOI technology. Development of CMOS technology. Technology problems due to scaling

ADVANCED MATERIALS AND PROCESSES FOR NANOMETER-SCALE FINFETS

International Journal of Scientific & Engineering Research, Volume 6, Issue 2, February-2015 ISSN

Basic Fabrication Steps

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics

Semiconductor Devices

I E I C since I B is very small

CMOS Technology. 1. Why CMOS 2. Qualitative MOSFET model 3. Building a MOSFET 4. CMOS logic gates. Handouts: Lecture Slides. metal ndiff.

Performance investigations of novel dual-material gate (DMG) MOSFET with dielectric pockets (DP)

IOLTS th IEEE International On-Line Testing Symposium

SRM INSTITUTE OF SCIENCE AND TECHNOLOGY (DEEMED UNIVERSITY)

6. LDD Design Tradeoffs on Latch-Up and Degradation in SOI MOSFET

LSI ON GLASS SUBSTRATES

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

A Review of Low-Power VLSI Technology Developments

Notes. (Subject Code: 7EC5)

+1 (479)

ECE 340 Lecture 37 : Metal- Insulator-Semiconductor FET Class Outline:

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families

Evaluation of STI degradation using temperature dependence of leakage current in parasitic STI MOSFET

Davinci. Semiconductor Device Simulaion in 3D SYSTEMS PRODUCTS LOGICAL PRODUCTS PHYSICAL IMPLEMENTATION SIMULATION AND ANALYSIS LIBRARIES TCAD

Solid State Devices- Part- II. Module- IV

EE E6930 Advanced Digital Integrated Circuits. Spring, 2002 Lecture 12. SOI Devices and Circuits

UNIT-VI FIELD EFFECT TRANSISTOR. 1. Explain about the Field Effect Transistor and also mention types of FET s.

Chapter 3 Basics Semiconductor Devices and Processing

CHAPTER 3 TWO DIMENSIONAL ANALYTICAL MODELING FOR THRESHOLD VOLTAGE

45nm Bulk CMOS Within-Die Variations. Courtesy of C. Spanos (UC Berkeley) Lecture 11. Process-induced Variability I: Random

ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations

Fabrication, Corner, Layout, Matching, & etc.

3-D Modelling of the Novel Nanoscale Screen-Grid Field Effect Transistor (SGFET)

Integrated Circuits: FABRICATION & CHARACTERISTICS - 4. Riju C Issac

Basic Electronics. Introductory Lecture Course for. Technology and Instrumentation in Particle Physics Chicago, Illinois June 9-14, 2011

VLSI Design. Introduction

UNIT 3: FIELD EFFECT TRANSISTORS

VLSI Design. Introduction

Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness

3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013

Session 10: Solid State Physics MOSFET

Power Semiconductor Devices

Three Terminal Devices

Device Technologies. Yau - 1

EECS130 Integrated Circuit Devices

Variation-Aware Design for Nanometer Generation LSI

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs

Device design methodology to optimize low-frequency Noise in advanced SOI CMOS technology

(Refer Slide Time: 02:05)

FinFET Devices and Technologies

Newer process technology (since 1999) includes :

value of W max for the device. The at band voltage is -0.9 V. Problem 5: An Al-gate n-channel MOS capacitor has a doping of N a = cm ;3. The oxi

Index. Cambridge University Press Fundamentals of Modern VLSI Devices: Second Edition Yuan Taur and Tak H. Ning.

Investigation and Modelling of the Floating Body Effects and Surface Recombination on SOS MOSFETs

INTRODUCTION: Basic operating principle of a MOSFET:

DesignofaRad-HardLibraryof DigitalCellsforSpaceApplications

NEW INSIGHTS INTO THE TOTAL DOSE RESPONSE OF FULLY- DEPLETED PLANAR AND FINFET SOI TRANSISTORS

3D SOI elements for System-on-Chip applications

UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

MEASUREMENT AND INSTRUMENTATION STUDY NOTES UNIT-I

FET(Field Effect Transistor)

Floating Body and Hot Carrier Effects in Ultra-Thin Film SOI MOSFETs

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI

Analog and Telecommunication Electronics

Processing and Reliability Issues That Impact Design Practice. Overview

Transcription:

Session 3: Solid State Devices Silicon on Insulator 1

Outline A B C D E F G H I J 2

Outline Ref: Taurand Ning 3

SOI Technology SOl materials: SIMOX, BESOl, and Smart Cut SIMOX : Synthesis by IMplanted OXygen. thickness uniformity of the thin SOl layer high defect densities in Si and SiO2 BESOl : Bond and Etch back Good crystalline quality thickness variation Smart Cut: both ion implantation and bonding are used H2 implantation 4

SOl CMOS schematic cross-section of SOlCMOS, with shallow trench isolation, dual polysilicongates, and self-aligned silicide. Very low junction capacitance No body effect No latch-up Ease in scaling Simpler device isolation (denser) Compatible with conv. Si processing (Sometimes) fewer steps to fabricate Reduced leakage Soft error immunity Drain Current Overshoot kink effect floating body (Historydependent ) Thickness control (fully depleted operation) Surface states 5

Partially Depleted SOI MOSFETs partially depleted (PD) : silicon film is thicker than the maximum gate depletion width and the devices exhibit floating-body effect Fully depleted (FD) : silicon film is thin enough that the entire film is depleted before the threshold condition is reached Floating-body effects: Unique kink effect: impact ionization near the drain affect the device threshold voltage practical switching: drain current overshoot. (Even though floating-body effects tend to enhance circuit speed in certain conditions, the drain current overshoot (or undershoot) is history dependent) 6

CMOS Latchup SOI : no parasitic bipolar device no latch up 7

Soft Errors in bulk CMOS Alpha Particles Sources: Cosmic Rays (aircraft electronics vulnerable) Decaying uranium and thorium impurities in integrated circuit interconnect Generates electron-hole pairs in substrate: Excess carriers collected by diffusion terminals of transistors Can cause upset of state nodes floating nodes, DRAM cells most vulnerable 8

Denser Layout Simpler isolation smaller layout memory cell implementation 9

Electrical Anomalies Floating-body effect: Usually seen in Partially-Depleted devices. As shown in figure, the MOS structure is accompanied by a parasitic bipolar device in parallel.the base of this device is floating. Kink Effect: Sudden discontinuity in drain current. Seen when the device is biased in the saturation region. The bipolar device is turned on. Solution: Provide a body contact for the device. Use FD devices. 10

Q? 1/f Noise in SOI NFET SOI offers 33% less noise than bulk. 11

Performance Enhancement 12

Fully Depleted SOI MOSFETs Floating-body effect can be largely avoided in FD SOl devices the entire silicon film can be undopedbecause FD SOlMOSFETs scale by the silicon film thickness 1 1 3 1 lower (for the same off-current) lower supply voltages low power operation To function properly: ~5 3 ~0.5 13

Thin-Silicon SOl Bipolar Schematic cross section of a thin-silicon SOlSiGe-base bipolar transistor. The dotted arrows indicate the path ofelectrons from the emitter to the collector reach-through. 14

Double-Gate MOSFETs ~1.5 2 15

Multiple-Gate MOSFETs 16

Scaling Limits! 17

DG SOI Medici-predicted DIBL and subthresholdswing versus effective channel length for DG and bulk-silicon nfets 18

FINFET 19

FINFET lightly p-doped substrate with a hard mask on top (e.g. silicon nitride) as well as a patterned resist layer highly anisotropic etch process(height width) oxide deposition with a high aspect ratio filling Another etch process is needed to recess the oxide film to form a lateral isolation of the fins gate oxide is deposited via thermal oxidation oxide is planarized by chemical mechanical polishing highly n+ doped poly silicon layer is deposited 20

Q? Punch through in SOI Surface charge influence on the depletion layer at the edge of a planar junction: (a) positive charge (b) zero charge (c) negative charge 21

Strained Si tension compression IEEE ED, Vol25, pp191. 22

Lattice Mismatch! 23

Strained Si n-mosfet 24

Strained Silicon in SOI Peak electron mobility enhancement = 85% Peak hole mobility enhancement = 50% 25

SSOI vs. SOI Charge mobility enhancement of SSOI vs. SOI 26

FINFET 27