Field-Effect Transistors (FETs) 3.9 MOSFET as an Aplifier Sall-signal equivalent circuit odels Discussions about the MOSFET transconductance W Forula 1: g = k n ( VGS Vt ) L It indicates that g is proportional to the k, W/L ratio and ( VGS Vt ) However, a large V GS reduces the allowable signal swing at the drain. Forula 2: g = 2k n W L It indicates (1) for a given MOSFET, g is proportional to the square root of the DC bias current. (2) At a given bias current, g is proportional to W / L In contrast, the transconductince of BJT is proportional to the bias current and is independent of the geoetry. I D Forula 3: g = I D ( VGS Vt ) / 2 As copared with that of BJT, for which I g = V The transconductance value for MOSFET is uch sall than that of BJT in light of the fact that the values of (V GS -V t )/2 are at least 0.1 V or so. In spite of their low g, MOSFETs have any other advantages, such as high R in, sall size, low power dissipation and ease of fabrication. C T
An Exaple of Sall Signals Two solutions: I D1 = 1.0589 A and V D = 4.4 V I D2 = 1.721 A and V D < 0 which is not physically eaningful
An Exaple of Sall Signals The value of g is given by W g = kn ( VGS Vt ) L = 0.25(4.4 1.5) = 0.725 A/V The output resistance VA 50 ro = = = 47kΩ I 1.06 Since R G is very large (10MW), the current through it can be neglected. v g o D v gs ( RD // RL // ro )
3.10 The T Equivalent Circuit Model
3.11 Biasing of MOS Aplifiers Biasing of Discrete MOSFET Aplifiers Single power suppler is used. Since I G =0, R G1 and R G2 can be very large, allowing large Rin, R S provides negative feedback. R D should be large for high gain and should be sall for large signal swing. Two power suppliers are used. Sipler bias arrangeent. R G establishes a DC ground and presents a high input resistance to a signal that ay be capacitively coupled to the gate. Even sipler and ore direct bias. A constantcurrent source I feeds the source terinal. Large resistor R G forces the V G to be equal to V D. The output signal swing should be liited in the negative direction to V t,
3.11 Biasing of MOS Aplifiers Biasing of IC MOSFET Aplifiers Two reasons that ake the biasing circuits for discrete aplifiers not practical for IC aplifiers: (1) Extensive use of resistors; (2) Capacitively coupled input and output. Let s look at the constant current source Two significance of the constant current source: (1) A siple relation between I O and I REF by the ratio of the aspect ratios of the geoetry. When I O = I REF, it is called current irror; (2) Current irrors are essential building blocks in the design of IC aplifiers.
Effect of V O on I O I O will equal the I REF only at the value of V O that causes the two devices to have the sae V DS, that is V O =V GS. As V O is increased above this value, I O will increase according to the channel-length odulation. The current source and current irror have finite output resistance R O V V O A2 Ro = ro 2 I = = O IO Recall that V A is proportional to the transistor channel length; thus to obtain high output-resistance values, current sources are usually designed using transistors with long channels.
Current-Steering Circuits Once a constant current is generated, it can be replicated to provide DC bias currents for various aplifier stages in an IC. Current Sink Current Source
3.12 Basic Configurations of Single-Stage IC MOS Aplifiers Active Load Since it is difficult to ipleent resistors in ICs, people eploy current sources in place of load resistors. It is called active loaded. These diagra shows the skeletons of the three basic configurations: the coon-source (CS); the coon-gate (CG) and the coon-drain (CD) Current Source Current Sink (CS) (CG) (CD)