LECTURE 19 DIFFERENTIAL AMPLIFIER

Lecture 19 Differential Amplifier (6/4/14) Page 191 LECTURE 19 DIFFERENTIAL AMPLIFIER LECTURE ORGANIZATION Outline Characterization of a differential amplifier Differential amplifier with a current mirror load Differential amplifier with MOS diode loads An intuitive method of small signal analysis Large signal performance of differential amplifiers Differential amplifiers with current source loads Design of differential amplifiers Summary CMOS Analog Circuit Design, 3 rd Edition Reference Pages 19817

Lecture 19 Differential Amplifier (6/4/14) Page 19 CHARACTERIZATION OF A DIFFERENTIAL AMPLIFIER What is a Differential Amplifier? A differential amplifier is an amplifier that amplifies the difference between two voltages and rejects the average or common mode value of the two voltages. Differential and common mode voltages: v 1 and v are called singleended voltages. They are voltages referenced to ac ground. The differentialmode input voltage, v ID, is the voltage difference between v 1 and v. The commonmode input voltage, v IC, is the average value of v 1 and v. v ID = v 1 v and v IC = v 1v v 1 = v IC 0.5v ID and v = v IC 0.5v ID v OUT = A VD v ID ± A VC v IC = A VD (v 1 v ) ± A VC v 1 v where A VD = differentialmode voltage gain A VC = commonmode voltage gain

Lecture 19 Differential Amplifier (6/4/14) Page 193 Differential Amplifier Definitions Common mode rejection rato (CMRR) CMRR = A VD A VC CMRR is a measure of how well the differential amplifier rejects the commonmode input voltage in favor of the differentialinput voltage. Input commonmode range (ICMR) The input commonmode range is the range of commonmode voltages over which the differential amplifier continues to sense and amplify the difference signal with the same gain. Typically, the ICMR is defined by the commonmode voltage range over which all MOSFETs remain in the saturation region. Output offset voltage (V OS (out)) The output offset voltage is the voltage which appears at the output of the differential amplifier when the input terminals are connected together. Input offset voltage (V OS (in) = V OS ) The input offset voltage is equal to the output offset voltage divided by the differential voltage gain. V OS = V OS(out) A VD

Lecture 19 Differential Amplifier (6/4/14) Page 194 Transconductance Characteristic of the Differential Amplifier Consider the following nchannel differential amplifier (called a sourcecoupled pair). Where should bulk be connected? Consider a pwell, CMOS technology: D1 G1 S1 S G D n n p n n n pwell nsubstrate 1.) Bulks connected to the sources: No modulation of V T but large common mode parasitic capacitance..) Bulks connected to ground: Smaller common mode parasitic capacitors, but modulation of V T. What are the implications of a large common mode capacitance? v IN R 0V R Little charging of capacitance Fig. 5.3 0704160 I Bias v IN v ID v G1 i D1 I SS i D M v GS1 v GS V Bulk Large charging of capacitance v G Fig. 5.

Lecture 19 Differential Amplifier (6/4/14) Page 195 Transconductance Characteristic of the Differential Amplifier Continued Defining equations: v ID = v GS1 v GS = Solution: v ID I SS i D1 i D i I SS I D1 = SS v 4 ID 4I SS 1/ which are valid for v ID (I SS /) 1/. Illustration of the result:.0 and I SS = i D1 i D v ID I SS and i I SS I D = SS 1.414 i D /I SS 1.0 v 4 ID 4I SS Differentiating i D1 (or i D ) with respect to v ID and setting V ID =0V gives 0.8 0.6 0.4 0. 0.0 i D1 i D v ID 1/ i D1 1.414.0 v ID (I SS /ß)0.5 i D M v GS1 v GS I SS 14100901 Fig. 5.4 gm = di D1 dv ID (V ID = 0) = I SS 4 = K'1I SS W1 4L1 (half the g m of an inverting amplifier)

Lecture 19 Differential Amplifier (6/4/14) Page 196 DIFFERENTIAL AMPLIFIER WITH A CURRENT MIRROR LOAD Voltage Transfer Characteristic of the Differential Amplifier In order to obtain the voltage transfer characteristic, a load for the differential amplifier must be defined. We will select a current mirror load as illustrated below. Note that output signal to ground is equivalent to the differential output signal due to the current mirror. The shortcircuit, transconductance is given as g m = di OUT dv ID (V ID = 0) = I SS = v G1 v GS1 mm 1mm mm 1mm V Bias i D3 i D1 mm 1mm K' 1 I SS W 1 L 1 mm 1mm I SS M5 M mm 1mm i D4 i D v GS i OUT v G v OUT Fig. 5.5

Lecture 19 Differential Amplifier (6/4/14) Page 197 Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load Regions of operation of the transistors: M is saturated when, v DS v GS V TN v OUT V S1 V IC 0.5v ID V S1 V TN v OUT V IC V TN where we have assumed that the region of transition for M is close to v ID = 0V. is saturated when, v SD4 v SG4 V TP v OUT V SG4 V TP v OUT V SG4 V TP The regions of operations shown on the voltage transfer function assume I SS = 100µA. Note: V SG4 = 50 50 V TP = 1 VTP vout 5 1 0.7 0.7 = 4V

Lecture 19 Differential Amplifier (6/4/14) Page 198 Input Common Mode Range (ICMR) ICMR is found by setting v ID = 0 and varying v IC until one of the transistors leaves the saturation. Highest Common Mode Voltage Path from G1 through and to : V IC (max) =V G1 (max) =V G (max) = V SG3 V DS1 (sat) V GS1 or V IC (max) = V SG3 V TN1 Path from G through M and to : V IC (max) = V SD4 (sat) V DS (sat) V GS = V SD4 (sat) V TN v G1 v GS1 mm 1mm mm 1mm V Bias i D3 i D1 mm 1mm mm 1mm I SS M5 M mm 1mm i D4 i D v GS i OUT v G v OUT Fig. 3300 V IC (max) = V SG3 V TN1 Lowest Common Mode Voltage (Assume a V SS for generality) V IC (min) = V SS V DS5 (sat) V GS1 = V SS V DS5 (sat) V GS where we have assumed that V GS1 = V GS during changes in the input common mode voltage.

Lecture 19 Differential Amplifier (6/4/14) Page 199 SmallSignal Analysis of the DifferentialMode of the Diff. Amp A requirement for differentialmode operation is that the differential amplifier is balanced. VDD v id i D3 i D1 M i D4 i out i D v out G1 v g1 v id G v g C1 D1=G3=D3=G4 i 3 1 r ds5 i 3 gm1v gs1 g m v gs g m3 r ds3 S3 r ds1 C3 S1=S r ds D=D4 r ds4 S4 C v out V Bias M5 I SS Differential Transconductance: G1 v gs1 g m1 v gs1 i 3 C3 1 rds3 g m3 C1 g m v gs i 3 S1=S=S3=S4 Assume that the output of the differential amplifier is an ac short. v id G v gs D1=G3=D3=G4 i out = g m1g m3 r p1 1 g m3 r p1 v gs1 g m v gs g m1 v gs1 g m v gs = g md v id r ds1 where g m1 = g m = g md, r p1 = r ds1 r ds3 and i' out designates the output current into a short circuit. rds D=D4 r ds4 C i out ' v out Fig. 33003 It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched. However, we will continue to use the assumption regardless.

Lecture 19 Differential Amplifier (6/4/14) Page 1910 SmallSignal Analysis of the DifferentialMode of the Diff. Amplifier Continued Output Resistance: 1 r out = g ds g = r ds r ds4 ds4 Differential Voltage Gain: A v out g md v = = v id g ds g ds4 If we assume that all transistors are in saturation and replace the small signal parameters of g m and r ds in terms of their largesignal model equivalents, we achieve Av v out (K' 1ISSW1/L1)1/ = vid = ( 4)(ISS/) = 4 K' 1W1 ISSL1 1/ 1 I SS Note that the smallsignal gain is inversely proportional to the square root of the bias current! Example: If W 1 /L 1 = µm/1µm and I SS = 50µA (10µA), then A v (nchannel) = 46.6V/V (104.3V/V) v out v in Weak Inversion A v (pchannel) = 31.4V/V (70.7V/V) 1 1 r out = g ds g = ds4 5µA 0.09V 1 = 0.444M (.M)» 1µA Strong Inversion log(i Bias ) 06061401

Lecture 19 Differential Amplifier (6/4/14) Page 1911 Common Mode Analysis for the Current Mirror Load Differential Amplifier The current mirror load differential amplifier is not a good example for common mode analysis because the current mirror rejects the common mode signal. Therefore: Total common Common mode Common mode mode Output = output due to output due to due to v ic path M path The common mode output voltage should ideally be zero. Any voltage that exists at the output is due to mismatches in the gain between the two different paths.

Lecture 19 Differential Amplifier (6/4/14) Page 191 DIFFERENTIAL AMPLIFIER WITH MOS DIODE LOADS SmallSignal Analysis of the CommonMode of the Differential Amplifier The commonmode gain of the differential amplifier with a current mirror load is ideally zero. To illustrate the commonmode gain, we need a different type of load so we will consider the following: v o1 vo v o1 v o v o1 v o M v 1 M v M v id v id V Bias I SS M5 v ic I SS M5x 1 V Bias I SS v ic Differentialmode circuit DifferentialMode Analysis: General circuit Commonmode circuit 110140 v o1 v id g m1 g m3 and v o v id g m g m4 Note that these voltage gains are half of the active load inverter voltage gain.

Lecture 19 Differential Amplifier (6/4/14) Page 1913 SmallSignal Analysis of the CommonMode of the Differential Amplifier Cont d CommonMode Analysis: Assume that r ds1 is large and can be ignored (greatly simplifies the analysis). v gs1 = v g1 vs1 = v ic g m1 r ds5 v gs1 Solving for v gs1 gives v ic v gs1 r ds5 g m1 v gs1 r ds1 r ds3 1 g m3 v o1 Fig. 33006 v gs1 = v ic 1 g m1 r ds5 The singleended output voltage, v o1, as a function of v ic can be written as v o1 v = g m1[r ds3 (1/g m3 )] ic 1 g m1 r ds5 CommonMode Rejection Ratio (CMRR): (g m1 /g m3 ) 1 g m1 r ds5 g ds5 g m3 CMRR = v o1/v id v o1 /v ic = g m1/g m3 g ds5 /g m3 = g m1 r ds5 How could you easily increase the CMRR of this differential amplifier?

Lecture 19 Differential Amplifier (6/4/14) Page 1914 Frequency Response of the Differential Amplifier Back to the current mirror load differential amplifier: C bd3 C gd1 v id Ignore the zeros that occur due to C gd1, C gd and C gd4. C 1 = C gd1 C bd1 C bd3 C gs3 C gs4, C = C bd C bd4 C gd C L and C 3 = C gd4 The poles are p 1 = g m3 /C 1 and p = (g ds g ds4 )/C. Since p 1 >> p, then we can write V out (s) M M5 V Bias VDD C gs3 C gs4 g m1 C bd4 C gd4 C bd1 C gd C bd C L v out G1 v gs1 v gs gm1v gs1 i 3 C3 1 C1 i 3 g ds g ds4 s [V gs1 (s) V gs (s)] where g ds g ds4 C The approximate frequency response of the differential amplifier reduces to V out (s) V id (s) g m1 g ds g ds4 s v id v id v gs1 G v gs gm1v gs1 D1=G3=D3=G4 gm3 gmv gs S1=S=S3=S4 i 3 1 i 3 gm3 gmv gs D=D4 rds rds4 rds rds4 C C v out v out 07041603

Lecture 19 Differential Amplifier (6/4/14) Page 1915 SMALL SIGNAL PERFORMANCE OF THE DIFFERENTIAL AMPLIFIER Simplification of Small Signal Analysis Small signal analysis is used so often in analog circuit design that it becomes desirable to find faster ways of performing this important analysis. Intuitive Analysis (or Schematic Analysis) Technique: 1.) Identify the transistor(s) that convert the input voltage to current (these transistors are called transconductance transistors)..) Trace the currents to where they flow into an equivalent resistance to ground. 3.) Multiply this resistance by the current to get the voltage at this node to ground. 4.) Repeat this process until the output is reached. Simple Example: R 1 g m1 v in v o1 gm v o1 M v out v in R Fig. 5.10C v o1 = (g m1 v in ) R 1 v out = (g m v o1 )R v out = (g m1 R 1 g m R )v in

Lecture 19 Differential Amplifier (6/4/14) Page 1916 Intuitive Analysis of the CurrentMirror Load Differential Amplifier 1.) i 1 = 0.5g m1 v id and i = 0.5g m v id.) i 3 = i 1 = 0.5g m1 v id 3.) i 4 = i 3 = 0.5g m1 v id 4.) The shortcircuit output current is i 4 i = 0.5g m1 v id 0.5g m v id = g m1 v id 4.) The resistance at the output node, r out, is r ds r ds4 or 1 g ds g ds4 5.) v out = (0.5g m1 v id 0.5g m v id )r out v id V Bias g m1 v id g m1 v id M5 VDD g m1 v id g m v id v id M r out v id 140640 v out = g m1 v in g ds g ds4 = g m v in g ds g ds4 v out v in = g m1 g ds g ds4

Lecture 19 Differential Amplifier (6/4/14) Page 1917 Some Concepts to Help Extend the Intuitive Method of SmallSignal Analysis 1.) Approximate the output resistance of any cascode circuit as R out (g m r ds )r ds1 where is a transistor cascoded by M..) If there is a resistance, R, in series with the source of the transconductance transistor, let the effective transconductance be g m g m(eff) = 1g m R Proof: v in g m (eff)v in V Bias M g m (eff)v in M v in r ds1 v gs v in r ds1 g m v gs Smallsignal model i out Fig. 5.11A v gs = v g v s = v in (g m r ds1 )v gs v gs = v in 1g m r ds1

Lecture 19 Differential Amplifier (6/4/14) Page 1918 Thus, i out = g m v in 1g m r ds1 = g m (eff) v in

Lecture 19 Differential Amplifier (6/4/14) Page 1919 Noise Analysis of the Differential Amplifier V Bias M5 M5 V Bias M5 e n1 * M * i to e n3 e n4 e n e eq * M v OUT * * V out Solve for the total outputnoise current to get, i to = g m1 e n1 g m e n g m3 e n3 g m4 e n4 Fig. 5.11C This outputnoise current can be expressed in terms of an equivalent input noise voltage, e eq, given as i to = g m1 e eq Equating the above two expressions for the total outputnoise current gives, e eq = e n1 e n g m3 g e n3 e n4 m1 1/f Noise (e n1 =e n and e n3 =e n4 ): Thermal Noise (e n1 =e n and e n3 =e n4 ): e eq (1/f) = B P fw 1 L 1 K N B N 1 K L 1 P B P L e 16kT eq (th) = 3 3[K' 1 (W/L) 1 I 1 ] 1/ W 3 L 1 K' 3 1 L 3 W 1 K' 1

Lecture 19 Differential Amplifier (6/4/14) Page 190 CMOS Input Offset Voltage Strong Inversion Circuit: R D1 RD I D1 I D VOUT V 1 V V GS1 V GS I SS 1404304 Input Offset Voltage: V IO = V GS1 V GS = V T1 V T But I D1 R D1 = I D R D, therefore I D1 L1 K' W 1 L 1 V IO = V T I D R D I D W 1 K 1 R D1 K = V T where I D1 I D = I D and V T = V T1 V T. Assuming matched geometries, W 1 /L 1 = W /L = W/L, V IO = V T I D L R D 1 W K 1 R D1 K I D L K' W I D L 1 R D 1 W 1 K 1 R D1 K

Lecture 19 Differential Amplifier (6/4/14) Page 191 CMOS Input Offset Voltage Strong Inversion Define the following, R D1 = R 0.5R, R D = R 0.5R, K 1 = K 0.5K, and K = K 0.5K where R = 0.5(R D1 R D ), R = R D1 R D, K = 0.5(K 1 K ), and K = K 1 K. Substituting these relationships into the expression for V IO gives, I D L V IO = V T R 0.5R W (K 0.5K)(R 0.5R) 1 K 0.5K Factoring out R and K gives, I D L V IO = V T 1 0.5R/R KW (1 0.5K/K)(1 0.5R/R) 1 1 0.5K/K Approximating 1/(1 ± ) as 1 results in, V IO V T I D L KW (1 0.5R/R)(1 0.5K/K)(1 0.5R/R) 1 0.5K/K Finally, multiplying terms and ignoring higher order terms and letting x 0.5x gives, V IO V T 1 R R K K I D L KW = V T 1 R R K K (V GS V T )

Lecture 19 Differential Amplifier (6/4/14) Page 19 CMOS Input Offset Voltage Temperature Drift Strong Inversion Assumptions: Drain current is constant, R/R and K/K have very little temperature dependence. Therefore only V T and K will considered in the expression below V IO V T 1 R R K K I D L KW Assuming V T (T) = V T (T o ) (T T o ) and K(T) = kt 1.5, then we get, V T dt = d dt [V T1 (T T o ) V T (T T o )] = = and d dt I D L KW = I D L Therefore, dv IO dt = 3 4T R R K K Comments: KW 3 T.5 T 1.5 = 3 T I D L KW I D L KW = 3 4T R R K K (V GS V T ) = 1 400 100 1 10 = 5µV/ C When the overdrive is large, the input offset voltage temperature drift will be larger Typical values of dv IO /dt are 110µV/ C CMOS Input Offset Voltage Temperature Drift Weak Inversion

Lecture 19 Differential Amplifier (6/4/14) Page 193 Repeating the previous analysis with the following model for the transistors gives, But i D1 R D1 = i D R D and W 1 /L 1 = W /L = W/L which gives, Define the following, W æ i D = I T1 L exp V V ö ç GS T è nv t ø æ V IO = V GS1 V GS = V T1 nv t ln i L ö æ ç D1 1 è I T1 W V T nv t ln i L ö æ ç D 1 ø è I T W = DV T nv t ln i L I W ö ç D1 1 T ø èi D L I T1 W 1 ø æ V IO = DV T ln R I ö ç D T è R D1 I T1 ø R D1 = R 0.5R, R D = R 0.5R, I T1 = I T 0.5I T, and I T = I T 0.5I T where R = 0.5(R D1 R D ), R = R D1 R D, I T = 0.5(I T1 I T ), and I T = I T1 I T. Substituting these relationships into the expression for V IO gives, æ V IO = DV T nv t ln (R 0.5DR)(I 0.5DI ) ö æ ç T T è(r 0.5DR)(I T 0.5DI T ) = DV T nv t ln (1 0.5DR R)(1 0.5DI I T T ) ö ç ø è(1 0.5DR R)(1 0.5DI T I T ) ø» DV T nv t ln é ë (1 0.5DR R) (1 0.5DI T I T ) ù û» DV T nv t lné1 DR R DI T I ù ë T û æ DR» DV T nv t R DI ö ç T è ø I T

Lecture 19 Differential Amplifier (6/4/14) Page 194 LARGE SIGNAL PERFORMANCE OF THE DIFFERENTIAL AMPLIFIER Linearization of the Transconductance Goal: I SS i out I SS i out v in Linearization v in I SS I SS 06060803 Method (degeneration): i out i out v in V NBias1 R S R S M5 M or v in V NBias1 M5 R S M M6 06011810

Lecture 19 Differential Amplifier (6/4/14) Page 195 Linearization with Active Devices i out i out v in V NBias1 M5x1/ V Bias M6 M M5x1/ or v in V NBias1 M5 M6 M7 M M6 M6 is in deep triode region 06060805 M6 and M7 are in the triode region Note that these transconductors on this slide and the last can all have a varying transconductance by changing the value of I SS.

Lecture 19 Differential Amplifier (6/4/14) Page 196 Slew Rate of the Differential Amplifier Slew Rate (SR) = Maximum outputvoltage rate (either positive or negative) dv OUT It is caused by, i OUT = C L dt. When i OUT is a constant, the rate is a constant. Consider the following currentmirror load, differential amplifiers: v G1 v GS1 V Bias i D3 i D1 VDD I SS M5 Note that slew rate can only occur when the differential input signal is large enough to cause I SS (I DD ) to flow through only one of the differential input transistors. SR = I SS C L = I DD C L M i D4 i D v GS i OUT v G C L v OUT V Bias v G1 v SG1 If C L = 5pF and I SS = 10µA, the slew rate is SR = V/µs. (For the BJT differential amplifier slewing occurs at ±100mV whereas for the MOSFET differential amplifier it can be ±V or more.) i D1 i D3 M5 IDD M i D4 C L v SG i D i OUT v OUT v G Fig. 5.11B

Lecture 19 Differential Amplifier (6/4/14) Page 197 DIFFERENTIAL AMPLIFIERS WITH CURRENT SOURCE LOADS CurrentSource Load Differential Amplifier Gives a truly balanced differential amplifier. Also, the upper input commonmode range is extended. However, a problem occurs if I 1 I 3 or if I I 4. Current Current X1 M7 v 3 X1 I 3 I 4 X1 I Bias v 1 I 1 I X1 X1 M M6 M5 I 5 X1 X v4 Fig. 5.1 v I 3 I 1 I 3 I 1 0 0 v DS1 V DS1 <V DS (sat) 0 0 V SD3 <V SD (sat) (a.) I1>I3. (b.) I3>I1. v DS1 Fig. 5.13

Lecture 19 Differential Amplifier (6/4/14) Page 198 A DifferentialOutput, DifferentialInput Amplifier Probably the best way to solve the current mismatch problem is through the use of commonmode feedback. Consider the following solution to the previous problem. MB I Bias V CM MC3 Commonmode feedback circuit I C3 MC1 MC5 MCA MC4 I C4 MCB v 3 I 3 I 4 v 1 M M5 v 4 Selfresistances of v Operation: V SS Fig. 5.14 Common mode output voltages are sensed at the gates of MCA and MCB and compared to V CM. The current in MC3 provides the negative feedback to drive the common mode output voltage to the desired level. With large values of output voltage, this common mode feedback scheme has flaws.

Lecture 19 Differential Amplifier (6/4/14) Page 199 CommonMode Stabilization of the Diff.Output, Diff.Input Amplifier Continued The following circuit avoids the large differential output signal swing problems. I Bias V CM MC3 Commonmode feedback circuit I C3 MC1 MC MC4 I C4 v 3 R C R CM I 3 I 4 v 1 M v 4 Selfresistances of v MB MC5 M5 V SS Fig. 5.145 Note that R C and R CM must not load the output of the differential amplifier. (We will examine more CM feedback schemes in Lecture 8.)

Lecture 19 Differential Amplifier (6/4/14) Page 1930 DESIGN OF DIFFERENTIAL AMPLIFIERS Design of a CMOS Differential Amplifier with a Current Mirror Load Design Considerations: Constraints Power supply Technology Temperature Relationships A v = g m1 R out 3dB = 1/R out C L Specifications Smallsignal gain Frequency response (C L ) ICMR Slew rate (C L ) Power dissipation V IC (max) = V SG3 V TN1 V IC (min) = V SS V DS5 (sat) V GS1 = V SS V DS5 (sat) V GS SR = I SS /C L vin M P diss = ( V SS )x(all dc currents flowing from or to V SS ) V Bias V SS I 5 M5 ALA0 C L v out

Lecture 19 Differential Amplifier (6/4/14) Page 1931 Design of a CMOS Differential Amplifier with a Current Mirror Load Continued Schematicwise, the design procedure is illustrated as shown: Procedure: 1.) Pick I SS to satisfy the slew rate knowing C L or the power dissipation.) Check to see if R out will satisfy the frequency response, if not change I SS or modify circuit 3.) Design W 3 /L 3 (W 4 /L 4 ) to satisfy the upper ICMR 4.) Design W 1 /L 1 (W /L ) to satisfy the gain 5.) Design W 5 /L 5 to satisfy the lower ICMR 6.) Iterate where necessary

Lecture 19 Differential Amplifier (6/4/14) Page 193 Example 191 Design of a MOS Differential Amp. with a Current Mirror Load Design the currents and W/L values of the current mirror load MOS differential amplifier to satisfy the following specifications: = V SS =.5V, SR 10V/µs (C L =5pF), f 3dB 100kHz (C L =5pF), a small signal gain of 100V/V, 1.5VICMRV and P diss mw. Use the parameters of K N =110µA/V, K P =50µA/V, V TN =0.7V, V TP =0.7V, N =0.04V1 and P =0.05V1. Solution 1.) To meet the slew rate, I SS 50µA. For maximum P diss, I SS 00µA..) f 3dB of 100kHz implies that R out 318k Therefore R out = 318k ( N P )I SS I SS 70µA Thus, pick I SS = 100µA 3.) V IC (max) = V SG3 V TN1 V =.5 V SG3 0.7 50µA V SG3 = 1.V = 50µA/V(W 3 /L 3 ) 0.7 W 3 L 3 = W 4 L 4 = (0.5) = 8

Lecture 19 Differential Amplifier (6/4/14) Page 1933 Example 191 Continued g m1 4.) 100=g m1 R out = g ds g = ds4 110µA/V (W 1 /L 1 ) (0.040.05) 50µA = 3.31 W 1 L 1 W 1 L 1 = W L = 18.4 5.) V IC (min) = V SS V DS5 (sat)v GS1 1.5 =.5V DS5 (sat) V DS5 (sat) = 0.3 0. = 0.0777 50µA 110µA/V(18.4) 0.7 W 5 L 5 = I SS K N V DS5 (sat) = 150.6 We probably should increase W 1 /L 1 to reduce V GS1. If we choose W 1 /L 1 = 40, then VDS5(sat) = 0.149V and W 5 /L 5 = 41. (Larger than specified gain should be okay.)

Lecture 19 Differential Amplifier (6/4/14) Page 1934 SUMMARY Differential amplifiers are compatible with the matching properties of IC technology The differential amplifier has two modes of signal operation: Differential mode Common mode Differential amplifiers are excellent input stages for voltage amplifiers Differential amplifiers can have different loads including: Current mirrors MOS diodes Current sources/sinks Resistors The small signal performance of the differential amplifier is similar to the inverting amplifier in gain, output resistance and bandwidth The large signal performance includes slew rate and the linearization of the transconductance The design of CMOS analog circuits uses the relationships of the circuit to design the dc currents and the W/L ratios of each transistor