Applications l Switch Mode Power Supply (SMPS) l Uninterruptable Power Supply l High speed power switching SMPS MOSFET PD-93772A HEXFET Power MOSFET V DSS Rds(on) max I D 400V.0Ω 5.5A Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Effective Coss Specified (See AN) 2 D Pak TO-262 Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 5.5 I D @ T C = C Continuous Drain Current, V GS @ V 3.5 A I DM Pulsed Drain Current 22 P D @T C = 25 C Power Dissipation 74 W Linear Derating Factor 0.6 W/ C V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 4.6 V/ns T J Operating Junction and -55 to 50 T STG Storage Temperature Range Soldering Temperature, for seconds 300 (.6mm from case ) C Typical SMPS Topologies: l l Single Transistor Flyback Xfmr. Reset Single Transistor Forward Xfmr. Reset (Both US Line input only). Notes through are on page www.irf.com 5/8/00
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 400 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.5 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance.0 Ω V GS = V, I D = 3.3A V GS(th) Gate Threshold Voltage 2.0 4.5 V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 25 V µa DS = 400V, V GS = 0V 250 V DS = 320V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage V GS = 30V na Gate-to-Source Reverse Leakage - V GS = -30V Dynamic @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 3. S V DS = 50V, I D = 3.3A Q g Total Gate Charge 22 I D = 3.5A Q gs Gate-to-Source Charge 5.8 nc V DS = 320V Q gd Gate-to-Drain ("Miller") Charge 9.3 V GS = V, See Fig. 6 and 3 t d(on) Turn-On Delay Time V DD = 200V t r Rise Time 22 ns I D = 3.5A t d(off) Turn-Off Delay Time 20 R G = 2Ω t f Fall Time 6 R D = 57Ω,See Fig. C iss Input Capacitance 600 V GS = 0V C oss Output Capacitance 3 V DS = 25V C rss Reverse Transfer Capacitance 4.0 pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 890 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 30 V GS = 0V, V DS = 320V, ƒ =.0MHz C oss eff. Effective Output Capacitance 45 V GS = 0V, V DS = 0V to 320V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 290 mj I AR Avalanche Current 5.5 A E AR Repetitive Avalanche Energy 7.4 mj Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.7 C/W R θja Junction-to-Ambient ( PCB Mounted, steady-state)* 40 Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 5.5 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 22 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.6 V T J = 25 C, I S = 5.5A, V GS = 0V t rr Reverse Recovery Time 370 550 ns T J = 25 C, I F = 3.5A Q rr Reverse RecoveryCharge.6 2.4 µc di/dt = A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2 www.irf.com
I D, Drain-to-Source Current (A) 0. VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 0.0 T J = 25 C 0. V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current (A) 0. VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 50 C 0.0 0. V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) T J = 50 C T J = 25 C V DS = 50V 20µs PULSE WIDTH 0. 4.0 5.0 6.0 7.0 8.0 9.0.0 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.5 I D = 5.5 5.9A 2.0.5.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 20 40 60 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance(pF) 000 00 0 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 0 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 20 I D = 5.5 5.9A 6 V DS = 320V V DS = 200V V DS = 80V 2 8 4 FOR TEST CIRCUIT SEE FIGURE 3 0 0 5 5 20 25 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS(on) I SD, Reverse Drain Current (A) T = 50 J C T J = 25 C V GS = 0 V 0. 0.4 0.6 0.8.0.2 V SD,Source-to-Drain Voltage (V) I D, Drain Current (A) us us ms ms TC = 25 C TJ = 50 C Single Pulse 0. 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
6.0 V DS R D I D, Drain Current (A) 5.0 4.0 3.0 2.0 R G V GS V Pulse Width µs Duty Factor 0. % D.U.T. Fig a. Switching Time Test Circuit - V DD.0 0.0 25 50 75 25 50 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 0.0 2. Peak T J = P DM x Z thjc TC 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
V DSav, Avalanche Voltage ( V ) R G V DS 20V tp Fig 2a. Unclamped Inductive Test Circuit tp L D.U.T I AS 0.0Ω V (BR)DSS 5V DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) 700 600 500 400 300 200 TOP BOTTOM I D 2.5A 3.5A 5.5A 0 25 50 75 25 50 Starting T, Junction Temperature ( J C) I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy Vs. Drain Current V Q GS Q GD 6 V G Current Regulator Same Type as D.U.T. Charge Fig 3a. Basic Gate Charge Waveform 600 590 580 570 2V V GS.2µF 50KΩ 3mA.3µF D.U.T. I G I D Current Sampling Resistors V - DS Fig 3b. Gate Charge Test Circuit 540 0.0.0 2.0 3.0 4.0 5.0 6.0 I AV, Avalanche Current ( A) Fig 2d. Typical Drain-to-Source Voltage Vs. Avalanche Current 6 www.irf.com 560 550
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS www.irf.com 7
D 2 Pak Package Outline.40 (.055) M AX..54 (.45).29 (.405) - A - 2 4.69 (.85) 4.20 (.65) - B -.32 (.052).22 (.048).6 (.400) REF. 6.47 (.255) 6.8 (.243).78 (.070).27 (.050) 3 5.49 (.6) 4.73 (.580) 2.79 (.) 2.29 (.090) 5.28 (.208) 4.78 (.88) 2.6 (.3) 2.32 (.09) 3X.40 (.055).4 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.08).39 (.055).4 (.045) 8.89 (.350) REF. 0.25 (.0) M B A M MINIMUM RECOMMENDED FOOTPRINT.43 (.450) NOTES: DIMENSIONS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 3 CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. LEAD ASSIGNMENTS - GATE 2 - DRAIN 3 - SOURCE 8.89 (.350) 3.8 (.50) 7.78 (.700) 2.08 (.082) 2X 2.54 (.) 2X Part Marking Information D 2 Pak INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S 9246 9B M PART NUMBER DATE CODE (YYW W ) YY = YEAR WW = WEEK A 8 www.irf.com
Package Outline TO-262 Outline Part Marking Information TO-262 www.irf.com 9
Tape & Reel Information D 2 Pak TRR.60 (.063).50 (.059) 4. (.6) 3.90 (.53).60 (.063).50 (.059) 0.368 (.045) 0.342 (.035) FEED DIRECTION TRL.85 (.073).65 (.065).90 (.429).70 (.42).60 (.457).40 (.449) 6. (.634) 5.90 (.626).75 (.069).25 (.049) 5.42 (.609) 5.22 (.60) 24.30 (.957) 23.90 (.94) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.50 (.532) 2.80 (.504) 27.40 (.079) 23.90 (.94) 4 330.00 (4.73) MAX. 60.00 (2.362) MIN. Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 9mH R G = 25Ω, I AS = 5.5A. (See Figure 2) ƒ I SD 5.5A, di/dt 90A/µs, V DD V (BR)DSS, T J 50 C NOTES :. COMFORMS TO EIA-48. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (.039) 24.40 (.96) 3 Pulse width 300µs; duty cycle 2%. 30.40 (.97) MAX. 4 C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS Uses IRF730A data and test conditions * When mounted on " square PCB ( FR-4 or G- Material ). For recommended footprint and soldering techniques refer to application note #AN-994. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 IR EUROPEAN REGIONAL CENTRE: 439/445 Godstone Rd, Whyteleafe, Surrey CR3 OBL, UK Tel: 44 (0)20 8645 8000 IR CANADA: 5 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 57, 6350 Bad Homburg Tel: 49 (0) 672 96590 IR ITALY: Via Liguria 49, 7 Borgaro, Torino Tel: 39 0 45 0 IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo 7 Tel: 8 (0)3 3983 0086 IR SOUTHEAST ASIA: Kim Seng Promenade, Great World City West Tower, 3-, Singapore 237994 Tel: 65 (0)838 4630 IR TAIWAN:6 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 673 Tel: 886-(0)2 2377 9936 Data and specifications subject to change without notice. 5/00 www.irf.com