Assoc. Prof. Dr. MONTREE SIRIPRUCHYANUN

1 Assoc. Prof. Dr. MONTREE SIRIPRUCHYANUN Dept. of Teacher Training in Electrical Engineering 1 King Mongkut s Institute of Technology North Bangkok 1929 Bulky, expensive and required high supply voltages. www.maxim-ic.com/an1768 2

2 IEEE J. Solid-State Circuits, Vol. 32, 12, pp. 2071-2088, 1997 3 4

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4 1906 1906 1947 1947 Audion (Triode), 1906 Lee De Forest First point contact transistor (germanium), 1947 John Bardeen and Walter Brattain Bell Laboratories 7 1958 1958 1997 1997 First integrated circuit (germanium), 1958 Jack S. Kilby, Texas Instruments Contained five components, three types: transistors resistors and capacitors Intel Pentium II, 1997 Clock: 233MHz Number of transistors: 7.5 M Gate Length: 0.35 8

5 Number of transistors doubles every 2.3 years (acceleration over the last 4 years: 1.5 years) 42 M transistors Increase: ~20K 2.25 K transistors (From: http://www.intel.com) 9 2 GHz Intel Labs Sub-ps switching transistor μp clock > 20 GHz Gate length: 20nm Gate oxide: 3 atomic layers In production: 2007! 10

6 Intel Labs Sub-ps switching transistor μp clock > 20 GHz Gate length: 20nm Gate oxide: 3 atomic layers In production: 2007! 0.13 μm in production 11 Semiconductor Industry Association (SIA) Road Map, 1998 Update 1999 2002 2014 Technology (nm) 180 130 35 Minimum mask count 22/24 24 29/30 Wafer diameter (mm) 300 300 450 Memory-samples (bits) 1G 4G 1T Transistors/cm 2 (μp) 6.2M 18M 390M Wiring levels (maximum) 6-7 7 10 Clock, local (MHz) 1250 2100 10000 Chip size: DRAM (mm 2 ) 400 560 2240 Chip size: μp (mm 2 ) 340 430 901 Power supply (V) 1.5-1.8 1.2-1.5 0.37-0.42 Maximum Power (W) 90 130 183 Number of pins (μp) 700 957 3350 IEEE Spectrum, July 1999 Special report: The 100-million transistor IC These scaling trends will allow the electronics market to growth at 15% / year 12

7 1% GaAs and others 100 90 80 70 60 4% 19% 22% ECL TTL and OTHER BIPOLAR ANALOG 4% 12% 20% 10% 70% 8% BIPOLAR 50 40 30 2% 41% PMOS NMOS 24% CMOS 86 % MOS 20 39% BiCMOS 10 12% 16% 4% 1982 1987 1996 2001 Year http://smithsonianchips.si.edu/ice/cd/status97/sec04.pdf 13 1.6 100 Gate Length (nm) 90 80 70 65 57 50 0.16 1.2 0.12 2 DD 0.8 0.08 0.4 0.04 0.0 2002 2004 2006 2008 2010 0.00 Trend of supply voltage and 1/f noise from 2003 ITRS Roadmap 14

8 1000 500 Gate Length (nm) 100 90 80 70 65 57 50 Peak f max Peak f T 1.0 0.8 0.6 0.4 0.2 0.0 min 100 2002 2004 2006 2008 2010 Trend of supply voltage and 1/f noise from 2003 ITRS Roadmap 15 Si CMOS displacement of other technologies continues Boundary between GaAs & InP shifting to lower frequencies Cost is a key factor in determining boundaries ITRS 2003 Roadmap, RF and AMS Technologies for Wireless Communications 16

9 kabuki.eecs.berkeley.edu/~jrudell/ IEEE Spectrum, March 2002 Using standard, mature CMOS processes to design RFIC building blocks With CMOS, DSP blocks can be integrated with RF frontend on the same chip good IP 17 integration Drain Current (A) G 10-4 10-6 10-8 10-10 V GS 0.5V 0V -0.5V D S V DS B V BS NMOS, 10x0.2μm V DS =25mV V BS improves the MOSFET performance Forward substrate biasing (V BS >0) reduces the threshold voltage V T low voltage applications Forward substrate biasing (V BS >0) speeds - up the MOSFET RF applications Reverse substrate biasing (V BS <0) reduces the drain current I D low power applications 10-12 0.0 0.3 0.6 0.9 1.2 Gate Voltage (V) 18

10 Operate transistor in weak inversion Very low V DS required to operate transistor low-voltage applications Drain current I D also very low low-power applications I D (A) 10-9 10-10 10-11 10-12 10-13 10-14 Calculation Measured V DS (V) 0.20 0.15 0.10 0.04V V GS =-0.01V 0 0.05 0.1 0.15 Proc. ISCAS, pp. I697-I700 and I701-I704, Bangkok, Thailand (May 25-28, 2003) 19 Duplexer LNA PA Band-pass filter Band-pass filter LO ADC Channel select DAC Low frequency signal processing Small Signal RF Power Management Analog Baseband Power RF Digital Baseband (DSP + MCU) bwrc.eecs.berkeley.edu Proc. IEEE EDSSC, Hong Kong, 14-16 December 2003 20

11 m V DD Buffer IF+ (to buffer) LO+ R L R L LO- IF- (to buffer) LO+ RF- RF+ I BIAS Supply voltage/power 1.2V/3.95mW SSB Noise Figure/IIP3 17dB/8dBm RF Input/Conversion Gain 1.9GHz/-2dB FoM/Technology 199dB/0.18μm Proc. IEEE EDSSC, Hong Kong, 14-16 December 2003 21 V DD IF+ R L R L Buffer RF+ RF+ LO+ IF- RF- LO- V BIAS Supply voltage/power 0.8V/0.4mW RF Input/Conversion Gain 1.9GHz/3dB Proc. IEEE EDSSC, Hong Kong, 14-16 December 2003 SSB Noise Figure/IIP3 FoM/Technology 10dB/-11dBm 202dB/0.18μm 22

12 V DD R L R L RF+ IF+ LO+ RF- IF- LO+ Buffer LO- V bias Supply voltage/power RF Input/Conv. Gain Noise Figure/IIP3 FoM/Technology 1V/1mW 2.4GHz/-4dB 10dB/-2dB 202dB/0.18μm Proc. IEEE EDSSC, Hong Kong, 14-16 December 2003 23 Reduce number of off-chip passives Increase amount of integration Reduce number of off-chip passives Small product: Cell phone Cost effective 24

13 Inductor Quality factor PN Diode and MOS Varactor Tuning range Quality factor over tuning range N+ N+ N+ N Well P- Substrate Vias May become a concern as frequencies of RFIC reach the 10s of GHz range IMEC 2003, Microsystems 25 IEEE Spectrum, July 2003 26

14 RF Design, Nov. 2002 27 Issues Substrate noise isolation between noisy digital and low noise analog circuits Cross-talk between sensitive analog circuits Possible Solutions Careful attention to layout Multiple voltage sources Guard rings around noisy digital circuitry Double well and triple well (deep Nwell isolation) 28

15 Noise low frequency and SNR Matching of input stages fluctuation/dispersion effects Technology - t ox, N sub, x j V T, g m, g DS, f T, f MAX Design - L G, W G R G, g m, g DS, f T, f MAX Low-voltage design Voltage distribution across elements between V DD and V SS Modeling in subthreshold Novel circuits required Modeling of passives and improved passives Isolation techniques between digital and analog Design techniques microwave and mm-wave 29 1904 Vacuum tube by Fleming 1906 Solid state Diode by Pickard 1907 Radio Circuits 1920 Super Heterodyne Receiver by Armstrong 1925 Field Effect Device by Lilienfield 1933 FM by Armstrong 1940 Radar 1947 Silicon Transistor by Bardeen, Bratain and Shockley 1950 Color Television 1952 Unipolar Filed Effect Transistor by Shockley 30

16 History of Electronics (Continued) 1956 Silicon Controlled Rectifier by Bell Laboratories 1958 Commercial Thyristor by General Electric 1958 Integrated Circuits by Texas and Fairchild 1968 Op-Amp by Fairchild Semiconductor 1971 4004 Microprocessor by Intel 1972 8 bit Microprocessor by Intel 1995 Gigabit Memory Chip by Intel 31 Transistor Bardeen (Bell Labs) in 1947 Bipolar transistor Schockley in 1949 First bipolar digital logic gate Harris in 1956 First monolithic IC Jack Kilby in 1959 First commercial IC logic gates Fairchild 1960 TTL 1962 into the 1990 s ECL 1974 into the 1980 s 32

17 MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935 CMOS 1960 s, but plagued with manufacturing problems PMOS in 1960 s (calculators) NMOS in 1970 s (4004, 8080) for speed CMOS in 1980 s preferred MOSFET technology because of power benefits BiCMOS, Gallium-Arsenide, Silicon- Germanium SOI, Copper-Low K, 33 Computer Telecommunication Control Military Industrial Etc. 34

18 Classification of Transistors Transistors Bipolar Junction Transistor (BJT) Field Effect Transistor (FET) Insulated Gate Bipolar Transistor (IGBT) NPN PNP Junction FET (JFET) Metal Oxide Semiconductor FET (MOSFET) Depletion MOSFET (D-MOSFET) Enhancement MOSFET (E-MOSFET) MOS 35 36

19 37 Transistors on lead microprocessors double every 2 years 1000 100 2X growth in 1.96 years! Transistors (MT) 10 1 0.1 0.01 0.001 8085 8086 8080 4004 8008 386 286 486 P6 Pentium proc 1970 1980 1990 2000 2010 Courtesy, Year Intel 38

20 human memory human DNA Kbit capacity/chip 100000000 10000000 1000000 100000 10000 1000 100 64 4X growth every 3 years! 1,000 book 4,000 256 1.6-2.4 μm 16,000 1.0-1.2 μm page 0.7-0.8 μm 64,000,000 0.07 μm 16,000,000 0.1 μm 4,000,000 0.13 μm 1,000,000 0.18-0.25 μm 256,000 0.35-0.4 μm 64,000 0.5-0.6 μm encyclopedia 2 hrs CD audio 30 sec HDTV 10 1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010 Year 39 Die size grows by 14% to satisfy Moore s Law 100 Die size (mm) 10 8080 8008 4004 386 8085 8086 286 486 P6 Pentium proc ~7% growth per year ~2X growth in 10 years 1 1970 1980 1990 2000 2010 Year Courtesy, Intel 40

21 Lead microprocessors frequency doubles every 2 years 10000 1000 2X every 2 years Frequency (Mhz) 100 10 1 8085 8080 8086 286 386 486 P6 Pentium proc 0.1 8008 4004 1970 1980 1990 2000 2010 Year Courtesy, Intel 41 Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Mtrans/cm 2 7 14-26 47 115 284 701 Chip size (mm 2 ) 170 170-214 235 269 308 354 Signal pins/chip 768 1024 1024 1280 1408 1472 Clock rate (MHz) 600 800 1100 1400 1800 2200 Wiring levels 6-7 7-8 8-9 9 9-10 10 Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6 High-perf power (W) 90 130 160 170 174 183 Battery power (W) 1.4 2.0 2.4 2.0 2.2 2.4 For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999 doubling every two years) http://www.itrs.net/ntrs/publntrs.nsf 42

22 SYSTEM + MODULE GATE CIRCUIT V in V out S n+ G DEVICE D n+ 43 44

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24 47 Source: Richard Newton 48

25 49 Novel circuits will be needed - deep submicron Higher frequencies, reduced power, improved linearity Lower noise, matching issues, High quality passives at very high frequencies Modeling, design, technology Packaging technology and modeling - integration Several promising new applications are arising Imaging systems and transceiver circuits discussed Intelligent transceiver architectures e.g. radio with a brain RFICs in new technologies RFID tags in polymers/organics Several research issues identified Future applications of RFICs - limited by our imagination and economics--- Nanotechnology 50