EEN689: Special Topics in High-Speed Lins ircuits and Systems Spring 2010 Lecture 21: rosstal Sam Palermo Analog & Mixed-Signal enter Texas A&M University
Announcements HW6 will be posted today and due Wednesday April 7 Exam 2 will be either April 28 or 30 Reading Dally 6.1-6.3 2
Agenda ommon noise sources rosstal ISI 3
ommon Noise Sources Power supply noise Receiver offset rosstal Inter-symbol interference Random noise 4
rosstal rosstal is noise induced by one signal (aggressor) that interferes with another signal (victim) Main crosstal sources oupling between on-chip (capacitive) wires oupling between off-chip (t-line/channel) wires Signal return coupling rosstal is a proportional noise source annot be reduced by scaling signal levels Addressed by using proper signal conventions, improving channel and supply networ, and using good circuit design and layout techniques 5
rosstal to apacitive Lines On-chip wires have significant capacitance to adjacent wires both on same metal layer and adjacent vertical layers Floating victim Examples: Sample-nodes, domino logic When aggressor switches Signal gets coupled to victim via a capacitive voltage divider Signal is not restored [Dally] V c B c V + A O 6
rosstal to Driven apacitive Lines rosstal to a driven line will decay away with a time-constant τ xc O ( ) R + O [Dally] Pea crosstal is inversely proportional to aggressor transition times, t r, and driver strength (1/R O ) V B ( t) t V ( ) B t c exp τ xc Step with Finite Rise Time, t c τ tr xc Ideal Unit Step : τ xc t c 1 exp tr τ xc t t r t exp exp τ xc τ r xc : if if t t < t t r r 7
apacitive rosstal Delay Impact Aggressor transitioning near victim transition can modulate the victim s effective load capacitance This modulates the victim signal s delay, resulting in deterministic jitter [Hodges] Aggressor Static : Aggressor Switching Same Way : Aggressor Switching Opposite Way : L L L gnd gnd + gnd + 2 8
Mitigating apacitive (On-hip) rosstal Adjacent vertical metal layers should be routed perpendicular (Manhattan routing) Limit maximum parallel routing distance Avoid floating signals and use eeper transistors with dynamic logic Maximize signal transition time Trade-off with jitter sensitivity For differential signals, periodically twist routing to mae cross-tal common-mode Separate sensitive signals Use shield wires ouple D signals to appropriate supply 9
Transmission Line rosstal 2 coupled lines: I A I B [Dally] Transient voltage signal on A is coupled to B capacitively dv dt ( x, t) dv ( x t) B A, cx dt where cx + Transient current signal on A is coupled to B through mutual inductance dvb dx ( x, t) V ( x, t) ( x, t) di ( x, t) M dv ( x, t) dv ( x, t) M I A A t dt L A L x A dx lx S A dx where lx M L 10
Near- and Far-End rosstal [Dally] rx fx ( + ) cx 4 ( ) cx 2 lx lx For derivation of rx and fx, see Dally 6.3.2.3 11
Off-hip rosstal Occurs mostly in pacage and boardto-board connectors FEXT is attenuated by channel response and has band-pass characteristic NEXT directly couples into victim and has high-pass characteristic 12
Signal Return rosstal Shared return path with finite impedance Return currents induce crosstal occurs among signals V -V xr [Dally] V xr V Z Z R 0 xr V 13
ommon Noise Sources Power supply noise Receiver offset rosstal Inter-symbol interference Random noise 14
Inter-Symbol Interference (ISI) Previous bits residual state can distort the current bit, resulting in inter-symbol interference (ISI) cursor y ( d ) ( ) ( ) t c d ( t) h( t) post-cursor ISI pre-cursor ISI y (1) (t) sampled relative to pulse pea: [ 0.003 0.036 0.540 0.165 0.065 0.033 0.020 0.012 0.009 ] [ -2 1 0 1 2 3 4 5 6 ] By Linearity: y (0) (t) -1*y (1) (t) 15
Pea Distortion Analysis Example s 0 0 y (1) 0 ( t) 0.540 ( 1 ) ( t T ) y ( t T ) y y < 0 ( 1 ) ( t T ) y ( t T ) > 0 0.007 0.389 ( t) 2( 0.540 0.007 0.389) 0. 288 16
Next Time Noise Sources Timing Noise BER Analysis Techniques 17