I. Digital Integrated Circuits - Logic Concepts

Similar documents
Digital Electronics. Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region. Positive Logic.

Lecture 11 Circuits numériques (I) L'inverseur

Lecture 11 Digital Circuits (I) THE INVERTER

Digital Electronics. Assign Ò1Ó and Ò0Ó to a range of voltage (or current), with a separation that minimizes a transition region.

Lecture 12 - Digital Circuits (I) The inverter. October 20, 2005

Combinational Logic Gates in CMOS

Chapter 6 DIFFERENT TYPES OF LOGIC GATES

Chapter 6 DIFFERENT TYPES OF LOGIC GATES

CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look

Lecture Summary Module 1 Switching Algebra and CMOS Logic Gates

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD?

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Week 9a OUTLINE. MOSFET I D vs. V GS characteristic Circuit models for the MOSFET. Reading. resistive switch model small-signal model

EE 330 Lecture 5. Basic Logic Circuits Complete Logic Family Other Logic Styles. Improved Device Models. complex logic gates pass transistor logic

ECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha

Digital Electronics Part II - Circuits

DIGITAL ELECTRONICS. A2: logic circuits parameters. Politecnico di Torino - ICT school

DIGITAL ELECTRONICS. Digital Electronics - A2 28/04/ DDC Storey 1. Politecnico di Torino - ICT school. A2: logic circuits parameters

ELEC 2210 EXPERIMENT 12 NMOS Logic

5. CMOS Gates: DC and Transient Behavior

EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families

EE100Su08 Lecture #16 (August 1 st 2008)

Digital Microelectronic Circuits ( ) Terminology and Design Metrics. Lecture 2: Presented by: Adam Teman

EE 330 Lecture 5. Basic Logic Circuits Complete Logic Family Other Logic Styles. complex logic gates

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. October 25, 2005

EE 330 Lecture 5. Other Logic Styles. Improved Device Models. complex logic gates pass transistor logic

Experiment 5 Single-Stage MOS Amplifiers

Microelectronics, BSc course

Lecture 4. The CMOS Inverter. DC Transfer Curve: Load line. DC Operation: Voltage Transfer Characteristic. Noise in Digital Integrated Circuits

Digital Circuits Introduction

Digital Integrated Circuits EECS 312

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics

IC Logic Families. Wen-Hung Liao, Ph.D. 5/16/2001

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

Chapter 2 Combinational Circuits

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad

In this experiment you will study the characteristics of a CMOS NAND gate.

Digital Integrated CircuitDesign

Design & Analysis of Low Power Full Adder

ECE315 / ECE515 Lecture 9 Date:

ELEC451 Integrated Circuit Engineering Fall 2009 Solution to CAD Assignment 2 Inverter Voltage Transfer Characteristic (VTC)

Lecture 16: MOS Transistor models: Linear models, SPICE models. Context. In the last lecture, we discussed the MOS transistor, and

Digital Microelectronic Circuits ( ) CMOS Digital Logic. Lecture 6: Presented by: Adam Teman

EE 330 Lecture 5. Other Logic Styles Improved Device Models Stick Diagrams

Propagation Delay, Circuit Timing & Adder Design. ECE 152A Winter 2012

Propagation Delay, Circuit Timing & Adder Design

CHAPTER 8 FIELD EFFECT TRANSISTOR (FETs)

MOS TRANSISTOR THEORY

D n ox GS THN DS GS THN DS GS THN. D n ox GS THN DS GS THN DS GS THN

EE40 Lecture 35. Prof. Chang-Hasnain. 12/5/07 Reading: Ch 7, Supplementary Reader

Electronic Circuits EE359A

Basic Characteristics of Digital ICs

Digital CMOS Logic Circuits

EECE2412 Final Exam. with Solutions

Written Examination on. Wednesday October 17, 2007,

Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits

8. Combinational MOS Logic Circuits

DIGITAL VLSI LAB ASSIGNMENT 1

ECE 301 Digital Electronics

Lecture 13. Biasing and Loading Single Stage FET Amplifiers. The Building Blocks of Analog Circuits - III

CMOS VLSI Design (A3425)

CMOS VLSI Design (A3425)

Reading. Lecture 17: MOS transistors digital. Context. Digital techniques:

Field Effect Transistors (FET s) University of Connecticut 136

Digital Integrated CircuitDesign

Electronics Basic CMOS digital circuits

problem grade total

Problem Points Score Grader Total 100

The CMOS Inverter. Lecture 3a Static properties (VTC and noise margins)

Gechstudentszone.wordpress.com

Designing Information Devices and Systems II Fall 2017 Note 1

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Lecture 02: Logic Families. R.J. Harris & D.G. Bailey

Microelectronics Circuit Analysis and Design

ELEC 350L Electronics I Laboratory Fall 2012

Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor

Topic 2. Basic MOS theory & SPICE simulation

Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor

ECE380 Digital Logic. Logic values as voltage levels

UNISONIC TECHNOLOGIES CO., LTD CD4069

M74HCT04. Hex inverter. Features. Description

EE 330 Lecture 5. Improved Device Models Propagation Delay in Logic Circuits

ENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits

EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

Chapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

EE 330 Lecture 44. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

Digital circuits. Bởi: Sy Hien Dinh

CMOS LOGIC Inside the CMOS inverter, no I D current flows through transistors when input is logic 1 or logic 0, because

Lecture Summary Module 1 Switching Algebra and CMOS Logic Gates

Adaptive Power MOSFET Driver 1

55:041 Electronic Circuits

CHAPTER 6 DIGITAL CIRCUIT DESIGN USING SINGLE ELECTRON TRANSISTOR LOGIC

EE311: Electrical Engineering Junior Lab, Fall 2006 Experiment 4: Basic MOSFET Characteristics and Analog Circuits

Design considerations (D)

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)

6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers

VLSI Design I; A. Milenkovic 1

Transcription:

I. Digital Integrated Circuits - Logic Concepts. Logic Fundamentals: binary mathematics: only operate on and (oolean algebra) simplest function -- inversion = symbol for the inverter INPUT OUTPUT EECS 6.2 Spring 998 Lecture

. Other Logic Functions ND and NND = not ND OR and NOR = not OR XOR ND NND INPUT OUTPUT ND NND OR NOR (a) INPUT OUTPUT OR NOR (b) INPUT OUTPUT XOR (c) One gate can have many inputs C = C XZ Practical limitations... set by need to maintain both adequate switching speed and valid logic levels fan-in -- maximum number logic gates connected to the input fan-out -- maximum number of logic gates connected to the output EECS 6.2 Spring 998 Lecture

C. n Ideal Inverter Let the logical variable be represented by a voltage. Let the correspond to a high voltage (say, 5 V) and the correspond to the low voltage (say, V). Voltage transfer curve for an inverter yields V when a high voltage is input and the high voltage,, when a low voltage is input. > = / 2 --> = < = / 2 --> = The ideal inverter returns correct logical outputs ( V or ) even when the input voltage is corrupted by noise, voltage spikes, etc. which are nearly half the supply voltage! + + = /2 V M = 2 (a) (b) EECS 6.2 Spring 998 Lecture

D. Real Inverters Inverters which we can build are approximations to the ideal inverter. typical inverter characteristic is: X = IN V IL V IH On the output and input axes, several voltages are defined: = input voltage for which = = voltage output low = max. output voltage for a valid = voltage output high = min. output voltage for a valid V IL = voltage input low = smaller input voltage where slope equals - V IH = voltage input high = larger input voltage where slope equals - X = for = V; usually, X =, the supply voltage IN = for = and is the minimum output voltage EECS 6.2 Spring 998 Lecture

E. Inverter Transfer Function - Hand Calculations Problem: evaluating where slope = - is an algebraic mess. dopt more convenient definitions of, V IL,V IH (new in H&S) = X Slope v = IN V IL V IH Use small-signal model to evaluate tangent to transfer curve = IN and = X = Input voltage at which = V IL = intersection of tangent to ( ) curve at and the line = X (=, typically) V IH = intersetion of tangent to ( ) curve at and the line = IN (= V, typically) If <V IL, then is considered a valid If >V IH, then is considered a valid EECS 6.2 Spring 998 Lecture

F. Noise Margins Cascade of two logic inverters-- output of # is input to #2 Output of inverter # is at least, Margin of - V IH2 to spare before the input to inverter #2 has an invalid high input. NM H = - V IH = noise margin (high) NM L = V IL - = noise margin (low) v NOISE 2 2 V IH NM H V IH2 Voltage V IL NM L V IL2 2 NM H = V IH NM L = V IL EECS 6.2 Spring 998 Lecture

G. Propagation Delay Time is required for an inverter to change states from to and vice versa Charging and discharging MOSFET and parasitic capacitance 9% 5% % t t R t F t PHL t PLH 9% 5% % t t t F R t CCLE Definitions:t R = risetime; t F = falltime -- both % to 9% of total swing t PHL = delay between 5% points on the input and output waveforms during the high-to-low transition t PLH = delay between 5% points on the input and output waveforms during the low-to-high transition EECS 6.2 Spring 998 Lecture

H. Propagation Delay - Hand Calculations For hand calculations, make the input waveform ideal Find delay in the output waveform before it reaches the 5% point. t CCLE t t PHL t PLH VOH 5% t CCLE t Transient analysis can only be roughly approximated in hand calculations SPICE is essential for accurate analysis. EECS 6.2 Spring 998 Lecture

II. Inverter Circuits: NMOS-Resistor Load. MOSFET is an excellent switch: open-circuit at control terminal (gate) drain-source connection is open for V GS < V Tn (cutoff region) drain-source connection is a resistor for V GS >V Tn (triode region). Qualitative Circuit Operation V DD R + C L _ = V DD = 5 V (typically) C L = load capacitance (from interconnections and from other inverters connected to the output V S = V -- bulk-to-source short circuit is typically not shown < V Tn MOSFET-OFF --- = V DD >> V Tn MOSFET - ON --- is small ( value is set by resistive divider) EECS 6.2 Spring 998 Lecture

C. Quantitative Calculation of Transfer Characteristic Key concept: the static output current is zero MOSFET drain current = I D = I R = current through resistor = = = V V DD OUT I I D R ----------------------------- R V --------- DD R -- V R OUT Plotting these equations on the drain characteristics of the MOSFET since V DS = : I D V DD R V DD The transfer characteristic can be found by plotting the intersections between the I D (, ) characteristics with the load line I R ( ) EECS 6.2 Spring 998 Lecture

D. Transfer Characteristic IN V IL V IH E. Small Signal Model Use small signal model to calculate the gain v out /v in at Gain is the slope of the inverter transfer characteristic at Gain =v out /v in = -g m (r o R) -g m R EECS 6.2 Spring 998 Lecture