Applications l l l l Switch Mode Power Supply (SMPS) Uninterruptible Power Supply High Speed Power Switching Lead-Free SMPS MOSFET PD - 9546 HEXFET Power MOSFET V DSS R DS(on) max I D 650V 0.93Ω 8.5A Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current TO-220AB Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 8.5 I D @ T C = C Continuous Drain Current, V GS @ V 5.4 A I DM Pulsed Drain Current ˆ 2 P D @T C = 25 C Power Dissipation 67 W Linear Derating Factor.3 W/ C V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒˆ 2.8 V/ns T J Operating Junction and -55 to 50 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torqe, 6-32 or M3 screw lbf in (.N m) Typical SMPS Topologies l Single Transistor Flyback l Single Transistor Forward Notes through are on page 8 www.irf.com 06/6/04
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 650 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.67 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 0.93 Ω V GS = V, I D = 5..A V GS(th) Gate Threshold Voltage 2.0 4.0 V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 25 V µa DS = 650V, V GS = 0V 250 V DS = 520V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage V GS = 30V na Gate-to-Source Reverse Leakage - V GS = -30V Dynamic @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 3.9 S V DS = 50V, I D = 3.Aˆ Q g Total Gate Charge 48 I D = 5.2A Q gs Gate-to-Source Charge 2 nc V DS = 400V Q gd Gate-to-Drain ("Miller") Charge 9 V GS = V, See Fig. 6 and 3 ˆ t d(on) Turn-On Delay Time 4 V DD = 325V t r Rise Time 20 ns I D = 5.2A t d(off) Turn-Off Delay Time 34 R G = 9.Ω t f Fall Time 8 R D = 62Ω,See Fig. ˆ C iss Input Capacitance 47 V GS = 0V C oss Output Capacitance 77 V DS = 25V C rss Reverse Transfer Capacitance 7.0 pf ƒ =.0MHz, See Fig. 5ˆ C oss Output Capacitance 92 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 48 V GS = 0V, V DS = 520V, ƒ =.0MHz C oss eff. Effective Output Capacitance 84 V GS = 0V, V DS = 0V to 520V ˆ Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 325 mj I AR Avalanche Current 5.2 A E AR Repetitive Avalanche Energy 6 mj Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 5.2 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 2 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.5 V T J = 25 C, I S = 5.2A, V GS = 0V t rr Reverse Recovery Time 493 739 ns T J = 25 C, I F = 5.2A Q rr Reverse RecoveryCharge 2. 3.2 µc di/dt = A/µs ˆ t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2 www.irf.com
I D, Drain-to-Source Current (A) VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V I D, Drain-to-Source Current (A) VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 4.5V T J = 25 C 0. 0. V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 50 C 0. V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) T J = 50 C T J = 25 C V DS= V 20µs PULSE WIDTH 0. 4.0 5.0 6.0 7.0 8.0 9.0 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.0 I D = 5.2A 2.5 2.0.5.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 20 40 60 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance (pf) 2000 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd 600 C oss = C ds Cgd C iss 200 C oss 800 400 C rss 0 A 0 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 20 6 2 8 4 I = D 5.2A V DS = 400V 520V V DS = 325V V DS = 30V FOR TEST CIRCUIT SEE FIGURE 3 0 0 20 30 40 50 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) T J = 50 C T J = 25 C V GS = 0 V 0. 0.2 0.4 0.6 0.8.0.2 V SD,Source-to-Drain Voltage (V) I D, Drain Current (A) OPERATION IN THIS AREA LIMITED BY R DS(on) us us ms ms TC = 25 C TJ = 50 C Single Pulse 0. 0 00 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
.0 V DS R D I D, Drain Current (A) 8.0 6.0 4.0 2.0 Fig a. Switching Time Test Circuit V DS 90% R G V GS V Pulse Width µs Duty Factor 0. % D.U.T. - V DD 0.0 25 50 75 25 50 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 PDM t 0.02 SINGLE PULSE t2 0.0 (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 0.0 2. Peak T J = P DM x Z thjc TC 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
5V V DS L DRIVER R G D.U.T I AS - V DD A 20V tp 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS tp E AS, Single Pulse Avalanche Energy (mj) 800 600 400 200 I D TOP 2.3A 3.3A BOTTOM 5.2A 0 25 50 75 25 50 Starting T, Junction Temperature ( J C) I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy Vs. Drain Current V Q GS Q GD 800 V G 2V Current Regulator Same Type as D.U.T..2µF 50KΩ.3µF Charge Fig 3a. Basic Gate Charge Waveform V DSav, Avalanche Voltage (V) 780 760 740 720 V GS 3mA D.U.T. V - DS 700 0 2 3 4 5 6 I av, Avalanche Current (A) A I G I D Current Sampling Resistors Fig 2d. Typical Drain-to-Source Voltage Fig 3b. Gate Charge Test Circuit Vs. Avalanche Current 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFET Power MOSFETs www.irf.com 7
TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.3).54 (.45).29 (.405) 3.78 (.49) 3.54 (.39) - A - 4.69 (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) 4 2 3 6.47 (.255) 6. (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LEAD ASSIGNMENTS LEAD ASSIGNMENTS HEXFET IGBTs, CoPACK - GATE - GATE 2 - DRAIN - GATE 2- DRAIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRAIN 3- EMITTER 4- DRAIN 4- COLLECTOR 0.93 (.037) 3X 0.55 (.022) 0.69 (.027) 3X.40 (.055) 0.46 (.08) 3X.5 (.045) 0.36 (.04) M B A M 2.92 (.5) 2.64 (.4) 2.54 (.) 2X NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: T HIS IS AN IR F LOT CODE 789 AS S EMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INT E RNAT IONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ) Starting T J = 25 C, L = 24mH R G = 25Ω, I AS = 5.2A. (See Figure 2) ƒ I SD 5.2A, di/dt 90A/µs, V DD V (BR)DSS, T J 50 C Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS Uses IRFIB5N65A data and test conditions Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information. 06/04 8 www.irf.com