Applications l High Frequency Point-of-Load Synchronous Buck Converter for Applications in Networking & Computing Systems. l Lead-Free Benefits l Very Low R DS(on) at 4.5V V GS l Low Gate Charge l Fully Characterized Avalanche Voltage and Current HEXFET Power MOSFET V DSS R DS(on) max Q g (typ.) 30V 9.1mW@V GS = V 9.3nC A 1 8 S D S S G 2 3 4 7 6 5 D D D Top View SO-8 PD - 95213A Absolute Maximum Ratings Parameter Max. Units V DS Drain-to-Source Voltage 30 V V GS Gate-to-Source Voltage ± 20 I D @ T A = 25 C Continuous Drain Current, V GS @ V 13.6 I D @ T A = 70 C Continuous Drain Current, V GS @ V 11 A I DM Pulsed Drain Current c P D @T A = 25 C Power Dissipation f 2.5 W P D @T A = 70 C Power Dissipation f 1.6 Linear Derating Factor 0.02 W/ C T J Operating Junction and -55 to 155 C T STG Storage Temperature Range Thermal Resistance Parameter Typ. Max. Units R θjl Junction-to-Drain Lead g 20 C/W R θja Junction-to-Ambient fg 50 Notes through are on page www.irf.com 1 05/23/07
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 30 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient 0.025 V/ C R DS(on) Static Drain-to-Source On-Resistance 7.0 9.1 mω 9.5 12.5 V GS(th) Gate Threshold Voltage 1.0 V V GS(th) Gate Threshold Voltage Coefficient - 4.9 mv/ C I DSS Drain-to-Source Leakage Current 1.0 µa V DS = 24V, V GS = 0V 150 V DS = 24V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage na V GS = 20V Gate-to-Source Reverse Leakage - V GS = -20V gfs Forward Transconductance 22 S V DS = 15V, I D = A Q g Total Gate Charge 9.3 14 Q gs1 Pre-Vth Gate-to-Source Charge 2.5 V DS = 15V Q gs2 Post-Vth Gate-to-Source Charge 0.8 nc V GS = 4.5V Q gd Gate-to-Drain Charge 2.9 I D = A Q godr Gate Charge Overdrive 3.1 See Fig. 16 Q sw Switch Charge (Q gs2 Q gd ) 3.7 Q oss Output Charge 6.1 nc V DS = V, V GS = 0V t d(on) Turn-On Delay Time 6.3 V DD = 15V, V GS = 4.5V e t r Rise Time 2.7 I D = A t d(off) Turn-Off Delay Time 9.7 ns Clamped Inductive Load t f Fall Time 7.3 C iss Input Capacitance V GS = 0V C oss Output Capacitance 360 pf V DS = 15V C rss Reverse Transfer Capacitance 1 ƒ = 1.0MHz Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy dh 44 mj I AR Avalanche Current c A Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 3.1 (Body Diode) A I SM Pulsed Source Current (Body Diode)ch V SD Diode Forward Voltage 1.0 V t rr Reverse Recovery Time 28 42 ns Q rr Reverse Recovery Charge 23 35 nc Conditions V GS = 0V, I D = 250µA Reference to 25 C, I D = 1mA V GS = V, I D = 13A e V GS = 4.5V, I D = A e V DS = V GS, I D = 250µA Conditions MOSFET symbol showing the integral reverse p-n junction diode. T J = 25 C, I S = A, V GS = 0V e T J = 25 C, I F = A, V DD = 20V di/dt = A/µs e 2 www.irf.com
I D, Drain-to-Source Current (Α) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) VGS TOP V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V VGS TOP V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V 1 2.5V 2.5V 0.1 20µs PULSE WIDTH Tj = 25 C 0.1 1 V DS, Drain-to-Source Voltage (V) 1 20µs PULSE WIDTH Tj = 150 C 0.1 1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics.0 T J = 150 C 2.0 I D = 13A V GS = V.0 1.5 T J = 25 C 1.0 1.0 V DS = 15V 20µs PULSE WIDTH 0.1 2.0 3.0 4.0 5.0 6.0 V GS, Gate-to-Source Voltage (V) 0.5-60 -40-20 0 20 40 60 80 120 140 160 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance (pf) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) V GS, Gate-to-Source Voltage (V) 00 V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 12 I D = A V DS = 24V VDS= 15V 0 Ciss 8 Coss 6 Crss 4 2 1 V DS, Drain-to-Source Voltage (V) 0 0 5 15 20 Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage.0 0 OPERATION IN THIS AREA LIMITED BY R DS (on).0 T J = 150 C µsec 1.0 T J = 25 C V GS = 0V 0.1 0.0 0.5 1.0 1.5 V SD, Source-toDrain Voltage (V) 1msec 1 msec Tc = 25 C Tj = 150 C Single Pulse 0.1 0.1 1.0.0.0 0.0 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
Thermal Response ( Z thja ) I D, Drain Current (A) V GS(th) Gate threshold Voltage (V) 14 2.6 12 2.2 8 6 1.8 I D = 250µA 4 2 1.4 0 25 50 75 125 150 T J, Junction Temperature ( C) 1.0-75 -50-25 0 25 50 75 125 150 T J, Temperature ( C ) Fig 9. Maximum Drain Current Vs. Case Temperature Fig. Threshold Voltage Vs. Temperature D = 0.50 1 0.20 0. 0.05 0.02 0.01 0.1 SINGLE PULSE ( THERMAL RESPONSE ) 0.01 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 t 1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient www.irf.com 5
R DS (on), Drain-to -Source On Resistance ( mω) E AS, Single Pulse Avalanche Energy (mj) 30 25 20 I D = 13A 80 I D TOP 4.5A 8.0A BOTTOM A 60 15 T J = 125 C 40 5 T J = 25 C 20 0 2.0 4.0 6.0 8.0.0 V GS, Gate-to-Source Voltage (V) Fig 12. On-Resistance Vs. Gate Voltage 0 25 50 75 125 150 Starting T J, Junction Temperature ( C) Fig 13c. Maximum Avalanche Energy Vs. Drain Current 15V V DS L D V DS L DRIVER V DD D.U.T R G 20V V GS tp D.U.T IAS 0.01Ω - V DD A V GS Pulse Width < 1µs Duty Factor < 0.1% Fig 13a. Unclamped Inductive Test Circuit Fig 14a. Switching Time Test Circuit tp V (BR)DSS V DS 90% % V GS I AS t d(on) t f t d(off) t r Fig 13b. Unclamped Inductive Waveforms Fig 14b. Switching Time Waveforms 6 www.irf.com
- D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Current Regulator Same Type as D.U.T. Vds Id 50KΩ Vgs 12V.2µF.3µF D.U.T. V - DS Vgs(th) V GS 3mA I G I D Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Test Circuit Fig 17. Gate Charge Waveform www.irf.com 7
Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) I Q gd V in f I Q gs 2 V in f i g ( ) Q g V g f Q oss 2 V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs1 and Q gs2, can be seen from Fig 16. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. i g Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ( ) P loss = I rms 2 R ds(on) ( ) Q g V g f Q oss 2 V f in Q V f rr in *dissipated primarily in Q1. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. As Q1 turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Q oss Characteristic 8 www.irf.com
SO-8 Package Details Dimensions are shown in milimeters (inches) ' % $ ( >@ $ ; H ' ( H H. / \,1&(6 0,//,0(7(56 ',0 0,1 0$; 0,1 0$; $ $ E F %$6,& %$6,& %$6,& ƒ ƒ %$6,& ƒ ƒ H $.[ƒ & \ ;E $ >@ ;/ ;F >@ & $ % 127(6 ',0(16,21,1* 72/(5$1&,1*3(5$60(<0 &21752//,1*',0(16,2,//,0(7(5 ',0(16,216$5(62:1,,//,0(7(56>,1&(6@ 287/,1(&21)250672-('(&287/,1(06$$ ',0(16,21'2(6127,1&/8'(02/'3527586,216 02/'3527586,21612772(;&(('>@ ',0(16,21'2(6127,1&/8'(02/'3527586,216 02/'3527586,21612772(;&(('>@ ',0(16,21,67(/(1*72)/($')2562/'(5,1*72 $68%675$7( SO-8 Part Marking >@ ;>@ )22735,17 ;>@ ;>@ (;$03/(7,6,6$1,5)026)(7,17(51$7,21$/ 5(&7,),(5 /2*2 ) ;;;; '$7(&2'(<:: 3 '(6,*1$7(6/($')5(( 352'8&7237,21$/ < /$67',*,72)7(<($5 :: :((. $ $66(0%/<6,7(&2'( /27&2'( 3$57180%(5 www.irf.com 9
SO-8 Tape and Reel Dimensions are shown in milimeters (inches) TERMINAL NUMBER 1 12.3 (.484 ) 11.7 (.461 ) 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 330.00 (12.992) MAX. NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.87mH R G = 25Ω, I AS = A. ƒ Pulse width 400µs; duty cycle 2%. When mounted on 1 inch square copper board R θ is measured at T J approximately 90 C 14.40 (.566 ) 12.40 (.488 ) Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information.05/2007 www.irf.com