.-Amp Output Current IGBT Gate Driver Optocoupler Description The ACPL-P/W consists of a GaAsP LED optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate-controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving small or medium power IGBTs. Applications Isolated IGBT/Power MOSFET gate drive AC and brushless DC motor drives Industrial inverters Inverter for home appliances Induction cooker Switching power supplies (SPSs) Features High-speed response Ultra high CMR Bootstrappable supply current Available in Stretched SO- package Package clearance/creepage at 8 mm (ACPL-W) Safety approval: UL77 recognized with 7 Vrms for minute for ACPL-P and Vrms for minute for ACPL-W CSA Approved IEC/EN/DIN EN 77-- Approved V IORM = 89 Vpeak for ACPL-P V IORM = Vpeak for ACPL-W Specifications.-A maximum peak output current.-a minimum peak output current.7-μs maximum propagation delay over temperature range I CC(max) = -ma maximum supply current kv/μs minimum common mode rejection (CMR) at V CM = V Wide V CC operating range: V to V over temperature range Wide operating temperature range: C to C CAUTION It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments. - -
Functional Diagram ANODE V CC N.C. V O CATHODE SHIELD V EE NOTE A.-μF bypass capacitor must be connected between pins V CC and VEE. Truth Table LED OFF ON VO LOW HIGH Ordering Information ACPL-P is UL Recognized with 7 Vrms for minute per UL77. ACPL-W is UL Recognized with Vrms for minute per UL77. Part Number Option RoHS Compliant Package Surface Mount Tape and Reel UL Vrms / Minute Rating IEC/EN/DIN EN 77-- Quantity ACPL-P -E Stretched SO- X per tube -E X X per reel -E X X per tube -E X X X per reel ACPL-W -E Stretched SO- X X per tube -E X X X per reel -E X X X per tube -E X X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-P-E to order product of Stretched SO- Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 77-- Safety Approval in RoHS compliant. Example : ACPL-P-E to order product of Stretched SO- Surface Mount package in tube packaging and RoHS compliant. Option data sheets are available. Contact your sales representative or authorized distributor for information. NOTE The notation #XXX is used for existing products, while (new) products launched since July, and RoHS compliant option will use -XXXE. - -
Package Outline Drawings ACPL-P Stretched SO- Package.8 ±.7 (. ±.).7 (.) BSG *.8 +..8 +.. ( ) Land Pattern Recommendation.7 (.).7 (.). (.8) 7. (.).8 (.8) 7.9 ±.7 (. ±.).7 (.).8 ±.7 (. ±.). (.8) 7 7. ±. (.8 ±.) ±. (. ±.) 7 NOM. 9.7 ±. (.8 ±.). ±. (. ±.) Floating Lead Protusions max.. (.) Dimensions in Millimeters (Inches) Lead Coplanarity =. mm (. Inches) * Total Package Length (inclusive of mold flash).8 ±. (.9 ±.) - -
ACPL-W Stretched SO- Package.8 ±.7 (. ±.).7 (.) BSG *.8 +..8 +.. ( ) Land Pattern Recommendation.7 (.).7 (.).87 +.7.8 +.. ( ) 7. (.). (.).9 (.7). (.8) 7.9 ±.7 (. ±.).8 ±.7 (. ±.) 7. ±. (.8 ±.).7 ±. (.9 ±.) 7. ±. (. ±.) 7 NOM.. ±. (. ±.) Floating Lead Protusions max.. (.) Dimensions in Millimeters (Inches) Lead Coplanarity =. mm (. Inches) * Total Package Length (inclusive of mold flash).8 ±. (.9 ±.) Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD- (latest revision). Non-halide flux should be used. Regulatory Information The ACPL-P/W is approved by the following organizations. IEC/EN/DIN EN 77-- (Option only) UL Approval under IEC 77--:7. Approval under UL 77 component recognition program up to V ISO = 7 V RMS for the ACPL-P and V ISO = V RMS for the ACPL-W, File E. CSA Approval under CSA Component Acceptance Notice #, File CA 88. - -
IEC/EN/DIN EN 77-- Insulation Related Characteristics a (ACPL-P/W Option ) Description Symbol ACPL-W ACPL-P Unit Installation Classification per DIN VDE /.89, Table For Rated Mains Voltage Vrms For Rated Mains Voltage Vrms For Rated Mains Voltage Vrms For Rated Mains Voltage Vrms For Rated Mains Voltage Vrms I-IV I-IV I-IV I-IV I-III I-IV I-IV I-III I-III Climatic Classification // // Pollution Degree (DIN VDE /.89) Maximum Working Insulation Voltage V IORM 89 V peak Input to Output Test Voltage, Method b a V IORM.87 = V PR, % Production Test with t m = s, Partial Discharge < pc Input to Output Test Voltage, Method a a V IORM. = V PR, Type and Sample Test, t m = s, Partial Discharge < pc V PR 7 7 V peak V PR 8 V peak Highest Allowable Overvoltage* (Transient Overvoltage, t ini = s) V IOTM 8 V peak Safety Limiting Values (maximum values allowed in the event of a failure) Case Temperature Input Current b Output Power b T S I S,INPUT P S,OUTPUT 7 7 C ma mw Insulation Resistance at T S, V IO = V R S 9 9 Ω a. Refer to IEC/EN/DIN EN 77-- Optoisolator Safety Standard section of the Regulatory Guide to Isolation Circuits, AV-EN, for a detailed description of Method a and Method b partial discharge test profiles. b. Refer to the following figure for dependence of P S and I S on ambient temperature: OUTPUT POWER P S, INPUT CURRENT I S 8 7 P S (mw) I S (ma) 7 7 T S CASE TEMPERATURE C - -
Insulation and Safety-Related Specifications Parameter Symbol P ACPL- W Unit Conditions Minimum External Air Gap (External Clearance) L() 7. 8. mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) L() 8. 8. mm Measured from input terminals to output terminals, shortest distance path along body..8.8 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Minimum Internal Tracking (Internal Creepage) N/A N/A mm Measured from input terminals to output terminals, along internal cavity. Tracking Resistance (Comparative Tracking CTI >7 >7 V DIN IEC /VDE Part. Index) Isolation Group IIIa IIIa Material Group (DIN VDE, /89, Table ). NOTE All data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered (the recommended land pattern does not necessarily meet the minimum creepage of the device). There are recommended techniques such as grooves and ribs that may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors, such as pollution degree and insulation level. - -
Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Note Storage Temperature T S C Operating Temperature T A C Average Input Current I F(AVG) ma a Peak Transient Input Current (< μs pulse width, pps) I F(TRAN). A Reverse Input Voltage V R V High Peak Output Current I OH(PEAK). A b Low Peak Output Current I OL(PEAK). A b Supply Voltage V CC V EE. V Output Voltage V O(PEAK). V CC V Output Power Dissipation P O mw c Input Power Dissipation P I mw d Lead Solder Temperature Solder Reflow Temperature Profile C for s.,. mm below seating plane See Package Outline Drawings section. a. Derate linearly above 7 C free air temperature at a rate of. ma/ C. b. Maximum pulse width = ms, maximum duty cycle =.%. This value is intended to allow for component tolerances for designs with I O peak minimum =.A. See Applications Information section for additional details on limiting I OL peak. c. Derate linearly above 8 C, free air temperature at the rate of. mw/ C. d. Input power dissipation does not require derating. Recommended Operating Conditions Parameter Symbol Min. Max. Unit Note Power Supply V CC V EE V Input Current (ON) I F(ON) 8 ma Input Voltage (OFF) V F(OFF)..8 V Operating Temperature T A C - 7 -
Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified. Parameter Symbol Min. Typ. Max. Unit Test Conditions Figure Note High Level Output Current I OH. A V O = V CC a a. Maximum pulse width = ms, maximum duty cycle =.%... A V O = V CC b Low Level Output Current I OL.. A V O = V EE +. a.. A V O = V EE + b High Level Output Voltage V OH V CC V CC.8 V I O = ma c, d Low Level Output Voltage V OL. V I O = ma High Level Supply Current I CCH.7 ma I F = ma 7, 8 e Low Level Supply Current I CCL. ma I F = ma 7, 8 e Threshold Input Current Low to High I FLH 7 ma I O = ma, V O > V 9, Threshold Input Voltage High to Low V FHL.8 V I O = ma, V O > V Input Forward Voltage V F...8 V I F = ma Temperature Coefficient of Input Forward ΔV F /ΔT A. mv/ C I F = ma Voltage Input Reverse Breakdown Voltage BV R V I R = μa Input Capacitance C IN pf f = MHz, V F = V b. Maximum pulse width = ms, maximum duty cycle =.%. This value is intended to allow for component tolerances for designs with I O peak minimum =.A. See the Applications section for additional details on limiting I OL peak. c. In this test, V OH is measured with a DC load current. When driving capacitive load, V OH approaches V CC as I OH approaches zero amps. d. Maximum pulse width = ms, maximum duty cycle = %. e. The power supply current increases when operating frequency and Q g of the driven IGBT increases. - 8 -
Switching Specifications (AC) Over recommended operating conditions unless otherwise specified. Parameter Symbol Min. Typ. Max. Unit Test Conditions Figure Note Propagation Delay Time to High Output Level t PLH...7 μs R g = 7Ω, C g = nf, f = khz, Duty Cycle = %, a. This load condition approximates the gate load of a V/A IGBT.,,,,, 7 Propagation Delay Time to Low Output Level t PHL...7 μs a I F = 8 ma, Propagation Delay Difference Between Any PDD.. μs b V CC = V Two Parts or Channels Rise Time t R ns Fall Time t F ns Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity CM H kv/μs T A = C, V CM = V b. PDD is the difference between t PHL and t PLH between any two parts or channels under the same test conditions. a 8 c CM L kv/μs 8 d c. Common mode transient immunity in the high state is the maximum tolerable dv CM /dt of the common mode pulse V CM to ensure that the output remains in the high state (that is, V O >.V). d. Common mode transient immunity in a low state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to ensure that the output remains in a low state (that is, V O <.V). Package Characteristics Parameter Symbol Min. Typ. Max. Unit Test Conditions Figure Note Input-Output Momentary Withstand Voltage ACPL-P V ISO 7 Vrms T A = C, RH < % for min. ACPL-W b, c a, b Input-Output Resistance R I-O V I-O = V b Input-Output Capacitance C I-O. pf Freq = MHz a. In accordance with UL 77, each optocoupler is proof tested by applying an insulation test voltage > V rms for second (leakage detection current limit I I-O < μa). This test is performed before % production test for partial discharge (method B) shown in the IEC/EN/DIN EN 77-- Insulation Related Characteristics a (ACPL-P/W Option ) table, if applicable. b. The device is considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. c. In accordance with UL 77, each optocoupler is proof tested by applying an insulation test voltage > V rms for second (leakage detection current limit I I-O < A). This test is performed before % production test for partial discharge (method B) shown in the IEC/EN/DIN EN 77-- Insulation Related Characteristics a (ACPL-P/W Option ) table, if applicable. - 9 -
Figure V OH vs. Temperature Figure I OH vs. Teperature. (V OH -V CC ) HIGH OUTPUT VOLTAGE DROP V -. -. -. -. I OH OUTPUT HIGH CURRENT A.8... -. - - 7. - - 7 T A TEMPERATURE C T A TEMPERATURE C Figure V OH vs. I OH Figure V OL vs. Temperature. V OL OUTPUT LOW VOLTAGE V.....9 - - 7 T A TEMPERATURE C Figure I OL vs. Temperature Figure V OL vs. I OL.7 I OL OUTPUT LOW CURRENT A..... V OL OUTPUT LOW VOLTAGE V. - - 7 7 T A TEMPERATURE C I OL OUTPUT LOW CURRENT ma - -
Figure 7 I CC vs. Temperature Figure 8 I CC vs. V CC.... I CC SUPPLY CURRENT ma..8... I CC L I CC H I CC SUPPLY CURRENT ma.8... I CC L I CC H - - 7 T A TEMPERATURE C V CC SUPPLY VOLTAGE V Figure 9 I FLH vs. Temperature. Figure Propagation Delay vs. V CC I FLH LOW TO HIGH CURRENT THRESHOLD ma.... - - 7 T A TEMPERATURE C T P PROPAGATION DELAY ns V CC SUPPLY VOLTAGE V T PLH T PHL Figure Propagation Delay vs. I F Figure Propagation Delay vs. Temperature T P PROPAGATION DELAY ns T P PROPAGATION DELAY ns T PLH T PHL 9 I F FORWARD LED CURRENT ma 8 - - 7 T A TEMPERATURE C - -
Figure Propagation Delay vs. Rg Figure Propagation Delay vs. Cg T P PROPAGATION DELAY ns T PLH T PHL T P PROPAGATION DELAY ns T PLH Rg SERIES LOAD RESISTANCE W T PHL 8 Cg LOAD CAPACITANCE nf Figure Transfer Characteristics Figure Input Current vs. Forward Voltage V O OUTPUT VOLTAGE V I F FORWARD CURRENT ma -....8 I F FORWARD LED CURRENT ma V F FORWARD VOLTAGE V Figure 7 Propagation Delay Test Circuit and Waveforms I F = 7 to ma I F. F t r t f + V O V = + - - CC to V KHz 7 % DUTY nf CYCLE V OUT 9% % % t PLH t PHL - -
Figure 8 CMR Test Circuit and Waveforms I F V CM V A B. F + V O + - - V CC = V V t V V CM = t t V O V OH + - V CM = V SWITCH AT A: I F = ma V O SWITCH AT B: I F = ma V OL Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the ACPL-P/W has a very low maximum V OL specification of.v. Minimizing R g and the lead inductance from the ACPL-P/W to the IGBT gate and emitter (possibly by mounting the ACPL-P/W on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 9. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the ACPL-P/W input as this can result in unwanted coupling of transient signals into the input of ACPL-P/W and degrade performance. (If the IGBT drain must be routed near the ACPL-P/W input, then the LED should be reverse biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the ACPL-P/W.) Selecting the Gate Resistor (Rg) Step : Calculate Rg minimum from the I OL peak specification. The IGBT and Rg in Figure 9 can be analyzed as a simple RC circuit with a voltage supplied by the ACPL-P/W. R g VCC = I V OLPEAK =. = OL The V OL value of V in the previous equation is the V OL at the peak current of.a. (See Figure ). Figure 9 Recommended LED Drive and Application Circuit for ACPL-P/W + V 7 ACPL-P/W. F + - V CC = V + HVDC CONTROL INPUT 7XXX OPEN COLLECTOR R g Q -PHASE AC Q -HVDC - -
Step : Check the ACPL-P/W power dissipation and increase R g if necessary. The ACPL-P/W total power dissipation (P T ) is equal to the sum of the emitter power (P E ) and the output power (P O ). P P P T E O = P E + P = I F V F DutyCycle = P O(BIAS) + P O(SWITCHING) = ICC V CC + E SW (R g; Q g ) f = (I + K Q f ) V + E (R ; Q ) f CCBIAS O ICC g CC where K ICC Q g f is the increase in I CC due to switching and K ICC is a constant of. ma/(nc*khz). For the circuit in Figure 9 with I F (worst case) = ma, R g = Ω, Max Duty Cycle = 8%, Q g = nc, f = khz, and T AMAX = 8 C: P P E O = ma.8v.8 = mw = ( ma + (. ma/nc khz) khz nc) V +. J khz = 8 mw < mw ( P @8 C) The value of ma for I CC in the previous equation is the max. I CC over entire operating temperature range. Since P O for this case is less than P O(MAX), R g = Ω is alright for the power dissipation. SW g O(MAX) g LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure. The ACPL-P/W improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 8 as shown in Figure. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 9) can achieve kv/μs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. Figure Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers Figure Energy Dissipated in the ACPL-P/W and for Each IGBT Switching Cycle C LEDP Esw ENERGY PER SWITCHING CYCLE μj........ Qg = nc Qg = nc Qg = nc Qg = nc C LEDN Figure Optocoupler Input to Output Capacitance Model for Shielded Optocouplers C LEDP C LEDN C LED SHIELD C LED 8 CMR with the LED On (CMR H ) Rg GATE RESISTANCE A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 8 ma provides adequate margin over the maximum I FLH of ma to achieve kv/μs CMR. - -
CMR with the LED Off (CMR L ) A high CMR LED drive circuit must keep the LED off (V F V F(OFF) ) during common mode transients. For example, during a dv CM /dt transient in Figure, the current flowing through C LEDP also flows through the R SAT and V SAT of the logic gate. As long as the low state voltage developed across the logic gate is less than V F(OFF), the LED remains off and no common mode failure occurs. Figure Recommended LED Drive Circuit for Ultra-High CMR Dead Time and Propagation Delay Specifications + V C LEDP C LEDN SHIELD Figure Equivalent Circuit for Figure 7 During Common Mode Transient + V + V SAT - C LEDP C LEDN I LEDP SHIELD THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING - dv CM /dt The open collector drive circuit, shown in Figure, cannot keep the LED off during a +dv CM /dt transient, since all the current flowing through C LEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMR performance. The alternative drive circuit, like the recommended application circuit (Figure 9), achieves ultra high CMR performance by shunting the LED in the off state. Figure Not Recommended Open Collector Drive Circuit + - V CM. F V CC = 8V + - Rg Dead Time and Propagation Delay Specifications The ACPL-P/W includes a Propagation Delay Difference (PDD) specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time high and low side power transistors are off. Any overlap in Ql and Q conduction will result in large currents flowing through the power devices from the high voltage to the low-voltage motor rails. To minimize dead time in a given design, the turn on of LED should be delayed (relative to the turn off of LED) so that under worst-case conditions, transistor Q has just turned off when transistor Q turns on, as shown in Figure. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD max, which is specified to be ns over the operating temperature range of C to C. Figure Minimum LED Skew for Zero Dead Time I LED + V C LEDP V OUT Q ON Q OFF Q I LEDN C LEDN SHIELD V OUT Q OFF Q ON I LED t PHL MAX tplh MIN PDD* MAX = (t PHL - t PLH ) MAX = t PHL MAX - t PLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. - -
Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in Figure 7. The maximum dead time for the ACPL-P/W is μs (=. μs (. μs)) over the operating temperature range of C to C. Figure 7 Waveforms for Dead Time V OUT V OUT NOTE I LED I LED Q ON Q OFF t PHL MIN t PHL MAX (t PHL- t PLH ) MAX PDD* MAX t PLH MIN t PLH MAX *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (t PHL MAX - t PHL MIN ) + (t PLH MAX - t PLH MIN ) = (t PHL MAX - t PLH MIN ) (t PHL MIN - t PLH MAX ) = PDD* MAX PDD* MIN The propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. Q OFF Q ON Thermal Model for ACPL-P/W Streched-SO Package Optocoupler Definitions R : R : R : R : P : P : T : T : T a : ΔT : ΔT : Junction to Ambient Thermal Resistance of LED due to heating of LED. Junction to Ambient Thermal Resistance of LED due to heating of Detector (Output IC). Junction to Ambient Thermal Resistance of Detector (Output IC) due to heating of LED. Junction to Ambient Thermal Resistance of Detector (Output IC) due to heating of Detector (Output IC). Power dissipation of LED (W). Power dissipation of Detector/Output IC (W). Junction temperature of LED (C). Junction temperature of Detector (C). Ambient temperature. Temperature difference between LED junction and ambient (C). Temperature deference between Detector junction and ambient. Ambient Temperature: Junction to Ambient Thermal Resistances were measured approximately. cm above optocoupler at ~ C in still air. Description This thermal model assumes that an -pin single-channel plastic package optocoupler is soldered into a 7. cm 7. cm printed circuit board (PCB). The temperature at the LED and Detector junctions of the optocoupler can be calculated using the equations below. T = (R P + R P ) + T a -- () T = (R P + R P ) + T a -- () JEDEC Specifications R R, R R Low K board 7, 8 High K board 9 7, 79 9 NOTE Maximum junction temperature for above parts: C. - -
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