Homework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26

Homework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26 In the following problems, if reference to a semiconductor process is needed, assume processes with the following characteristics: CMOS Process -- n C OX = 100A/v 2 p C OX = n C OX /3, V TNO = 0.5V, V TPO = - 0.5V, C OX = 2fF/ 2, n p = 0.01V -1, and V Bipolar Process -- J S =10-15 A/ 2, β = 100 and V AF = 150V. If more extensive parasitic capacitance parameters, use the model parameters in the attachment for the ON 0.5u CMOS process. Problem 1 An open-loop amplifier has a gain Ao and left-half plane poles at p 1 and p 2 where p 2 =kp 1 If it is used as a feedback amplifier with a feedback factor, determine the pole ratio k so that the feedback amplifier has a 65 degree phase margin. Problem 2 Assume an amplifier has a dc gain of 40,000, a pole at -30 rad/sec and a pole at -500,000 rad/sec. Assume this is used as a feedback amplifier with a of 0.5. a) Present a Nyquist Plot and from this determine the phase margin of this feedback amplifier. b) Determine the pole locations of the feedback amplifier c) Present a magnitude and phase plot of the open loop gain A(s) and from this determine the phase margin and compare with that obtained in part a). d) What is the gain-bandwidth product of the open-loop and the closed-loop amplifier? Compensate the amplifier by adjusting the low frequency pole so that the phase margin becomes 75 degrees. Problem 3 The amplifier given below generally needs compensation. A compensation capacitor is used for this compensation. For the compensated amplifier, determine the dc gain, approximate location of the dominant pole, the GB, and an expression for the value of C C needed to obtain a pole Q of.707 if β = 1. Q7 V b1 Q8 Q10 Q5 V b2 Q6 Q3 V b3 Q4 C C Vi+ Q1 Q2 Vi- V b4 Q9 V b6 Q11

Problem 4 An analytical expression for the relationship between phase margin and pole Q for second-order lowpass amplifiers was given in class. Although analytical expressions are, in general, not possible for other structures, this relationship can be determined with computer simulations. a) Assume an amplifier with open-loop gain of As 10, 000 s s 1 1 p p 1 2 Assume this is used to build a standard feedback amplifier that has gain of As A 1 A where β is a constant. If β=0.2 and p 2 =1000rad/sec, determine the location of the pole p 1 so that the phase margin is 45 o. What is the resultant pole Q of the feedback amplifier? Determine the location of the pole p 1 so that the phase margin is 60 o. What is the resultant pole Q of the feedback amplifier? b) Repeat part a) if the open-loop gain is given by where z 1 = -500rad/sec A s s 10, 000 1 z s s 1 1 p p 1 1 2 c) Repeat part a) if the open-loop gain is given by A s s 10, 000 1 z s s 1 1 p p 1 1 2 where z 1 = + 500 rad/sec c) Repeat part a) if the open-loop gain is given by 10, 000 3 As s s 1 1 p p 1 2 d) From the first 4 parts of this problem, what conclusions can be drawn about the relationship between the pole Q and the phase margin of feedback amplifiers?

Problem 5 Assume the operational amplifier below is being sold by a competitor and the competitor gives the circuit schematic but refuses to disclose any information about frequency response or anything about device sizes that are on the inside beyond stating that it has an open-loop dc gain of 80dB and that it is fabricated in a 0.5u CMOS process with parameters as described in the attachment. Assume you have measured the supply current when biased at a supply voltage of 5V and found it to be 10mA, that the load capacitance is 50pF, and that the output starts to distort when the output voltage exceeds 4.5V. Determine as many of the following as possible from the information given. If a parameter can not be determined from the information given, state that fact. a) W1/L1 b) W3/L3 c) GB d) SR e) V OMIN f) W9/L9 g) phase margin of the feedback amplifier if β = 1. M 3 M 4 V M M IN 1 2 V B2 M 9

Problem 6 The magnitude and phase plot of an operational amplifier are shown. a) Determine the phase margin if this is used in a feedback amplifier with a feedback factor of β=0.025 b) Is the feedback amplifier stable? Why? c) What is the maximum value of β that can be used if the amplifier is to have a 60 o phase margin? d) If β =.001, what is the ideal closed loop gain and what is the percent closed-loop gain error due to the finite dc gain limitations of the op amp? 100 80 Gain Plot Gain in db 60 40 20 0-20 1 10 10 2 10 3 10 4 10 5 ω -40-60 Phase in degrees 0-50 -100-150 -200-250 -300 1 10 10 2 10 3 10 4 10 5 Phase Plot ω

Problem 7 A two-stage operational amplifier is shown along with the device sizes in microns. Assume =5V and V XX =1V a) Determine the dc gain of the op amp b) What is the GB of the op amp if C C =4pf and =1pf? Neglect all other capacitances in the amplifier c) Determine the power dissipation of the amplifier d) What is the pole Q if used in a noninverting feedback amplifier with β=0.25? M 3 M 4 M 5 V M 1 M 2 1 V 2 C C V XX M 7 V XX M 6 W L Q1 200 1 Q2 200 1 Q3 400 1 Q4 400 1 Q5 700 1 Q6 250 1 Q7 350 1 Problem 8 If a feedback amplifier has a characteristic polynomial given by 3 2 D FB(s) s 4s as 36 where a is a variable, what is the minimum value of a that can be used if the feedback amplifier is to remain stable? Problem 9 Assume an operational amplifier has a dc gain of 80dB, three poles in the LHP of magnitudes 10rad/sec, 4Krad/sec and 30krad/sec. If the position of a zero can be adjusted in a way that the dc gain and all poles remain fixed, plot the phase margin versus the location of the zero as it is moved from 10K rad/sec in the RHP to -10K rad/sec in the LHP.

Problem 10 A network that can be used as the β network for a feedback amplifier is shown. The blue arrow shows the intended direction of propagation of the feedback signal through the feedback network. 2 R 1 R 2 1 a) Determine the β of this network if the overall feedback amplifier is a transresistance amplifier b) Determine the β of this network if the overall feedback amplifier is a current amplifier c) Obtain the two-port parameters of this β network Problem 11 Assume a feedback network has an all-pole second-order closed loop transfer function. Assume further that the A amplifier has a dc gain of 80dB and that the feedback network does not cause any loading on the open-loop amplifier. a) If the amplifier has been compensated for a phase margin of 45 o with a feedback factor of β=0.2, determine the percent overshoot in the step response of the feedback amplifier. b) Determine the spread in the amplifier open-loop poles using the compensation determined in part a) c) If the compensation of the open-loop amplifier determined in part a) is maintained but the feedback factor β is increased to 0.5, determine the percent overshoot in the step response. d) What is the phase margin of the feedback amplifier in part c)?

Problem 12 Assume that a folded-cascode op amp with n-channel inputs, tail-current input bias, and current-mirror n-channel biasing was designed so that all transistors had V EB =0.25V. If = 2.5V, V SS = -2.5V, V B2 =1.4V, V B3 = -1.4V, and the bias current in transistors {M 1,M 2,M 3, M 4, M 7, M 8, M 9, and M 10 } are all the same, a) Determine the devices sizes if P=2mW b) Determine the SR if the load capacitance is 2pF c) What is the output signal swing? d) What is the dc gain of the amplifier? M 5 M 6 V B1 M 3 M 4 V B2 M 9 M 1 M 2 M7 V B3 M 10 M 8 I T V SS V SS Problem 13 Analytically compare the power dissipation and the gain for the folded cascode amplifier discussed in Problem 12 with that of the reference op amp with the same excess biases and the same GB?

Problem 14 The block diagram shown identifies one two-stage op amp. a) Give the circuit schematic for this two-stage op amp b) Give an expression for the dc gain and the GB of this op amp in terms of the small-signal parameters of the devices in the op amp c) Identify a practical design parameter domain and give the dc gain and GB in terms of the practical design parameters Common Source Cascode Regulated Cascode Folded Cascode Folded Regulated Cascode Current Mirror Differential Input Single-Ended Input Single-Ended Output Differential Output CMFB BIAS Current Mirror Bias Tail Voltage Bias Tail Current Bias Stage 1 n-channel input p-channel Input Common Source Cascode Regulated Cascode Folded Cascode Folded Regulated Cascode Current Mirror Differential Input Single-Ended Input Single-Ended Output Differential Output CMFB BIAS Current Mirror Bias Tail Voltage Bias Tail Current Bias Stage 2 n-channel input p-channel Input Compensation Output Compensated Internally Compensated Problem 15 Consider the amplifier architecture shown. Identify which architecture this is in the context of the amplifier types of Problem 14. Identify parametrically the two dominant poles (assume the dominant capacitance on the drain node of Q 6 is due to the GS capacitance of Q 10 and that on the drain node of Q 10 is the extgernal load capacitance ). Determine parametric expressions for the dc gain and the GB if the pole on the internal node is much smaller than the pole on the output node. Assume the device is fabricated in the ON 0.5u process. How far apart must these two poles be for proper operation (define proper operation to be a phase margin of 60 o ) of a feedback amplifier if =0.5? If these are not far enough apart, how can the circuit be modified to achieve the required pole ratios? Q7 V b1 Q8 Q10 Q5 V b2 Q6 Q3 V b3 Q4 Vi+ Q1 Q2 Vi- V b4 Q9 V b6 Q11

Problem 16 A new amplifier structure is shown below. Assume the only capacitor in the circuit is (i.e. neglect any internal parasitic capacitors). a) Determine the small signal voltage gain and the GB from the differential input to the output (it can be shown that the small signal voltage V SS =0 when excited differentially) b) Define a set of practical design parameters and give the expression for the dc gain and the GB in terms of these parameters. c) Assume that the lengths of M 3, M 4, and M x are identical and that M 3 and M 4 are matched. Define the width of the transistor M x to be θw 3. Determine the maximum value of θ for stabllity of this amplifier d) If θ is 0.999 times this maximum value, determine the gain of this amplifier in terms of the practical design parameters e) If θ is 0.999 times this maximum value, determine the GB of this amplifier in terms of the practical design parameters f) Comment on how this amplifier compares to the reference op amp. M 3 M x M 4 - M 1 M 2 + V ss V B1 M 5

TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS MINIMUM 3.0/0.6 Vth 0.78-0.93 volts SHORT 20.0/0.6 Idss 439-238 ua/um Vth 0.69-0.90 volts Vpt 10.0-10.0 volts WIDE 20.0/0.6 Ids0 < 2.5 < 2.5 pa/um LARGE 50/50 Vth 0.70-0.95 volts Vjbkd 11.4-11.7 volts Ijlk <50.0 <50.0 pa Gamma 0.50 0.58 V 0.5 K' (Uo*Cox/2) 56.9-18.4 ua/v 2 Low-field Mobility 474.57 153.46 cm 2 /V*s COMMENTS: XL_AMI_C5F FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS Vth Poly >15.0 <-15.0 volts PROCESS PARAMETERS N+ACTV P+ACTV POLY PLY2_HR POLY2 MTL1 MTL2 UNITS Sheet Resistance 82.7 103.2 21.7 984 39.7 0.09 0.09 ohms/sq Contact Resistance 56.2 118.4 14.6 24.0 0.78 ohms Gate Oxide Thickness 144 angstrom PROCESS PARAMETERS MTL3 N\PLY N_WELL UNITS Sheet Resistance 0.05 824 815 ohms/sq Contact Resistance 0.78 ohms COMMENTS: N\POLY is N-well under polysilicon. CAPACITANCE PARAMETERS N+ACTV P+ACTV POLY POLY2 M1 M2 M3 N_WELL UNITS Area (substrate) 429 721 82 32 17 10 40 af/um 2 Area (N+active) 2401 36 16 12 af/um 2 Area (P+active) 2308 af/um 2 Area (poly) 864 61 17 9 af/um 2 Area (poly2) 53 af/um 2 Area (metal1) 34 13 af/um 2 Area (metal2) 32 af/um 2 Fringe (substrate) 311 256 74 58 39 af/um Fringe (poly) 53 40 28 af/um Fringe (metal1) 55 32 af/um Fringe (metal2) 48 af/um Overlap (N+active) 206 af/um Overlap (P+active) 278 af/um

Practice Problems: The following problems will not be collected or graded but are here as practice problems for those interested. Problem P1 A reference op amp was designed with V EB1 = V EB3 = 500mV. If the supply voltages were =2.5V, V SS =-2.5Vand the desired output voltage is 0V, determine a) The systematic output offset voltage b) The systematic input-referred offset voltage (assume V IC =0V and the desired output voltage is 0V) V B1 M 3 M 4 M 1 M 2 V B2 M 9 V SS Problem P2 Analytically compare the power dissipation and the gain for the folded cascode amplifier discussed in Problem 12 with that of the telescopic cascode op amp with the same excess biases and the same GB?

Problem P3 The GB of the CS amplifier was shown to be g m /. In this derivation, is the total load capacitance on the output node and the high-frequency coupling capacitance, C C, from Gate to Drain was neglected. I DD M 1 M 1 V SS CS amplifier Small-Signal Equivalent Ckt a) What is the GB of this amplifier if V SS is chosen so that V EB =0.2V and P=100uW (assume =2.5V)? b) What is the W/L ratio required for V EB =0.2V and P=100uW c) With the W/L ratio obtained in part b) and a length of L=2u, determine the parasitic drain-substrate capacitance, C DSUB. d) If the load capacitance of 500fF is entirely an external load, how much will the dc gain and the GB change if the parasitic capacitance C DSUB is present? e) What effect will the parasitic capacitance C GD that has been neglected up to this point have on the GB of the amplifier? (Analytically derive GB if CGD effects are included) C GD M 1 f) Estimate the value of C GD if the MOS device is fabricated in a 0.5u AMI process assuming the same biasing as in part a)

Problem P4 A new amplifier structure, exclusive of the CMFB circuit, is shown. Determine the dc gain, the dominant pole location and the GB for the amplifier. Q5 V b1 Q6 Q7 V b2 Q8 Q7 V b3 Q8 Q3 V b4 Q4 Q3 V b5 Q4 Vi+ Vi+ Q1 Q2 Vi- V b6 Q9

Problem P5 Assume the OTAs are ideal. Obtain the transfer function for the two circuits shown and an expression for the pole locations. If the circuits have more than one pole, determine the wo and Q of the poles. g m1 C g m2 V O g m3 g m1 g m2 V O C 1 C 2 Problem P6 A capacitance multiplication scheme which shows the basic principles used for generating the Miller capacitance used for internal compensation is shown below. In this structure, if the amplifier is an ideal voltage amplifier (with A positive), the equivalent capacitance, often termed the Miller capacitance is C EQ =C(1+A) -A C C EQ

If the magnitude of the input conductance for this circuit were plotted versus ω, it would be proportional to ω and if the frequency axis used a logarithmic scale, the conductance plot would be a straight line. If the amplifier becomes nonideal, however, then the conductance plot would deviate from a straight line and the larger the deviation, the less useful this Miller capacitance would be at representing a capacitor. In the context of using this as a compensation capacitor, if the deviation in the conductance from that of an ideal capacitor becomes 10% or more, the performance as a capacitor would be compromised. a) Compare the Miller Capacitance with that of an ideal capacitor using an input conductance plot if the amplifier A has a dc gain of -100 and a pole at ω = 25KRad/sec. At what frequency does the deviation from linear become 10%? b) Repeat part a) if the amplifier shown below is used to build the A amplifier where the op amps have a GB of 1MHz and a dc gain of 10 5 R 100R c) Repeat part a) if the amplifier is the common-source circuit shown where the W/L ration of M 1 is chosen so that V OQ =0V. Assume the transistor is fabricated in the AMI 0.5u CMOS process and that the capacitors C GS and C DSUB are present. 100uA M 1-2V