High Speed Area Efficiet Modulo 2 1 1-Soali Sigh (PG Scholar VLSI, RKDF Ist Bhopal M.P) 2- Mr. Maish Trivedi (HOD EC Departmet, RKDF Ist Bhopal M.P) Adder Abstract Modular adder is oe of the key compoets for the applicatio of residue umber system (RNS). Moduli set with the form of 2 +1 ca offer excellet balace amog the RNS chaels for multi-chaels RNS processig. As oe of the processor's ALU performace issues, the carry propagatio durig the additio operatio limits the speed of arithmetic operatio. I this paper review o 2 +1 additio i the residue umber system. The architecture desig of CCS modular adder is simple ad regular for various bit-width iputs. The review modulo adder i the aforemetioed paper cosists of a dual-sum carry look-ahead (DS-CLA) adder, a circular carry geerator, ad a multiplexer, which ca reduce both umber of slice ad maximum combiatio path delay (MCPD). Keywords:- Modulo Adder, Prefix Carry Computatio Residue Number System (RNS), Moduli Set, Dimiished-1 Number represetatio, VLSI desig, Xilix Software Itroductio A Residue umber system is a o-weight umeric system [1] which has gaied importace durig the last decade, because some of the mathematical operatios ca be divided ito categories of sub-operatios based o RNS [2]. Additio, subtractio ad multiplicatio are performed i parallel o the residues i distict desig uits (ofte called chaels), avoidig carry propagatio amog residues [3]. Therefore, arithmetic operatios such as, additio, subtractio ad multiplicatio ca be carried out more efficietly i RNS tha i covetioal two's complemet systems. That makes RNS a good cadidate for implemetig variety of applicatios [4] such as: digital Sigal Processig (DSP) for filterig, covolutios, FFT computatio, fault-tolerat computer systems, commuicatio ad cryptography. Choosig a proper moduli set greatly affects the performace of the whole system. The prevalet issue is that as the umber of moduli icreases the speed of the residue arithmetic uits icreases, whereas the residue-to-biary coverters become slower ad more complex. Thus, I carried out a detailed study o differet moduli sets with differet moduli umbers ad differet dyamic rages ad compared timig performace of systems based o them i order to determie the moduli umber effect o the overall RNS timig performace ad fid out the most efficiet set for each dyamic rage. The study has bee published i a iteratioal coferece i Dubai, UAE [13] ad a exteded versio of it has bee published i the iteratioal joural of Emergig Treds i Computig ad Iformatio Scieces [14]. Based o the aalysis ad outcomes of this research, the uexpected issue I have ascertaied is that, the umber of moduli does ot affect that much the overall delay of the system cosiderig all its compoets. Five-moduli sets do ot show ay superiority over other sets takig ito accout the three compoets of RNS (modular adders, modular multipliers ad residue to biary coverters). Moreover the three-moduli set {2+1 1, 2, 2 1} [4] showed the best timig performace cocerig all the three compoets. Hece, there is o poit for choosig a five-moduli set if the overall timig performace will be worse tha that based o three or four-modulus sets. DIMINISHED -1 NUMBER REPRESENTATION The modulo arithmetic operatios require (+1) bit operads. To avoid (+1)-bit circuits, the dimiished-1 umber system [15] has bee adopted. Let be the dimiished-1 represetatio of the ormal biary umber, amely (i) 47 www.ijergs.org
I (i), whe, is a -bit umber, therefore (+1) -bit circuits ca be avoided i this case. However, (ii) is a (+1) -bit umber. This leads to special treatmet for d [0]. The dimiished-1 arithmetic operatios [15] are defied as (iii) (iv) (v) (vi) ( ) (vii) ( ) (viii) Where represets the oe s complemet of d [A]. I (vii) ad (viii) icls (d[a], k) is the k -bit left-circular shift of i which the bits circulated ito the LSB are complemeted. MODULO ADDER Due to the fact that biary to residue coverters are rather simple, little work has bee dedicated to ehace their performace. Sice my research dealt with special moduli sets rather tha geeral moduli sets, the utilized compoets to obtai residues with respect to the moduli set {2 1, 2, 2 + 1} are preseted i this sectio. Sice the majority of moduli sets have moduli of the followig forms (2 k 1), (2 k) or (2 k + 1), thus, the illustrated forward coverters ca be used to obtai the RNS represetatio with respect to ay of those sets. The most straightforward residue to obtai is the oe with respect to modulo 2. This residue represets the least bits of the biary umber. Thus, o adders or ay logical compoets are eeded. However, computig a residue with respect to modulo (2 1), demads two cosecutive modulo (2 1) adders. Istead of usig this structure, a carry save adder with ed aroud carry (CSA-EAC) followed by carry ripple adder with ed aroud carry (CRA-EAC) ca perfectly fulfill the task. This structure is show i Figure 1. 48 www.ijergs.org
Figure 1: Proposed biary to residue coverter (a) modulo (2 1) chael (b) Modulo (2 + 1) chael The most difficult residue to obtai is the oe with respect to (2 + 1) modulo. Typically, this oe requires modulo (2 + 1) sub tractor followed by modulo (2 + 1) adder. This structure is rather complicated, sice both compoets are complex ad time cosumig. However, by a proper extractio of the equatios eeded for the forward coversio process, the proposed structure of the compoet that computes the residue with respect to modulo (2 + 1) is cosiderably simplified. It is realized usig two parallel biary adders followed by modulo (2 + 1) adder as illustrated i Figure 1 (b). Sice oe of the iputs of the first biary adder is costat, its structure ca be simplified, the ( + 1) full adders ca be replaced by ( 2) half adders. However, this simplificatio does ot reduce the delay (due to the secod adder that adds B1 + B3), but the overall hardware complexity decreases. Majority of the published structures of modulo (2 1) adder perform additio first, ad the apply the ecessary correctio, i order to get the correct result that correspods to this modulo. The stadard structure of this adder depeds o two biary adders ad a multiplexer. However, the proposed modular adder employs the prefix adders cocept i order to pre calculate the carry-out eeded for the correctio process. This desig has bee published i a iteratioal coferece i Bro [1] ad a exteded versio has bee published i Electro Scope joural. 49 www.ijergs.org
MODULO (2N + 1) ADDER BASED ON PREFIX CARRY COMPUTATION Cotrary to the previously proposed modulo (2 + 1) adder, this oe cosists of ( + 1) -bit circuits. However, it utilizes the cocept of prefix carry computatio used i parallel prefix adders i order to speed-up the computatio process. This modular adder has bee published i a iteratioal coferece i Bro [2] ad a exteded versio has bee published i Electro Scope joural. Figure 2: Proposed modulo (2 + 1) adder - based o the prefix computatio The structure of the proposed adder is illustrated i Figure 2. The mai cocept of this adder is based o the prefix computatio of the MSB of (X + Y 1), ad the applyig the ecessary correctio. This correctio is represeted i applyig the correct carry-i ito the CRA. To prove the efficiecy of this adder, it was compared with aother already published oe, which was published i [9] ad deoted as (k). This Modular adder (k) was chose due to its superiority over other modular adders stated i [9]. Both adders were implemeted o Sparta-3 xc3s200 FPGA. RESULT AND SIMULATION All the desigig ad experimet regardig algorithm that we have metioed i this paper is beig developed o Xilix 14.1i updated versio. Xilix 9.2i has couple of the strikig features such as low memory requiremet, fast debuggig, ad low cost. The latest release of ISE TM (Itegrated Software Eviromet) desig tool provides the low memory requiremet approximate 27 percetage low. ISE 14.1i that provides advaced tools like smart compile techology with better usage of their computig hardware provides faster timig closure ad higher quality of results for a better time to desigig solutio. ISE 14.1i Xilix tools permits greater flexibility for desigs which leverage embedded processors. The ISE 14.1i Desig suite is accompaied by the release of chip scope Pro TM 14.1i debug ad verificatio software. By the aid of that software we debug the program easily. Also icluded is the ewest release of the chip scope Pro Serial IO Tool kit, providig simplified debuggig of high-speed serial IO desigs for Virtex-4 FX ad Virtex-5 LXT ad SXT FPGAs. With the help of this tool we ca develop i the area of commuicatio as well as i the area of sigal processig ad VLSI low power desigig. To simplify multi rate DSP ad DHT desigs with a large umber of clocks typically foud i wireless ad video applicatios, ISE 14.1i software features breakthrough advacemets i place ad route ad clock algorithm offerig up to a 15 percet performace advatage. Xilix 14.1i Provides the low memory requiremet while providig expaded support for Microsoft widows Vista, Microsoft Widows XP x64, ad Red Hat Eterprise WS 5.0 32-bit operatig systems. 50 www.ijergs.org
Figure 3: Device summary of 8-bit residue umber Figure 4: Device summary of 12-bit residue umber Figure 5: Device summary of 16-bit residue umber VI. CONCLUSION The mai aim of this paper was desigig RNS based buildig blocks for applicatios i the field of DSP applicatios (biary-toresidue coverter, residue-to-biary coverter ad residue adder. The mai RNS compoets have bee itroduced icludig a biary to residue coverter, modular adders, modular sub tractors, modular multipliers, a residue comparator, compoets for overflow ad sig detectio ad correctio ad a residue to biary coverter. The atithesis to the prevalet issue regardig the umber of moduli withi a set has bee also preseted. The three-moduli set {2+1 1, 2, 2 1} have show the best timig performaces amog all other sets. REFERENCES: [1] P. V. Aada Moha, Residue Number Systems: Algorithms ad Architectures, Kluwer, Academic Publishers, 2002. [2] MOHAN, P.V.A., Residue Number System: Algorithms ad Architectures. Massachusetts: Spriger, 2002. 272 pages. ISBN- 13: 978-1402070310. [3] PIESTRAK, S.J. A High-Speed Realizatio of a Residue to Biary Number System Coverter. I IEEE Tras. o Circuits ad Systems-II: Aalog ad Digital Sigal Processig, 1995, vol. 42, p. 661 663. ISSN 1057-7130. [4] MOHAN, P.V.A. RNS-to-Biary Coverter for a New Three-Moduli Set {2+1 1, 2, 2 1}. I IEEE Tras. o Circuits ad Systems-II: Express Briefs, 2007, vol. 54, p. 775 779. ISSN 1549-7747. [5] MOLAHOSSEINI, A.S., NAVI, K., RAFSANJANI, M.K. A New Residue to Biary Coverter Based o Mixed-Radix Coversio. I 3rd Iteratioal Coferece o Iformatio ad Commuicatio Techologies: From Theory to Applicatios, 2008, p. 1 6. ISBN 978-1-4244-1751-3. [6] BI, S., GROSS, W.J. Efficiet Residue Compariso Algorithm for Geeral Moduli Sets. I 48th Midwest Symposium o Circuits ad Systems, 2005, vol. 2, p. 1601 1604. ISBN 0-7803-9197-7. [7] WANG, W., SWAMY, M.N.S., AHMAD, M.O., WANG, Y. A Study of the Residue-to-Biary Coverters for the Three- Modulus Sets. I IEEE Tras. o Circuits ad Systems-I: Fudametal Theory ad Applicatios, 2003, vol. 50, p. 235 243. ISSN 1057-7122. [8] MOLAHOSSEINI, A.S., TEYMOURI, F., NAVI, K. A New Four-Modulus RNS to Biary Coverter. I Proc. of IEEE Iteratioal Symposium o Circuits ad Systems, 2010, p. 4161 4164. ISBN 978-1- 4244-5308-5. [9] A. Curiger, H. Boeberg, ad H. Kaesli, Regular VLSI architectures for multiplicatio modulo ( 2 1), IEEE J. Solid-State Circuits,vol. 26, o. 7, pp. 990 994, Jul. 1991. [10] L. Leibowitz, A simplified biary arithmetic for the fermat umber trasform, IEEE Tras. Acoust., Speech, Sigal Process., vol. ASSP-24, pp. 356 359, May 1976. [11] J.W.Che, R.H.Yao ad W.J.Wu,Efficiet modulo ( 2 1) multipliers, IEEE Tras. VLSI systems., vol. 19, o 12, pp. 2149 2157, Dec. 2011 51 www.ijergs.org