July 2013 FSUSB45 High-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect Features Low On Capacitance: 7.0 pf Typical Low On Resistance: 3.9 Ω Typical Low Power Consumption: 1 μa Maximum - 15 μa Maximum I CCT over an Expanded Voltage Range (V IN=1.8 V, V CC=4.3 V) Wide -3 db Bandwidth: > 720 MHz Packaged in: - 10-Lead MicroPak (1.6 x 2.1 mm) - 10-Lead UMLP (1.4 x 1.8 mm) 8 kv ESD Rating, >16 kv Power/ ESD Rating Power-Off Protection on All Ports When V CC=0 V - D+/D- Pins Tolerate up to 5.25 V Applications Cell Phone, PDA, Digital Camera, and Notebook LCD Monitor, TV, and Set-Top Box IMPORTANT NOTE: For additional performance information, please contact analogswitch@fairchildsemi.com. Description The FSUSB45 is a bi-directional, low-power, two-port, High-Speed, USB2.0 switch. Configured as a doublepole, double-throw (DPDT) switch, it is optimized for switching between two HS (480 Mbps) sources or an HS source and a Full-Speed (12 Mbps) source. The FSUSB45 is compatible with the requirements of USB2.0 and features an extremely low on capacitance (C ON) of 7.0 pf. The wide bandwidth of this device (720 MHz) exceeds the bandwidth needed to pass the third harmonic, resulting in signals with minimum edge and phase distortion. Superior channel-to-channel crosstalk also minimizes interference. The FSUSB45 contains special circuitry on the switch I/O pins for applications where the V CC supply is powered-off (V CC=0), which allows the device to withstand an over-voltage condition. This device is designed to minimize current consumption even when the control voltage applied to the SEL pin is lower than the supply voltage (V CC). This feature is especially valuable to mobile applications, such as cell phones, allowing for direct interface with the general-purpose I/Os of the baseband processor. An additional feature is the detection of the 1,1 state on D+/D- to signal an interrupt (INT) to the processor when entering a dedicated charging port mode of operation. INT HSD1+ HSD2+ D+ HSD1- HSD2- D- Sel Figure 1. Analog Symbol Ordering Information Part Number Top Mark Operating Temperature Range Package FSUSB45L10X JA -40 to +85 C 10-Lead, MicroPak 1.6 x 2.1 mm, JEDEC MO-255B FSUSB45UMX JB -40 to +85 C MicroPak is a trademark of Fairchild Semiconductor Corporation. 10-Lead, Quad, Ultrathin Molded Leadless Package (UMLP), 1.4 x 1.8 mm FSUSB45 Rev. 1.0.7
Pin Assignments Vcc Sel 1 10 9 INT HSD2+ HSD1+ HSD1+ 2 8 HSD1- D+ 3 2 1 10 Sel HSD2+ 3 7 HSD2-4 9 Vcc D+ 4 5 6 D- D- 5 6 7 8 HSD2- HSD1- INT Figure 2. Pad Assignments for MicroPak (Top Through View) Figure 3. Pin Assignments for UMLP (Top Through View) Pin Definitions MicroPak Pin # UMLP Pin # Name Description 9 8 INT Interrupt Signaling Output Pin 1 10 Sel Switch Select 4, 6 3, 5 D+, D- USB Data Bus 2, 3, 7, 8 1, 2, 6, 7 HSDn+, HSDn- Multiplexed Source Inputs 5 4 Ground Truth Table Sel Switch Connection INT Output L D+, D-=HSD1+, HSD1- LOW H D+, D-=HSD2+, HSD2- HIGH FSUSB45 Rev. 1.0.7 2
Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V CC Supply Voltage -0.5 +5.5 V V CNTRL DC Input Voltage (S) (1) -0.5 V CC V V SW DC Switch I/O Voltage (1) -0.50 5.25 V I IK DC Input Diode Current -50 ma I OUT DC Output Current 50 ma T STG Storage Temperature -65 +150 C ESD Human Body Model, JEDEC: JESD22-A114 All Pins 7 I/O to 8 Power to 16 Charged Device Model, JEDEC: JESD22-C101 2 Note: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. kv Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V CC Supply Voltage 3.0 4.3 V V CNTRL (2) Control Input Voltage (Sel) 0 V CC V V SW Switch I/O Voltage -0.5 V CC V T A Operating Temperature -40 85 C Note: 2. The control input must be held HIGH or LOW; it must not float. FSUSB45 Rev. 1.0.7 3
DC Electrical Characteristics All typical value are at 25 C, V CC=3.3 V unless otherwise specified. Symbol Parameter Conditions V CC (V) T A =- 40ºC to +85ºC Min. Typ. Max. V IK Clamp Diode Voltage I IN=-18 ma 3.0-1.2 V V IH V IL Input Voltage High Input Voltage Low V OH Output Voltage High I OH=-2 ma V OL Output Voltage Low I OL=2 ma Units 3.0 to 3.6 1.3 V 4.3 1.7 V 3.0 to 3.6 0.5 V 4.3 0.7 V 3.0 to 3.6 2.4 4.3 2.4 3.0 to 3.6 0.25 4.3 0.25 I IN Control Input Leakage V SW=0 to V CC 4.3-1 1 µa I NC(OFF), I NO(OFF) I Dn(ON) I OFF Off State Leakage ON State Leakage Power-Off Leakage Current (All I/O Ports) HSD1n or HSD2n=0 V, 3.6 V or floating, D+/-=0 or 3.6 V HSD1n or HSD2n=0 V, 3.6 V or floating, D+/-=0 or 3.6 V V SW=0 V to 4.3 V, V CC=0 V, Figure 5 (3) VSW=0.4 V, ION=-8 ma, R ON HS Switch On Resistance Figure 4 R ON HS Delta R ON (4) 4.3-2 2 µa 4.3-2 2 µa 0-2 2 µa 3.0 3.9 6.5 V SW=0.4 V, I ON=-8 ma 3.0 0.65 I CC Quiescent Supply Current V CNTRL=0 or V CC, I OUT=0 4.3 1.0 µa I CCT Increase in I CC Current per Control Voltage and V CC V CNTRL=2.6 V, V CC=4.3 V 4.3 10.0 µa V CNTRL=1.8 V, V CC=4.3 V 4.3 20.0 µa Notes: 3. Measured by the voltage drop between HSDn and Dn pins at the indicated current through the switch. On resistance is determined by the lower of the voltage on the two (HSDn or Dn ports). 4. Guaranteed by characterization. V V FSUSB45 Rev. 1.0.7 4
AC Electrical Characteristics All typical value are for V CC=3.3 V at 25 C unless otherwise specified. Symbol Parameter Conditions V CC (V) t ON Turn-On Time, S to Output t OFF Turn-Off Time, S to Output RL=50 Ω, CL=5 pf, VSW=0.8 V, Figure 6, Figure 7 RL=50 Ω, CL=5 pf, VSW=0.8V, Figure 6, Figure 7 (5) CL=5 pf, RL=50 Ω, Figure 6, t PD Propagation Delay Figure 8 t BBM Break-Before-Make R L=50 Ω, C L=5 pf, V SW1=V SW2=0.8 V, Figure 12 T A =- 40 to +85 C Min. Typ. Max. Units 3.0 to 3.6 13 30 ns 3.0 to 3.6 12 25 ns 3.3 0.25 ns 3.0 to 3.6 2.0 6.5 ns t PLH/HL INT Propagation Delay (5) R L=50 Ω, C L=5 pf 3.0 to 3.6 10 ns O IRR Off Isolation R L=50 Ω, f=24 0MHz, Figure 14 3.0 to 3.6-30 db Xtalk BW Non-Adjacent Channel Crosstalk -3 db Bandwidth Note: 5. Guaranteed by characterization. USB Hi-Speed-Related AC Electrical Characteristics R L=50 Ω, f=240 MHz, Figure 15 3.0 to 3.6-45 db R L=50 Ω, C L=0 pf, Figure 13 720 MHz 3.0 to 3.6 R L=50 Ω, C L=5 pf, Figure 13 550 MHz Symbol Parameter Conditions V CC (V) t SK(P) Skew of Opposite Transitions of C L=5 pf, R L=50 Ω, the Same Output (6) Figure 9 t J Total Jitter (6) t R=t F=500 ps (10-90%) at R L=50 Ω, C L=5 pf, 480 Mbps (PRBS=2 15 1) Note: 6. Guaranteed by characterization. T A =- 40 to +85 C Min. Typ. Max. Units 3.0 to 3.6 20 ps 3.0 to 3.6 200 ps Capacitance Symbol Parameter Conditions T A =- 40 to +85 C Min. Typ. Max. Units C IN Control Pin Input Capacitance V CC=0 1.5 pf C OUT INT Pin Output Capacitance V CC=0 2.5 pf C ON D+/D- On Capacitance V CC=3.3 V, f=1 MHz, Figure 11 7.0 7.9 pf C OFF D1n, D2n Off Capacitance V CC=3.3 V, Figure 10 2.0 pf FSUSB45 Rev. 1.0.7 5
Test Diagrams V ON HSD1n V SW Dn HSD2n A D+, D- VSW I ON Select V Sel = 0 orvcc Sel 0 or VCC R ON = V ON / I ON Figure 4. On Resistance Figure 5. Off/On Leakage Dn t RISE = 2.5ns t FALL = 2.5ns V SW V Sel C L R L,, and C L are functions of the application environment (see AC Tables for specific values) C L includes test fixture and stray capacitance. Figure 6. AC Test Circuit Load R L V CC Input V /OE, V Sel 90% 90% V CC /2 V CC /2 10% 10% V OH 90% 90% Output- V OL t ON t OFF Figure 7. Turn-On / Turn-Off Waveforms t RISE= 500ps t FALL = 500ps +400mV -400mV 10% 0V 90% 90% 10% Output t PHL t PLH Figure 8. Propagation Delay (t Rt F 500ps) Figure 9. Intra-Pair Skew Test t SK(P) Capacitance Meter S V Sel = 0 or V cc Capacitance Meter S V Sel = 0 or V cc Figure 10. Channel Off Capacitance Figure 11. Channel On Capacitance FSUSB45 Rev. 1.0.7 6
Test Diagrams (Continued) t RISE = 2.5ns V SW1 V SW2 Dn C L R L V cc Input - V Sel 0V 10% 0.9*V out 90% V cc /2 0.9*V out t BBM V Sel R L,, and C L are functions of the application environment (see AC Tables for specific values) C L includes test fixture and stray capacitance. Figure 12. Break-Before-Make Interval Timing Network Analyzer V IN V S V Sel R T and R T are functions of the application environment (see AC Tables for specific values). Figure 13. Bandwidth Network Analyzer V Sel and R T are functions of the application environment (see AC Tables for specific values). R T V IN R T Off isolation = 20 Log ( / V IN ) Figure 14. Channel Off Isolation V S NC Network Analyzer V IN V S V Sel R T and R T are functions of the application environment (see AC Tables for specific values). Crosstalk = 20 Log ( / V IN ) Figure 15. Non-Adjacent Channel-to-Channel Crosstalk R T FSUSB45 Rev. 1.0.7 7
Physical Dimensions 2X 0.10 C 2.10 A B (0.11) 1.62 KEEPOUT ZONE, NO TRACES OR VIAS ALLOWED 1.60 1.12 0.56 PIN1 IDENT IS 2X LONGER THAN OTHER LINES TOP VIEW 2X 0.10 C 0.50 (0.35) 10X (0.25) 10X RECOMMENDED LAND PATTERN 0.55 MAX 0.05 C 0.05 C C SIDE VIEW 0.05 0.00 (0.20) 0.35 0.25 DETAIL A 0.35 0.25 D 0.65 0.55 1 4 (0.36) 0.56 (0.15) 0.35 0.25 DETAIL A 2X SCALE (0.29) 0.50 10 5 9 6 1.62 BOTTOM VIEW 0.25 9X 0.15 0.35 9X 0.25 0.10 C A B 0.05 C ALL FEATURES NOTES: A. PACKAGE CONFORMS TO JEDEC REGISTRATION MO-255, VARIATION UABD. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. PRESENCE OF CENTER PAD IS PACKAGE SUPPLIER DEPENDENT. IF PRESENT IT IS NOT INTENDED TO BE SOLDERED AND HAS A BLACK OXIDE FINISH. E. DRAWING FILENAME: MKT-MAC10Arev5. Figure 16. 10-Lead MicroPak Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/ma/mac10a.pdf. FSUSB45 Rev. 1.0.7 8
Physical Dimensions 2X 0.10 C 1.40 A B 1.70 (9X) 0.663 0.563 PIN#1 IDENT 1.80 1 2.10 TOP VIEW 0.10 C 2X 0.40 (10X)0.225 0.10 C 0.55 MAX. (0.15) RECOMMENDED LAND PATTERN 0.08 C 0.05 0.00 DETAIL A PIN#1 IDENT 0.25 0.15 45 SEATING PLANE SIDE VIEW 0.35 0.45 (9X) 3 1 10 BOTTOM VIEW 0.55 0.45 DETAIL A SCALE : 2X 6 C 0.40 0.15 0.25 (10X) 0.10 C A B 0.05 C LEAD OPTION 1 SCALE : 2X PACKAGE EDGE LEAD OPTION 2 SCALE : 2X 0.55 0.40 (10X) 0.225 NOTES: 1.45 9X 0.45 1.85 OPTIONAL MINIMIAL TOE LAND PATTERN A. PACKAGE DOES NOT CONFORM TO ANY JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. LAND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY. E. DRAWING FILENAME: MKT-UMLP10Arev5. F. FAIRCHILD SEMICONDUCTOR. Figure 17. 10-Lead Ultrathin Molded Leadless Package (UMLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/um/umlp10a.pdf. FSUSB45 Rev. 1.0.7 9
FSUSB45 Rev. 1.0.7 10 FSUSB45 Hi-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect
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