Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science

Similar documents
RF CMOS 0.5 µm Low Noise Amplifier and Mixer Design

High Speed Communication Circuits and Systems Lecture 10 Mixers

3-Stage Transimpedance Amplifier

6.976 High Speed Communication Circuits and Systems Lecture 20 Performance Measures of Wireless Communication

Linear electronic. Lecture No. 1

SP 22.3: A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver

Design of Single to Differential Amplifier using 180 nm CMOS Process

High Frequency Amplifiers

6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators

Experiment 8 Frequency Response

Lecture 20: Passive Mixers

A 900MHz / 1.8GHz CMOS Receiver for Dual Band Applications*

Transceiver Architectures (III)

Homework Assignment 11

Chapter 14 Operational Amplifiers

Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B

Chapter 6. Case Study: 2.4-GHz Direct Conversion Receiver. 6.1 Receiver Front-End Design

6.976 High Speed Communication Circuits and Systems Lecture 8 Noise Figure, Impact of Amplifier Nonlinearities

ECE4902 C Lab 7

1-GHz and 2.8-GHz CMOS Injection-locked Ring. Oscillator Prescalers. Rafael J. Betancourt-Zamora, Shwetabh Verma. and Thomas H.

ECEN 474/704 Lab 6: Differential Pairs

CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN

1-GHz and 2.8-GHz CMOS Injection-locked Ring Oscillator Prescalers

Analysis and Design of Analog Integrated Circuits Lecture 1. Overview of Course, NGspice Demo, Review of Thevenin/Norton Modeling

A GSM Band Low-Power LNA 1. LNA Schematic

ISSCC 2004 / SESSION 26 / OPTICAL AND FAST I/O / 26.6

Homework Assignment 12

A 1MHz-64MHz Active RC TI-LPF with Variable Gain for SDR Receiver in 65-nm CMOS

ME 365 EXPERIMENT 7 SIGNAL CONDITIONING AND LOADING

Receiver Architecture

Course Project Topic: RF Down-Conversion Chain Due Dates: Mar. 24, Apr. 7 (Interim reports), Apr. 28 (Final report)

Designing a 960 MHz CMOS LNA and Mixer using ADS. EE 5390 RFIC Design Michelle Montoya Alfredo Perez. April 15, 2004

CMOS Cascode Transconductance Amplifier

CHAPTER 3 CMOS LOW NOISE AMPLIFIERS

2.Circuits Design 2.1 Proposed balun LNA topology

Lecture 17 Date: Parallel Resonance Active and Passive Filters

Radio-Frequency Conversion and Synthesis (for a 115mW GPS Receiver)

CHAPTER 14. Introduction to Frequency Selective Circuits

Design of a Low Power 5GHz CMOS Radio Frequency Low Noise Amplifier Rakshith Venkatesh

Chapter 10: Operational Amplifiers

Chapter 2. The Fundamentals of Electronics: A Review

THE INTERNATIONAL JOURNAL OF SCIENCE & TECHNOLEDGE

6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers

CMOS RFIC Design for Direct Conversion Receivers. Zhaofeng ZHANG Supervisor: Dr. Jack Lau

CMOS Dual Band Receiver GSM 900-Mhz / DSS-GSM1800-GHz

Advanced Operational Amplifiers

University of North Carolina, Charlotte Department of Electrical and Computer Engineering ECGR 3157 EE Design II Fall 2009

Homework Assignment True or false. For both the inverting and noninverting op-amp configurations, V OS results in

Multimode 2.4 GHz Front-End with Tunable g m -C Filter. Group 4: Nick Collins Trevor Hunter Joe Parent EECS 522 Winter 2010

Assignment 11. 1) Using the LM741 op-amp IC a circuit is designed as shown, then find the output waveform for an input of 5kHz

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier

UNIVERSITY OF UTAH ELECTRICAL ENGINEERING DEPARTMENT

Texas A&M University Electrical Engineering Department ECEN 665. Laboratory #3: Analysis and Simulation of a CMOS LNA

STATION NUMBER: LAB SECTION: Filters. LAB 6: Filters ELECTRICAL ENGINEERING 43/100 INTRODUCTION TO MICROELECTRONIC CIRCUITS

5.4: A 5GHz CMOS Transceiver for IEEE a Wireless LAN

Noise Figure Degradation Analysis of Power/Ground Noise on 900MHz LNA for UHF RFID

Electronic Noise. Analog Dynamic Range

DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 02139

6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers

Electronics basics for MEMS and Microsensors course

EE 140 / EE 240A ANALOG INTEGRATED CIRCUITS FALL 2015 C. Nguyen PROBLEM SET #7

Self Calibrated Image Reject Mixer

A 2.4 GHZ RECEIVER IN SILICON-ON-SAPPHIRE MICHAEL PETERS. B.S., Kansas State University, 2009 A REPORT

Single-Ended to Differential Converter for Multiple-Stage Single-Ended Ring Oscillators

Up to 6 GHz Low Noise Silicon Bipolar Transistor Chip. Technical Data AT-41400

EE4902 C Lab 7

Bluetooth Receiver. Ryan Rogel, Kevin Owen I. INTRODUCTION

433MHz front-end with the SA601 or SA620

6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers

1-13GHz Wideband LNA utilizing a Transformer as a Compact Inter-stage Network in 65nm CMOS

TSEK03: Radio Frequency Integrated Circuits (RFIC) Lecture 5-6: Mixers

University of Southern C alifornia School Of Engineering Department Of Electrical Engineering

Başkent University Department of Electrical and Electronics Engineering EEM 311 Electronics II Experiment 8 OPERATIONAL AMPLIFIERS

Op-Amp Simulation Part II

A-1.8V Operation Switchable Direct-Conversion Receiver with sub-harmonic mixer

2005 IEEE. Reprinted with permission.

Chapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers

EECS 290C: Advanced circuit design for wireless Class Final Project Due: Thu May/02/2019

AN-742 APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA Tel: 781/ Fax: 781/

System-on-Chip. Electro-thermal effects in radio ICs. Overview. Tri-band GSM radio receiver (front-end)

Twelve voice signals, each band-limited to 3 khz, are frequency -multiplexed using 1 khz guard bands between channels and between the main carrier

Lecture 15: Introduction to Mixers

Homework Assignment 05

Dual-Frequency GNSS Front-End ASIC Design

A Low Power 900MHz Superheterodyne Compressive Sensing Receiver for Sparse Frequency Signal Detection

ATF High Intercept Low Noise Amplifier for the MHz PCS Band using the Enhancement Mode PHEMT

Low Cost Mixer for the 10.7 to 12.8 GHz Direct Broadcast Satellite Market

EE12: Laboratory Project (Part-2) AM Transmitter

You will be asked to make the following statement and provide your signature on the top of your solutions.

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers

Keywords: ISM, RF, transmitter, short-range, RFIC, switching power amplifier, ETSI

Experiment 9- Single Stage Amplifiers with Passive Loads - MOS

Mixer. General Considerations V RF VLO. Noise. nonlinear, R ON

Assist Lecturer: Marwa Maki. Active Filters

1.25Gbps/2.5Gbps, +3V to +5.5V, Low-Noise Transimpedance Preamplifiers for LANs

HOME ASSIGNMENT. Figure.Q3

Electrical Circuits II (ECE233b)

CHAPTER - 3 PIN DIODE RF ATTENUATORS

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Electronic Circuits Spring 2007

it Gb/s NRZ Modulator Driver VD1 VCTRL1 OUT/VD2 Description Features Device Diagram Gain

Transcription:

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.976 High Speed Communication Circuits and Systems Spring 2003 Homework #4: Narrowband LNA s and Mixers Copyright c 2003 by Michael H. Perrott Reading: Chapters 11 and 12 of Thomas H. Lee s book. Chapter 6 and pages 138-146 of Behzad Razavi s book. 1. This problem will focus on design of the LNA shown in Figure 1. In the figure, L deg (L s ) is assumed to have infinite Q, but inductors L g and L d have associated resistances due to their finite Q (i.e., the values of R pg and R pd are set by the Q and inductance value of L g and L d, respectively). Assume the following Design of the LNA should be focused on its performance at frequency w o = (2π)2.5 GHz If an external inductor is used for L g, its Q is 40. For integrated inductors, assume the Q to be 5 (other than for L deg ). The LNA input impedance, Z in, must be designed to match that of the source resistance of 50 Ohms at frequency w o (Note: assume is a short at frequency w o, and ignore the influence of the 5 kohm bias resistor) The power dissipation of the core amplifier must be no greater than 10 mw. (Ignore the bias circuitry here) All transistor devices are the same size and have length L=0.18 µm The influence of the cascode device M 2 can be ignored for noise figure and gain calculations. Ignore C gd, C db, r o, and backgate effects for all transistors. Ignore the noise contribution of transistors M 2 and M 3 and the 5 kωbias resistor. Assume the following process parameters c = j0.55 γ =3 δ = 6 g m /g do =0.68 w t =(2π)42.8 GHz 1

I den = 100 µa/µm W g m = 1.8 0.78 ms, where W is transistor width in microns V dd =1.8 V L d I bias R pd M 3 5 kω 50 Ω L g R pg M 2 C L =1pF R ps x M 1 V in L s Z in Figure 1: Narrowband LNA. (a) Design the amplifier to achieve the minimum noise figure given the conditions stated above. State the resulting noise figure (at w o ), I bias, transistor widths, component values, and gain (at w o ) for the amplifier. For intermediate calculations, determine η, χ d,and Z gsw. (b) How does the noise figure change for part (a) if c = 0? (a numerical answer is required here) (c) How does the noise figure change for part (a) if c = j1? (a numerical answer is required here) 2. The following is based on Problem 4 in Chapter 12 of Thomas Lee s book. Here we consider the ideal multiplying mixer shown in Figure 2, whose input RF signal is Asin(w rf t) and whose signal is either a square-wave or sinusoidal waveform. Asin(w rf t) out Figure 2: Ideal multiplying mixer. (a) Derive the conversion gain of the mixer under the following conditions: 2

i. A square-wave waveform with peak-to-peak amplitude of 2B whose frequency is chosen such that the mixer output occurs at a nonzero IF frequency. ii. A sine-wave waveform with peak-to-peak amplitude of 2B whose frequency is chosen such that the mixer output occurs at a nonzero IF frequency. iii. A square-wave waveform with peak-to-peak amplitude of 2B whose frequency is chosen such that the mixer output occurs at zero IF frequency. iv. A sine-wave waveform with peak-to-peak amplitude of 2B whose frequency is chosen such that the mixer output occurs at zero IF frequency. (b) Comparing the above cases, is there a difference in conversion gain if the IF output occurs at zero or nonzero frequency? (c) Which type of signal achieves a higher conversion gain (assuming the same peak-to-peak amplitude)? (d) Given a non-zero IF frequency, compare the relative requirements on a post-mixer filter to reject undesired frequency components for square-wave and sine-wave signals. Present your arguments using pictures of the appropriate Fourier transforms of the relevant signals. 3. This problem is based on Problems 5 and 6 in Chapter 12 of Thomas Lee s book. Here we focus on the double-balanced mixer shown in Figure 3. It will be assumed that a nonzero IF output frequency is sought in all cases. R S /2 C L V dd 0 2A in V in R L /2 R L /2 0 V V dd 0 R S /2 Figure 3: A double-balanced passive CMOS mixer. (a) Given that R L is set equal to R S, what is the conversion gain of the mixer? Assume infinitely fast switching, neglect switch resistance, and assume that the post-mixer RC filter formed by R L and C L has higher bandwidth than the desired IF output. 3

(b) Repeat part (a) given non-zero switch resistance (denoted as R sw ). What is the maximum acceptable switch resistance if the degradation in conversion gain (relative to part (a)) is not to exceed 1 db? (c) How does the filter requirement change if the drive does not possess a perfect 50 % duty cycle? Express your answer using pictures of the appropriate Fourier transforms where you have considered the impact of the non-50% duty cycle square wave. Based on this exercise, how important is the achievement of symmetry in device switching for the mixer? 4. This problem focuses on the analysis and simulation of the Weaver image rejection mixer architecture shown in Figure 4. LPF A C RF Input sin(w 1 t) sin(w 2 t) Baseband Output cos(w 1 t) cos(w 2 t) LPF B D RF input Desired Signal Image f -f i -f 1 -f d f d f 1 f i Figure 4: The Weaver image rejection mixer architecture. (a) Given the RF signal Fourier transform shown in Figure 4, what condition is required for the signal centered at f i to be the image of the desired signal centered at f d (i.e., what is the relationship between f i, f d,and f 1?). (b) Given the relationship in part (a), what value should be chosen for f 2 so that the overall mixer output is at baseband frequencies (i.e., has an IF frequency of zero)? (c) Given the conditions in part (a) and (b), sketch the Fourier transforms of the signals at nodes A, B, C, D, and the overall output of the mixer. (d) Verify operation of the mixer by simulating the system in Figure 4 using CppSim given f 1 =1GHz, f d = 900 MHz, the lowpass cutoff frequencies are at 150 MHz, 4

and f 2 is appropriately chosen for baseband conversion. Rather than inputing an RF signal as shown in the figure (which would be rather challenging), simply input two sinusoidal signals. One of the signals should be placed at the center of the desired frequency band, and the other should be placed just slightly offset from its respective image frequency location (offset so that you can view it distinctly from the desired location if it were to not be completely rejected in the final output). Note that you ll need to create new CppSim module blocks for the mixers and lowpass filter. Turn in the module code and plots at A, C, and the Output. Hint: Make sure that your input is real-valued. (e) Now modify your CppSim simulation to observe the impact of phase mismatch between the cosine and sine waves at frequency f 1. Specifically, phase shift the sine wave by 1 degree and then measure the corresponding image rejection ratio at DC based on the simulation results. 5