Daa Shee, Rev.., July 2009 TE 8444S Quad Half-Bridge Driver IC Auomoive Power
Table of Conens Table of Conens Overview....................................................................... 3 2 Block Diagram................................................................... 4 3 Pin Configuraion................................................................ 6 3. Pin Assignmen................................................................... 6 3.2 Pin Definiions and Funcions........................................................ 6 4 General Produc Characerisics.................................................... 8 4. Absolue Maximum Raings......................................................... 8 4.2 Funcional Range................................................................. 9 4.3 Thermal Resisance............................................................... 9 4.4 Elecrical Characerisics.......................................................... 0 5 Block Descripion............................................................... 2 5. Power Supply................................................................... 2 5.. General...................................................................... 2 5..2 Sleep Mode................................................................... 2 5..3 Reverse Polariy............................................................... 3 5.2 Inpu / Oupu Sages............................................................. 4 5.3 Monioring Funcions............................................................. 6 5.3. Diagnosics................................................................... 6 5.3.2 Power Supply Monioring......................................................... 7 5.3.3 Temperaure Monioring......................................................... 8 5.4 Power-Oupus -4 (Half Bridge Oupus).............................................. 9 5.4. Proecion and Diagnosis......................................................... 9 5.4.. Shor Circui of Oupu o Ground or Vs............................................ 9 5.4..2 Open oad.................................................................. 23 5.5 Oupu Swiching Capabiliy........................................................ 24 5.5. Applicaion Noe for Bipolar Sepper Moor Conrol..................................... 28 6 Package Oulines............................................................... 30 7 Revision Hisory................................................................ 3 Daa Shee 2 Rev.., 2009-07-07
Quad Half-Bridge Driver IC TE 8444S Overview Feaures 4 Half-Bridge Power Oupus (.3Ω R DS(ON)MAX @ T j =50 C) Minimum Overcurren Shudown a 0.9A Simple parallel inerface conrol of Half-Bridge Oupus Invered and Non-invered Inpus o minimize number of microconroller connecions Very low curren consumpion in sleep mode (max. 5µA) Error Flag Diagnosis Open oad Diagnosis in ON-sae for all oupus Oupus proeced agains overcurren Over emperaure proecion wih hyseresis Over and Under volage lockou 3.3V / 5V compaible inpus wih hyseresis No crossover curren Inernal freewheeling diodes Thermally enhanced package (fused leads) Green Produc (RoHS complian) AEC Qualified PG-SSOP-24-7 Descripion The TE 8444S is a proeced Quad-Half-Bridge-IC argeed owards auomoive and indusrial moion conrol applicaions. I is a monolihic die based on Infineon s smar mixed echnology SPT which combines bipolar and CMOS conrol circuiry wih DMOS power devices. DC-Moors can be driven in forward (cw), reverse (ccw), brake and high impedance modes where as Sepper- Moors can be driven in No-Curren, negaive / posiive oupu curren modes. These various modes can easily be achieved via sandard parallel inerface of he device o a microconroller. The PG-SSOP-24-7 package is advanageous as i saves PCB-board space and coss. The inegraed shor circui and over-emperaure proecion as well as i s buil-in diagnosis feaures such as over- and under volage-lockou and open load deecion improves sysem reliabiliy and performance. Targe Applicaions: Unipolar or Bipolar oads Sepper Moors (e.g. Idle Speed Conrol) DC brush Moors Type Package Marking TE 8444S PG-SSOP-24-7 TE8444S Daa Shee 3 Rev.., 2009-07-07
Block Diagram 2 Block Diagram VS TE8444 Inernal Supply Vs monior under/overvolage deecion IN IN2 Funcion ogic OUT+2 Proeced Driver Sage OUT+2 OUT OUT2 INH Inhibi EF EF2 Error Flag Generaion Charge Pump OUT3 IN3 IN4 Funcion ogic OUT3+4 Proeced Driver Sage OUT3+4 OUT4 Figure Block Diagram Daa Shee 4 Rev.., 2009-07-07
Block Diagram V S I S VS V DSHSx V FU INH V INH, V INHH, V INH I INHH TE8444 V EFx, V EFx I EFKx EFx OUTx I OUTx I INx V DSSx V F INx V INx, V INHx, V INx I Figure 2 Terms Daa Shee 5 Rev.., 2009-07-07
Pin Configuraion 3 Pin Configuraion 3. Pin Assignmen OUT VS EF IN IN2 EF2 VS OUT 2 2 3 4 5 6 7 8 9 0 2 24 23 22 2 20 9 8 7 6 5 4 3 n.c. OUT3 VS n.c. IN3 IN4 INH n.c. VS OUT 4 n.c. Figure 3 Pin Configuraion 3.2 Pin Definiions and Funcions Pin Symbol Funcion, 2,, 2, 20 Ground; Signal ground; All pins mus be exernally conneced ogeher o he common poenial 3 OUT Power Oupu of Half-bridge Shor circui proeced; wih inegraed free-wheeling diodes 4, 9, 5, 22 V S Power Supply Volage; All V S pins mus be exernally conneced ogeher o he Baery Volage wih Reverse proecion Diode, buffer capaciance and Filer agains EMC. See Applicaion Diagram, Figure 8 and Figure 9 for more informaion 5 EF Error Flag (Diagnosis Oupu) Open drain by defaul; ow = error 6 IN Inpu Channel of Half-bridge Conrols OUT, Non-invering Inpu wih inernal Pull Down 7 IN2 Inpu Channel of Half-bridge 2 Conrols OUT2, Invering Inpu wih inernal Pull Up 8 EF2 Error Flag 2 (Diagnosis Oupu) Open drain by defaul; ow = error 0 OUT2 Power Oupu of Half-bridge 2 Shor circui proeced; wih inegraed free-wheeling diodes 3, 6, 2, 24 N.C. No Conneced Daa Shee 6 Rev.., 2009-07-07
Pin Configuraion Pin Symbol Funcion 4 OUT4 Power Oupu of Half-bridge 4 Shor circui proeced; wih inegraed free-wheeling diodes 7 INH Inhibi Inpu ow = Device in sleep mode 8 IN4 Inpu Channel of Half-bridge 4 Conrols OUT4, Invering Inpu wih inernal Pull Up 9 IN3 Inpu Channel of Half-bridge 3 Conrols OUT3, Non-invering Inpu wih inernal Pull Down 23 OUT3 Power Oupu of Half-bridge 3 Shor-circui proeced; wih inegraed free-wheeling diodes Daa Shee 7 Rev.., 2009-07-07
General Produc Characerisics 4 General Produc Characerisics 4. Absolue Maximum Raings Absolue Maximum Raings ) T j = -40 C o +50 C; all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Pos. Parameer Symbol imi Values Uni Condiions Min. Max. Volages 4.. Supply volage V S -0.3 40 V 4..2 ogic inpu volages (IN; IN2; IN3; IN4; INH) V IN(-4) -0.3 5.5 V 0 V < V S < 40 V V INH 4..3 ogic oupu volage V EF(+2) -0.3 5.5 V 0 V < V S < 40 V (EF ; EF 2 ) Currens 4..4 Oupu curren (diode) I OUT(-4) - A 4..5 Oupu curren (EF ; EF 2 ) I EF(-2) -2 5 ma Temperaures 4..6 Juncion emperaure T j -40 50 C 4..7 Sorage emperaure T sg -50 50 C ESD Suscepibiliy 4..8 ESD capabiliy of OUT and V S pin vers. V ESD -2 2 kv 2) 4..9 ESD capabiliy of logic pins vers. V ESD -2 2 kv 2) ) No subjec o producion es, specified by design. 2) Human Body Model according o ANSI EOS\ESD S5. sandard (eqv. o MI STD 883D and JEDEC JESD22-A4) Noe: Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. Noe: Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. Daa Shee 8 Rev.., 2009-07-07
General Produc Characerisics 4.2 Funcional Range Pos. Parameer Symbol imi Values Uni Condiions Min. Max. 4.2. Supply Volage Range for V S(nor) 8 8 V Normal Operaion 4.2.2 Exended Supply Volage Range for Operaion V S(ex) V UV OFF V OV OFF V imi values, deviaions possible; Afer V S rising above V UV ON 4.2.3 Supply volage increasing V S -0.3 V UV ON V Oupus are open 4.2.4 Supply volage decreasing V S -0.3 V UV OFF V Oupus are open 4.2.5 ogic inpu volages (IN; IN2; IN3; IN4; INH) Noe: Wihin he funcional range he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he relaed elecrical characerisics able. 4.3 Thermal Resisance V IN(-4) -0.3 5.5 V V INH 4.2.6 Juncion emperaure T j -40 50 C Noe: This hermal daa was generaed in accordance wih JEDEC JESD5 sandards. For more informaion, go o www.jedec.org. Pos. Parameer Symbol imi Values Uni Condiions Min. Typ. Max. 4.3. Juncion o Soldering Poin ) R hjsp 26 K/W pin, 2,, 2 2) 4.3.2 Juncion o Ambien ) R hja 60 K/W 3) ) No subjec o producion es, specified by design 2) Specified RhJS value is simulaed a naural convecion on a cold plae seup (all pins are fixed o ambien emperaure). Ta=25 C, S+HS2+S3+HS4 are dissipaing W (0.25W each). 3) Specified RhJA value is according o Jedec JESD5-2,-7 a naural convecion on FR4 2s2p board; The Produc (Chip+Package) was simulaed on a 76.2 x 4.3 x.5 mm board wih 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Ta=25 C, S+HS2+S3+HS4 are dissipaing W (0.25W each). Daa Shee 9 Rev.., 2009-07-07
General Produc Characerisics 4.4 Elecrical Characerisics 4.4.3 Elecrical Characerisics V S = 8 V o 8 V, T j = -40 C o +50 C, INH = HIGH; I OUT-4 = 0 A; all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Pos. Parameer Symbol imi Values Uni Condiions Min. Typ. Max. Curren Consumpion, INH = 4.4. Quiescen curren I S 5 µa V S = 3.5 V; T j < 85 C Curren Consumpion, INH = HIGH 4.4.2 Supply curren I S 5 0 ma IN+3=, IN2+4=H Over- and Under Volage ockou 4.4.3 UV Swich ON volage V UV ON 4.2 5 V V S increasing, see Figure 6 4.4.4 UV Swich OFF volage V UV OFF 4 4.8 V V S decreasing, see Figure 6 4.4.5 UV ON/OFF hyseresis V UV HY 0.05 0.26 0.7 V V UV ON - V UV OFF, see Figure 7 4.4.6 OV Swich OFF volage V OV OFF 2 25 V V S increasing, see Figure 6 4.4.7 OV Swich ON volage V OV ON 20 24 V V S decreasing, see Figure 6 4.4.8 OV ON/OFF hyseresis V OV HY V V OV OFF - V OV ON, see Figure 7 Saic Drain-source ON-Resisance 4.4.9 High- and low-side swich R DSON 0.6 0.8 Ω I OUT = ±0.8 A; T j = 25 C.0.3 Ω I OUT = ±0.8 A; T j = 50 C Oupu Proecion and Diagnosis 4.4.0 Shor Circui Curren ) I SC(-4).8 2.4 3.2 A HS+S each Channel, see Figure 3 4.4. Overcurren Shudown I SD(-4) 0.9.2.6 A Threshold 4.4.2 Shudown Delay Time dsd(-4) 0 25 50 µs 4.4.3 Open oad Deecion Curren I OD(-4) 6 2 20 ma each S Channel, see Figure 5 4.4.4 Open oad Delay Time dod(-4) 200 350 600 µs Oupu Swiching Times 4.4.5 high-side ON delay-ime donh 7 0 4 µs V S =3.5V, resisive oad 4.4.6 high-side swich ON ime ONH 2 6 9 µs =00Ω, 4.4.7 high-side OFFdelay-ime doffh 2 4 µs see Figure 6 and Figure 7 4.4.8 high-side swich OFF ime OFFH 0.2 2 µs 4.4.9 low-side ON delay-ime don 2 5 8 µs 4.4.20 low-side swich ON ime ON 0.5 3 µs 4.4.2 low-side OFF delay-ime doff 2 5 µs 4.4.22 low-side swich OFF ime OFF 0.5 2 µs 4.4.23 dead-ime DB 0. 2 µs donh - ONH - doff or don - ON - doffh Oupus OUT(-4), Freewheeling Diodes 4.4.24 Forward volage; upper V FU.5 V I F = 0.4 A, INH = OW Daa Shee 0 Rev.., 2009-07-07
General Produc Characerisics Elecrical Characerisics (con d) V S = 8 V o 8 V, T j = -40 C o +50 C, INH = HIGH; I OUT-4 = 0 A; all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Pos. Parameer Symbol imi Values Uni Condiions Min. Typ. Max. T 50 75 200 C T 25 75 C 4.4.25 Forward volage; lower V F 0.9.4 V I F = 0.4 A, INH = OW Inpu Inerface, ogic Inpus IN, IN2, IN3, IN4 4.4.26 High-inpu volage IN, IN3 V INH(+3) 2 V 4.4.27 ow-inpu volage IN, IN3 V IN(+3) 0.8 V 4.4.28 High-inpu volage IN2, IN4 V INH(2+4) 2 V 4.4.29 owh-inpu volage IN2, IN4 V IN(2+4) 0.8 V 4.4.30 Hyseresis of inpu volage V INHY 0. 0.3 V 4.4.3 Pull down curren I IN(+3) 0 25 50 µa V IN(+3) = 2 V 4.4.32 Pull up curren I IN(2+4) 0 25 50 µa V IN(2+4) = 0.8V Inpu Inerface, ogic Inpus INH 4.4.33 High-inpu volage V INHH 2 V 4.4.34 ow-inpu volage V INH 0.8 V 4.4.35 Hyseresis of inpu volage V INHHY 0.25 V 4.4.36 Pull down curren I INH 0 25 50 µa V INH = 2 V 4.4.37 Disable Delay Time ddis 00 µs VS=3.5V, resisive 4.4.38 Enable Delay Time den 00 µs oad=00ω, see Figure 4 4.4.39 Time delay o Sleep Mode SEEP - 40 µs INH = OW unil Sleep mode is reached Inpu Inerface, Error-Flags EF(+2) 4.4.40 ow-oupu volage level V EF(+2) 0.2 0.4 V I EF(+2) = 2 ma 4.4.4 eakage curren I EFK(+2) 0 µa 0 V < V EF(+2) < 5.5 V 4.4.42 Error delay ime def 5 0 µs Thermal Shudown 4.4.43 Thermal shudown juncion emperaure ) jsd 4.4.44 Thermal swich-on juncion emperaure ) jso ) No subjec o producion es, specified by design Daa Shee Rev.., 2009-07-07
Block Descripion 5 Block Descripion 5. Power Supply 5.. General The TE 8444S has one power supply inpu V S which is conneced o he auomoive 2V board-ne. All power drivers are conneced o his supply volage V S. The logic supply volage for he inegraed driver sages and logic block is generaed by an inernal bandgap reference circui derived from he 2V board-ne. To block he supply volage of he device, a 47µF elecrolyic capaciance is recommended. For EMC improvemens a 00nF ceramic capaciance can be added and should be placed as close as possible o he V S -Pin of he device. See Applicaion Diagrams, Figure 8 and Figure 9 for more informaion. 5..2 Sleep Mode The TE 8444S can be placed in low curren-consumpion mode (or sleep mode) by seing he inpu, INH pin o OW. The INH pin has an inernal pull-down curren source. In sleep-mode, all oupu ransisors are swiched off. An oupu disable and enable ime is specified and his behavior is shown in Figure 4 below. V High INH 50% 50% ow A ON 90% I OUTx OFF ddis 0% den Figure 4 Enable and Disable Delay Time Daa Shee 2 Rev.., 2009-07-07
Block Descripion 5..3 Reverse Polariy The TE 8444S requires an exernal reverse polariy proecion. This proecion is essenial o avoid an undesired reverse curren (I RB ) o flow from ground poenial o baery causing excessive power dissipaion across he diodes in he even of reverse polariy. Hence a reverse polariy proecion diode is recommended (Figure 5). a) b) VS DRP HSx HSx CS2 CS DZS OUTx OUTx Sx TE8444 Sx TE8444 IRB VS Figure 5 Reverse Polariy Proecion Daa Shee 3 Rev.., 2009-07-07
Block Descripion 5.2 Inpu / Oupu Sages Inpu Circui The conrol inpus consis of TT/CMOS-compaible schmi-riggers wih hyseresis. Inpus IN and IN3 have inernal pull down circuis whereas IN2 and IN4 have inernal pull up circuis. If no signal is applied o he inpus and INH=HIGH, hen he drivers will by defaul be placed in Brake mode. In sleep mode, he oupus are swiched OFF (risae or HIgh-Z). For opimized bipolar sepper moor conrol applicaions, he IN2 and IN4 inpus have inernal invering srucures. This concep allows IN+IN2 and IN3+IN4 o be ied ogeher, which ulimaely reduces µc oupu pins and provides a 2-phase ype of conrol o he device (refer o Figure 9 and Figure 2). Oupu sages The oupu sages consis of a oal of 4 DMOS Half-bridges. Inegraed circuis proec he oupus agains overcurren and overemperaure. Posiive and negaive volage spikes, which occur during swiching of inducive loads, are supressed hrough inegraed free-wheeling diodes. The Truh Table below shows he oupu behavior of OUT and OUT2 for DC-moor applicaions. The same able is also applied o OUT 3 and OUT4. Table Funcional Truh Table of Half-bridge and 2 for DC-Moor Applicaion INH IN IN2 OUT OUT2 Mode 0 X open 0 0 X open Z Noe: Half-Bridges and 2 form a full bridge The Truh Table below shows he oupu behavior of OUT and OUT2 for bipolar Sepper-moor applicaions. The same able is also applied o OUT 3 and OUT4. Noe: Half-Bridges and 2 form a full bridge 0 0 H H Z H H Sleep Mode (ow curren consumpion mode) Brake (boh low side ransisors urned-on) DC-Moor urns counerclockwise (CCW) Brake (boh low side ransisors urned-on) Brake HH (boh high side ransisors urned-on) DC-Moor urns clockwise (CW) Table 2 Funcional Truh Table of Half-bridge and 2 for Bipolar Sepper Moor Applicaion INH IN IN2 OUT OUT2 Mode 0 X open 0 0 X open 0 0 Z H H Z H H Sleep Mode (ow curren consumpion mode) no curren (boh low side ransisors urned-on) negaive phase curren no curren (boh low side ransisors urned-on) no curren (boh high side ransisors urned-on) posiive phase curren Daa Shee 4 Rev.., 2009-07-07
Block Descripion IN, IN3 OUT, OUT3 0 = ogic OW ow side ransisor is urned-on High side ransisor is urned-off = ogic HIGH High side ransisor is urned-on ow side ransisor is urned-off IN2, IN4 OUT2, OUT4 0 = ogic OW High side ransisor is urned-on ow side ransisor is urned-off = ogic HIGH ow side ransisor is urned-on High side ransisor is urned-off X = don care X = don care Z = High- and owside ransisor are urned-off (Oupu in Trisae, High Z) Daa Shee 5 Rev.., 2009-07-07
Block Descripion 5.3 Monioring Funcions 5.3. Diagnosics The EF and EF2 pins are open drain oupus and mus be exernally conneced via pull-up resisors o 5V. In normal condiions, he EF and EF2 signals are by defaul high. In case of an error, EF and EF2 pins are pulled low. There are 3 differen error condiions ha could flag a faul condiion: 5.3.. Overcurren Oupu shored o Ground: If an oupu ransisor is urned on and he curren rises above he shudown hreshold I SD for longer han he shudown delay ime d_sd, he oupu ransisor is urned off and he corresponding diagnosis bi is se. Wihin his delay ime, he curren is limied o I SC as shown in Figure 9. Changing he INHIBIT inpu reses he error flag. Also a power down even will rese he Error Flag. a) Oupu shor o VS: same behavior as shor o. b) Shor across he load: same behavior as shor o. 5.3..2 Open load If he curren hrough he low side ransisor is lower han he reference curren I OD in ON-sae for longer han he open-load deecion delay ime d_od, he open-load error flag is se. The oupu will remain ON. Once he oupu curren increases and I load > I OD, he Error Flag will be rese auomaically afer he d_od filer ime (Figure 5). 5.3..3 Over volage / over emperaure a) Over volage: For volages below he undervolage swich OFF hreshold (V UVOFF ) and above he overvolage swich OFF hreshold (V OVOFF ), he oupu sages will be swiched OFF. The Error Flag however only signals he overvolage swich OFF case (Figure 6). A swiching hyseresis is implemened a boh hresholds o allow an auorecovery mode if he supply volage is back wihin he operaional range. b) Over Temperaure: A a juncion emperaure higher han he hermal shudown emperaure T jsd (yp. 75 C) he device eners hermal shudown which urns-off all four oupu sages simulaneously and he corresponding Error Flags are se wih a delay. Afer cooling down o he hermal swich-on juncion emp T jso he device will auo resar. A hermal oggle behavior can be observed (he Error Flags and oupu sages will be modulaed by he hermal ime consans; Figure 8). The Table below shows he behavior of he Error Flags: Table 3 Diagnosis EF EF2 Inerpreaion of Error Error Flag behavior Oupu saus Prioriy 0 0 0 0 no error overcurren open load over volage / over emperaure - lach auo recovery auo recovery normal operaion lached swich OFF normal operaion auo recovery - 2 3 Daa Shee 6 Rev.., 2009-07-07
Block Descripion 5.3.2 Power Supply Monioring The power supply Volage V S is moniored for over- and under volage (refer o block diagram: Figure ). Figure 6 shows he error flag signalling during an undervolage and overvolage siuaion where as Figure 7 shows he hyseresis concep implemened during undervolage and overvolage. Under Volage If he supply volage V S drops below he swich off volage V UVOFF, all oupu ransisors are swiched off bu he he Error Flags remain high (no error). If V S rises again and reaches he swich on volage V UVON, he power sages are resared. Over Volage If he supply volage V S rises above he swich off volage V OVOFF, all oupu ransisors are swiched off and he Error Flags are se. The error is no lached, i.e. if V S falls again and reaches he swich on volage V OVON, he power sages are resared and he Error Flags are rese. V S V OVHY V OVOFF VOVON V UVHY V UVOFF V UVON V OUTx ON High Z Error Saus undervolage wihou error signalling overvolage wih error signalling EF d_ef d_ef H EF 2 d_ef d_ef H Figure 6 Error Flag behavior for he Over- and Undervolge case Daa Shee 7 Rev.., 2009-07-07
Block Descripion VOUT H V UVHY V UVHY VS V UVOFF (min) VUVON (min) VUVOFF (max) VUVON (max) Figure 7 Undervolage Hyseresis 5.3.3 Temperaure Monioring Temperaure sensors are inegraed in he power sages. Each half bridge (HS+S) is equipped wih one emperaure sensor. The emperaure monioring circui compares he measured emperaure o he shudown hresholds. If one or more emperaure sensors reach he shudown emperaure T jsd, he overemperaure Error Flag is se o OW. This Error Flag is no lached (i.e. if he emperaure falls below he swich on hreshold T jso, he Error Flag is auomaically rese o HIGH again). This is shown in Figure 8 below. T j T jsd Τ T jso V OUTx ON High Z Error Saus no error overemperaure error EF d_ef d_ef H EF 2 d_ef d_ef H Figure 8 Overemperaure signalling Daa Shee 8 Rev.., 2009-07-07
Block Descripion 5.4 Power-Oupus -4 (Half Bridge Oupus) 5.4. Proecion and Diagnosis The device provides embedded proecive funcions. Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in his arge daashee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. 5.4.. Shor Circui of Oupu o Ground or Vs The low-side swiches are proeced agains shor circui o supply and he high-side swiches agains shor o. If a swich is urned on and he curren rises above he shudown hreshold I SD for longer han he shudown delay ime dsd, he oupu ransisor is urned off and he corresponding Error Flag is se. Wihin he delay ime, he curren is limied o I SC as shown in Figure 9. OUTx shor o Vs I SC I SD shor o I OUT dsd Figure 9 Shor circui proecion The delay ime is opimized o limi he power ha is dissipaed in he device during a shor circui even. This scheme allows high peak-currens as required in moor-applicaions during normal operaions. The oupu sage says off and he corresponding diagnosics oupu informaion is se unil INHIBIT oggles o low and high again or a power-on rese is performed. (refer o Figure 3) Daa Shee 9 Rev.., 2009-07-07
Block Descripion Conrol Inpu Delay d Inernal Supply S-Dirver MOC MO owside Power Transisor OUT EF2 Curren imi Rsense overcurren Rsense openload Gae Saus Delay + - VOC EF Error Flag Generaion d Delay d + - VO Power Figure 0 Simplified Schemaic for Shor circui proecion and Open oad deecion in S-swich VCHP VS EF2 Conrol Inpu Gae Saus HS-Driver HS-Dirver 2 Delay Curren imi + - VOC Rsense overcurren MOC Highside Power Transisor OUT Error Flag Generaion d Figure Simplified Schemaic for shor circui proecion in HS-swich Daa Shee 20 Rev.., 2009-07-07
Block Descripion V REF V REF - + RF-Blanking RR H = OT Shu down all oupu sages Temp Sensor Thermal Shu Down +V S RF-Blanking Shu down all oupu sages OR6 EF2 VREF + - UV RR H = OV > evel-shif OC_HS OC_HS2 OC_HS3 OC_HS4 OC_S OC_S2 OC_S3 OC_S4 O O2 O3 O4 OR > OR2 > OR4 > Delay d Delay d Delay d - + OC_HSD OC_SD RF-Blanking RR OR3 > H = UV Vsupply-Supervision OCD Overcurren-Inerface OD POR Shu down all oupu sages R S ERROR-FF & & Q Q OR5 > evel-shif EF Openload-Inerface Error-Inerface Figure 2 Simplified Schemaic of he TE8444 Error Flag Generaion Concep Daa Shee 2 Rev.., 2009-07-07
Block Descripion Shor Circui Diagnosis If a shor circui of a halfbridge oupu o is presen, he device will behave like displayed in Figure 3 below. INH acive mode SEEP acive mode IN x sleep mode I OUTx I SC I SD d_sd d_en d_sd EF 2 EF Figure 3 Overcurren signalling Daa Shee 22 Rev.., 2009-07-07
Block Descripion 5.4..2 Open oad Open-load deecion in ON-sae is implemened in he low-side ransisors of he bridge oupus. If he curren hrough he low side ransisor is lower han he reference curren I OD in ON-sae for longer han he open-load deecion delay ime d_od, he open-load error flag is se. The oupu ransisor, however, remains ON. The open load Error Flag has an auorecovery behavior. Example of open load deecion is shown below in Figure 4, Figure 5. HS S HS2 S2 OUT OUT 2 M Open oad Figure 4 Open oad example IN IN2 I OUT2 I OD EF d_od d_od d_od EF 2 V OUT V OUT2 Figure 5 Open oad signalling Daa Shee 23 Rev.., 2009-07-07
Block Descripion 5.5 Oupu Swiching Capabiliy Dead Time o preven Cross Currens In bridge configuraions he high-side and low-side power ransisors are ensured never o be simulaneously ON o avoid cross currens. This is usually assured by he inegraion of delays in he driver sage for he power oupus, generaing a so-called dead-ime beween swiching off one Power Transisors while swiching on he oher Power Transisor of he same half-bridge. To ensure ha here is no overlap of he swiching slopes ha would lead o a cross curren, a dead-ime db is specified. Refer o Figure 6 and he es circui in Figure 7. V INx H 50% 50% IOUT x donh doffh + Vs 00Ω onh 90% 90% offh db db no curren 0% 0% 0% 0% - Vs 00Ω 90% off 90% on doff don Figure 6 Swiching Time Definiions Daa Shee 24 Rev.., 2009-07-07
Block Descripion VS INH=High HSx IOUT x 00Ω INx A OUTx Sx TE8444 00Ω Figure 7 Swiching Time Characerizaion Circui Daa Shee 25 Rev.., 2009-07-07
Block Descripion Wachdog In Wachdog Ou Rese Ou Q CD 00 nf 8 4 9 CQ 22µF 6 D 3-5,0-2 7 VReg TE4678 G Rese Adjus 3 2 Wachdog Adjus Inpu RWA 00kΩ CI 00nF VBAT DRP WDO WDI R VCC REF2 REF CS2 CS DZS EF EF2 VS ( pin 4,9,5,22) OUT 00 nf 47µF M M INH OUT2 µc XC866 IN IN2 IN3 IN4 TE8444 OUT3 M2 M M2 M3 OUT4 ( pin,2,,2, 20) Two Moor separaely Three Moor cascaded Single moor, higher curren a b c Figure 8 Applicaion Circui for DC brush moor loads Figure 8a, Two Moor separaely: e.g. mirror x-y posiion. The moors can be driven independenly or in parallel. Figure 8b, Three Moor cascaded: e.g. HVAC flap conrol. The DC brush moors are never ON a he same ime. The swiching of he cascaded moors should happen one afer anoher. Due o his seup, 3 flaps can be driven, by saving one halfbridge. Figure 8c, Single Moor higher curren: Applicaions wih DC brush moors which require higher sall and inrush currens. The applicaion PCB layou of inpu and oupu races mus be as symmerical as possible o assure a proper behavior of he device. Noe : All VS and pins mus be exernally conneced ogeher. CS and CS2 capaciors mus be placed as close as possible o he Vs pin for opimized EMC performance. Daa Shee 26 Rev.., 2009-07-07
Block Descripion Wachdog In Wachdog Ou Rese Ou Q CD 00 nf 8 4 9 CQ 22µF 6 D 3-5,0-2 7 VReg TE4678 G Rese Adjus 3 2 Wachdog Adjus Inpu RWA 00kΩ CI 00nF VBAT DRP WDO WDI R VCC REF2 REF CS2 CS DZS VS 00 nf 47µF EF EF2 ( pin 4,9,5,22) OUT INH µc XC866 IN IN2 IN3 IN4 TE8444 OUT2 OUT3 M OUT4 ( pin,2,,2, 20) Bipolar Sepper Moor Figure 9 Applicaion Circui for bipolar sepper moor loads Noe : All VS and pins mus be exernally conneced ogeher. CS and CS2 capaciors mus be placed as close as possible o he Vs pin for opimized EMC performance. Daa Shee 27 Rev.., 2009-07-07
Block Descripion 5.5. Applicaion Noe for Bipolar Sepper Moor Conrol Curren Flow In a H-Bridge for sepper moor conrol To achieve a coninuous movemen of a bipolar sepper moor roor, he phase curren has o be reversed sep by sep. The curren flow hrough a fullbridge is displayed in Figure 20 below. Picure a) on he lef hand side shows a curren flow over HS he phase coil of he sepper moor load, he S2 o. The nex sep reverses he curren flow hrough he phase coil of he moor by swiching off HS and S2 and acivaing HS2 and S insead (Picure b). Vs Vs HS HS2 HS HS2 phase phase OUT OUT2 OUT OUT2 R phase R phase S S2 S S2 a b Figure 20 Reversing he curren in fullbridge operaion o achieve a sepper moor movemen Daa Shee 28 Rev.., 2009-07-07
Block Descripion Conrol paern for bipolar sepper moor applicaions Bipolar sepper moors applicaions for linear posiioning such as Idle Speed conrol requires a specific inpu signal paern which is displayed in Figure 2. Normally, he oupu swiching frequency is lower (approx. < 2kHz). This depends on he used moorload (/R raio). V IN = V IN2 High ow I OUT2 +Iload 0 -Iload V IN3 = V IN4 High ow I OUT34 +Iload 90 Phaseshif 0 -Iload Figure 2 Bipolar sepper moor conrol (full sep mode) Daa Shee 29 Rev.., 2009-07-07
Package Oulines 6 Package Oulines 0.35 x 45 ) 3.9 ±0. C 0.2-0. 0.25 8 MAX. 0.65 2) ±0.05 0.2-0. 0...8 B (.47).75 MAX. 0.7 M C A B 24x 0. B Seaing Plane 8 MAX. 0...8 6 ±0.2 0.9 +0.06 0.64 ±0.25 0.2 8 MAX. M C 24 3 2 ) 8.65 ±0. A Index Marking ) Does no include plasic or meal prorusion of 0.5 max. per side 2) Does no include dambar prorusion of 0.3 max. 3) JEDEC regisraion MO-37 variaion AE GPS024 Figure 22 PG-SSOP-24-7 (Plasic/Plasic Green - Dual Small Ouline Package) Green Produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions he device is available as a green produc. Green producs are RoHS-Complian (i.e Pb-free finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). You can find all of our packages, sors of packing and ohers in our Infineon Inerne Page Producs : hp://www.infineon.com/producs. Dimensions in mm Daa Shee 30 Rev.., 2009-07-07
Revision Hisory 7 Revision Hisory 0.40.3 TE 8444S Revision Hisory: Rev.., 2009-07-07 Version Subjecs (major changes since las revision). Package Illusraion on overview shee correced from exposed pad o sandard SSOP package.0 Final Daa Shee Release Daa Shee 3 Rev.., 2009-07-07
Ediion 2009-07-07 Published by Infineon Technologies AG 8726 Munich, Germany 2009 Infineon Technologies AG All Righs Reserved. egal Disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office (www.infineon.com). Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac he neares Infineon Technologies Office. Infineon Technologies componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. ife suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.