FB Elektrotechnik und Informationstechnik AG Entwurf mikroelektronischer Systeme Prof. Dr.-Ing. N. Wehn Vertieferlabor Mikroelektronik Modelling the DLX RISC Architecture in VHDL Versuch 7: Implementing Viterbi Algorithm in DLX Assembler Introduction Within this lab test, the following goals shall be achieved: Understand channel decoding using the Viterbi Algorithm (VA) Complete VA assembler source code Test and verify source code using ModelSim Synthesize DLX VHDL model Channel Coding and Decoding Figure 1: Information Transmission System Figure 1 shows a typical information transmission system. The output of the information source can be both analog or digital and is transformed into information bits by the source encoder. The purpose of the channel encoder is to group the information bits and to add parity bits. The encoded information bits are mapped to waveforms by the digital modulator and transmitted by the communication channel. During the transmission, the waveforms
2 may be altered or corrupted by noise or distortion. The digital demodulator estimates which symbol was sent with the greatest likelihood. The channel decoder uses its knowledge about the most likely sequence of the source information to correct faulty bits. One of the possible channel decoding techniques is the Viterbi Algorithm (VA) that is described indepth in the Appendix. As last step on the receiver side, the source decoder reverses the decoded information bits into the analog or digital signal that equals to the source signal with the greatest likelihood and hands the signal to the information sink. Convolutional codes are used to encode digital data before transmission through noisy or error-prone channels. They operate on serial data and are a major technique of forward error correction (FER) of wireless transmission standards. By adding thoroughly designed redundant bits to the payload data, the capacity of a channel can be exploited close to the Shannon Limit. This technique is particularly suited for communication channels that are disturbed by additive white gaussian noise (AWGN). The Viterbi algorithm (VA) was developed by Andrew J. Viterbi and published first in 1967. Its purpose is to estimate the most likely sequence of symbols that were potentially corrupted during transmission. The main advantages of this algorithm compared to other decoding techniques, e.g. sequential decoding, are consumption of fixed decoding time and maximum likelihood decoding. During the 1970s, it became part of the coding standard in deepspace data transmission. Later on, it was used in modems and for high-density magnetic recording. Today, the VA is used in more than 1 billion cell phones as it is the decoding algorithm utilized in CDMA and TDMA systems. However, the most important application measured in transferred bits is Digital Video Broadcasting (DVB) with approximately 1015 decoded bits per second worldwide. Furthermore, the VA is used in the 802.11 standards for Wireless LANs. Future applications also include speech recognition, keyword spotting and computational linguistics. Performing the Viterbi Algorithm As a preparation for the lab test, encode the following message using the 4-state-non-recursive, non-systematic convolutional encoder that is explained in the Appendix. The message consists out of 10 bits: dk 1 0 1 1 0 1 0 0 0 0 Please write the output of the encoder into the blank row named xk in the diagram on the next page. These are the encoded output symbols that would be transmitted over the channel. Due to noise, the fourth and sixth symbol were corrupted. All other symbols were received as they were encoded. Please fill the blank boxes named yk, accordingly. Now, the Viterbi Algorithm can be performed as explained in the Appendix. Please fill all empty boxes within the trellis according to the following scheme: The numbers to the right of the dot are the path metrics. They consist out of the lower path metric (first number) and the upper path metric (second number). The number below the dot is the decision bit. In case the lower path metric survives, it's value is 0, in case the upper path metric survives it's value is 1.
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4 Completing the Source Code The Viterbi Algorithm needs to be implemented using the DLX assembler programming language. After you performed the Viterbi Algorithm in the previous example, you should be able to program the computation of the branch and path metric using the instructions depicted in the Appendix. Start with the computation of the branch metric (BM) using the Hamming Distance (HD). As first step, the BM for the state transitions TO state S(3) shall be calculated. The already written parts of the source code hands over the received symbol in register R1. The value of the lower path metric shall be stored in register R12, the value of the upper path metric shall be stored in R13. After the branch metrics have been calculated, the corresponding path metrics can be computed. The path metric of the previous step of state S(2) has been stored in R4, the path metric of S(3) has been stored in R5. Subsequently, the survivor state needs to be determined; therefore, the lower path metric (LPM) needs to be compared with the upper path metric (UPM). In case the UPM is greater or equal to the LPM, the decision bit stored in R10 must be 1, otherwise it must equal 0. As temporary register for all set-on-comparisons, register R11 shall be used. As soon as the survivor state was identified, the new path metric for state S (3) must be stored in R9. Table 1 depicts the register allocation for the path metric calculation routine. Table 1: Register Allocation Please write the source code for the path metric calculation prior to the lab test. Within the lab test, you are going to insert your module into the existing source code.
5 Testing the Source Code After logging on into the terminal browse to the directory Lab_Test_7\DLX_VHDL\asm and open the file VA.S using nedit. Enter your source code between the specified labels in lines 72 to 85. After completing the source code, the binaries for the simulation need to be generated. The assembler is started from the terminal with the command: python asm.py [VA.s]. Subsequently, the source code can be tested. For this purpose, the software ModelSim is used. After starting ModelSim with the command vsim &, compile all required.vhd-files. After the compilation, the simulation can be started. Browse the library window and double click on dlx_tb. Add the required signals to the simulation signal list. As simulation time, choose 1800µs. If your source code performed the Viterbi Algorithm correctly, the values stored in the memory (signal /dlx_tb/mem/ram) at addresses 512 529 need to be identical as shown in the screenshot below: Please measure the effective execution time between fetching the first instruction and writing back the result of the last instruction. As the cycle time within the simulation is set to 50ns, you can compute the number of cycles needed to execute the Viterbi Algorithm for the 320 bit exemplary message. DLX w/o extensions Number of Cycles Instructions per decoded bit
6 Synthesizing the VHDL Model Following to the successful simulation, the DLX VHDL model can be synthesized to measure the hardware cost within an actual implementation on an FPGA. To start the synthesizing, the program ISE is utilized. Start it from the console with the command ise & and open the existing project file dlx_synth.ise from the directory DLX_VHDL\Synth\dlx_synth As first step, the synthesis needs to be performed. This process is initiated within the navigation menu on the left side as depicted in the screenshot. After the synthesis, the place and route can be performed. Following to the successful place&route, a report shows the number of used slices, the number of slice flip flops and 4input LUT's. Please note these numbers in the table below: DLX w/o extensions Number of Slices Number of Slice Flip Flops Number of 4 Input LUTs Thereof Logic Cycle Time [ns] Frequency [MHz]