Know your Algorithm! Architectural Trade-offs in the Implementation of a Viterbi Decoder. Matthias Kamuf,

Transcription

1 Know your Algorithm! Architectural Trade-offs in the Implementation of a Viterbi Decoder Matthias Kamuf,

2 Agenda Quick primer on communication and coding The Viterbi algorithm Observations to improve decoder architectures Trellis symmetries Hybrid approaches for survivor path processing Incorporate task flexibility Wrap-up Matthias Kamuf, DSP-Design,

3 Primer Shannon (1949): Reliable communication possible at certain SNR for R<C Here: R data bits per two-dimensional (I/Q) channel use Shannon limit on the BER for different R Limit at -1.6 db Matthias Kamuf, DSP-Design,

4 Channel coding: Popular overview Channel BXaXo LiXa AlpXa Xravo BXaXXa Transmitter Blablabla Bravo Lima Alpha Bravo Information disturbed during transmission Introduce redundancy coding theory Ex.: Standard phonetic alphabet Receiver guesses message (algorithms) Matthias Kamuf, DSP-Design,

5 Basic communication system High data rates dedicated HW How to approach reliable communication (or capacity)? Shannon said: Nothing beats random coding. An engineer says: But how should this be decoded? Pragmatic solution: Use block and convolutional codes! (nowadays even concatenated codes, e.g. turbo codes) Matthias Kamuf, DSP-Design,

6 Convolutional code representation Encoder realization with tap set (7,5) Redundancy (2 for 1) or code rate 1/2 Finite state machine of the encoder Matthias Kamuf, DSP-Design,

7 Convolutional code representation, ctd Matthias Kamuf, DSP-Design,

8 Decoding Maximum-likelihood decoding is optimal, i.e. Find the bit sequence c i which has the minimum Euclidean distance to the received sequence y. Example: Consider a B=100 bit block There are 2^100 bit possible sequences (or 1.27e30 sequences) How long does this take to decode? Matthias Kamuf, DSP-Design,

9 Intuitive and ingenious: The Viterbi Algorithm Cost function for a branch Discard suboptimal branches Establish cheapest path Several paths Take cheapest Add Compare Select Matthias Kamuf, DSP-Design,

10 Complexity considerations ACS is the heart of the algorithm For every state X at time instance k+1, one carries out For a radix-2 trellis: Arithmetic: 3N additions and N+1 selections per trellis stage are required Storage: N state metrics, N*B bits for trace-back What if B becomes large? Matthias Kamuf, DSP-Design,

11 Establish the cheapest path successively Pre-mature trace-back after stages d f = free distance of the code R c = code rate c = # of coded bits along a branch Rule of thumb: R c =1/2 requires 4-5 times constraint length of the code Matthias Kamuf, DSP-Design,

12 Branch transition probabilities Assume binary signaling per dimension, i.e. 1, 1 Euclidean distance for a branch (or transition) connecting states u, v c i Subtract the same amount from all λ (can be variable from stage to stage) Divide all λ by the same factor (needs to be constant) Matthias Kamuf, DSP-Design,

13 Trellis unit, upper butterfly Matthias Kamuf, DSP-Design,

14 Trellis unit, lower butterfly Matthias Kamuf, DSP-Design,

15 Strength reduction by symmetries Consider butterfly of rate 1/c convolutional code Complementary code symbols yield complementary cost measures One can be expressed by the other, i.e. A f A Matthias Kamuf, DSP-Design,

16 Trellis unit, revisited Matthias Kamuf, DSP-Design,

17 Simplified setup (update after decision) Offset to retain numerical relation Modified cost measures No update i.e. offset = 0 Matthias Kamuf, DSP-Design,

18 Retimed setup Reduce the critical path by a delayed update, i.e. move Δλ into next clock cycle Matthias Kamuf, DSP-Design,

19 Savings One adder saved in every other ACS unit Number of additions is halved in BM unit Total arithmetic savings ~17% But: Remember that this does not directly translate to absolute area savings (don t forget that there is other logic present, too) Matthias Kamuf, DSP-Design,

20 Finding the cheapest path Register-exchange (RE) Forward processing, limited to a small number of states Trace-back algorithm (TB) Forward and backward processing, scales well with any number of states Hybrid approaches TB and trace-forward (TF) RE and TB, specialized memory (accessible by row and column) Matthias Kamuf, DSP-Design,

21 Register-exchange Map the trellis portion directly onto HW. Easy to implement, no control necessary, low latency. But: Lots of rippling involved, N*L bits to be accessed per cycle Power consumption!!! Matthias Kamuf, DSP-Design,

22 Trace-back Here: Two read regions, one write region Tasks switch circularly among the partitions Latency 3L+L (stream needs to be reversed in time) TB start every Lth step only need to read N(L+L)/L bits per decoded bit Matthias Kamuf, DSP-Design,

23 A trace-forward unit (TFU) Idea: Do the starting state estimation in parallel to reduce latency (by L in the previous example) After L steps, all register hold the surviving state (if the paths have merged) Decision bits from trellis unit Stores the surviving predecessor state Load every register with corresponding state label Matthias Kamuf, DSP-Design,

24 How else can TFU s be used Use more than one TFU to estimate starting states over smaller intervals κ. Reduces latency even further if used with RE Matthias Kamuf, DSP-Design,

25 Hybrid survivor path architecture Memory requirement Hybrid approach: RE (length < L) and TFs (include the last m bits) No specialized FIFO (only conventional RAM) Trade complexity for latency/storage by varying l Easy to control Still allows high-speed applications Matthias Kamuf, DSP-Design,

26 Flexibility comes into play Mission: Evaluate the cost of flexibility in channel decoding Key question: How much area/speed/power is to be sacrificied for a certain flexibility? Here: Flexibility by providing different transmission rates viz. number of data bits per channel use. Explore other coding schemes that achieve better performance. This implies different radices. Example: Convolutional codes and TCM (Trellis Coded Modulation) Matthias Kamuf, DSP-Design,

27 What s TCM? Ex.: Standard 16-QAM Matthias Kamuf, DSP-Design,

28 What s TCM?, ctd. Divide constellation into subsets to increase the distance between symbols Subset number Uncoded bit Matthias Kamuf, DSP-Design,

29 How to achieve this? Convolutional encoder with rate b/c Matthias Kamuf, DSP-Design,

30 BER performance Adapt to varying channel conditions bad channel: Gray-mapped QPSK, rate 1/2 convolutional code gradually improving channel: 16-QAM, 64-QAM TCM, rate 2/3 subset selector Comparisons with punctured convolutional codes bad channel good channel Matthias Kamuf, DSP-Design,

31 Flexible architecture overview Matthias Kamuf, DSP-Design,

32 Subset decoding This part is exclusively to TCM (task-flexibility) Consider 16-QAM again 8 subsets, 2 symbols per subset Shaded part is the region, where With quantization this turns out be a sign check Higher constellations need more comparisons! This is adds quite some complexity! Matthias Kamuf, DSP-Design,

33 Mapping possibilties for the trellis unit Time-multiplexed F<N Direct-mapped F=N Direct-mapped F=N Higher radix What application areas do you foresee for these mappings? Matthias Kamuf, DSP-Design,

34 Higher radices, e.g. radix-4 Ideal speedup by 2. Is this realistic? Per state: 6 comparisons in parallel together with selection logic Matthias Kamuf, DSP-Design,

35 Fixed trellis unit Radix-2 Radix-2 butterfly: 2 ACS units Matthias Kamuf, DSP-Design,

36 Flexible trellis unit Radix-2/4 Radix-2 and radix-4 butterflies: 2 ACS units + routing (grey) Matthias Kamuf, DSP-Design,

37 SP unit based on register-exchange Number of states is only 8 Length of subset memory ~ L Process 3 bits per state and stage (subset number must be decoded) Grey parts disabled in radix-2 mode Matthias Kamuf, DSP-Design,

38 Folded architecture Match computation rate to the trellis unit (remember that it takes 3 cycles to process a trellis stage) 66% of MUXes and interconnects vanish Matthias Kamuf, DSP-Design,

39 Silicon implementation High-speed standard cell library for UMC 0.13 um CMOS Chip area (including pads): 1.44 mm 2 QPSK Gray 16-QAM TCM 64-QAM TCM QPSK Gray Matthias Kamuf, DSP-Design,

40 Measurements at f=160 MHz Chip verified functionally Adding more rates adds incremental cost once rate-flexibility accepted Note: Around 20% higher power than estimated for rate 5 Matthias Kamuf, DSP-Design,

41 Conclusion Get to know your algorithm (and system properties beyond) to make right trade-offs Note: If you got a standard to implement it s hard to explore different coding schemes Questions and comments? Matthias Kamuf, DSP-Design,