March 2013 FSUSB46 Hi-Speed USB2.0 (480Mbps) DPST Switch with Dedicated harger Port Detection Features Low On apacitance: 7.0pF Typical Low On Resistance: 3.9Ω Typical Low Power onsumption: 1μA Maximum - 15μA Maximum I T over an Expanded Voltage Range (V IN =1.8V, V =4.3V) Wide -3db Bandwidth: > 720MHz Packaged in Pb-free, 8-Lead MicroPak (1.6mm wide), US8 (3.1mm wide), and UMLP (1.4x1.4mm) 8kV ESD Rating, >16kV Power/ ESD Rating Power-Off Protection on All Ports When V =0V - D+/D- Pins Tolerate up to 5.25V Applications ell phone, PDA, Digital amera, and Notebook LD Monitor, TV, and Set-Top Box IMPORTANT NOTE: For additional performance information, please contact analogswitch@fairchildsemi.com. Description The FSUSB46 is a bi-directional, low-power, Hi-Speed, USB2.0 switch. onfigured as a double-pole, singlethrow switch (DPST) switch, it is optimized for switching a Hi-Speed (480Mbps) source. The FSUSB46 is compatible with the requirements of USB2.0 and features an extremely low on capacitance ( ON ) of 3.9pF. The wide bandwidth of this device (720MHz) exceeds the bandwidth needed to pass the third harmonic, resulting in signals with minimum edge and phase distortion. Superior channel-to-channel crosstalk also minimizes interference. The FSUSB46 contains special circuitry on the switch I/O pins for applications where the V supply is powered-off (V =0), which allows the device to withstand an over-voltage condition. This device is designed to minimize current consumption even when the control voltage applied to the pin is lower than the supply voltage (V ). This feature is especially valuable to ultra-portable applications, such as cell phones, allowing for direct interface with the generalpurpose I/Os of the baseband processor. An additional feature is the detection of the 1-1 (high/high) state on D+/D- to signal an interrupt (INT) to the processor when entering a dedicated charging port mode of operation. Ordering Information Part Number Operating Temperature Range Package Eco Status FSUSB46L8X -40 to +85 8-Lead MicroPak 1.6mm Wide RoHS FSUSB46K8X -40 to +85 8-Lead US8, JEDE MO187, Variation A 3.1mm Green FSUSB46UMX -40 to +85 8-Lead Ultrathin Molded Leadless Package (UMLP), 1.2 x 1.4mm Green For Fairchild s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. MicroPak is a trademark of Fairchild Semiconductor orporation. INT HSD+ D+ HSD- D- Figure 1. Analog Symbol FSUSB46 Rev. 1.0.4
HSD+ D+ INT HSD D FSUSB46 Hi-Speed USB2.0 (480Mbps) DPST Switch with Dedicated harger Port Detection Pin onfigurations Vcc 1 8 7 INT 8 7 6 HSD+ 2 6 HSD- INT 1 8 Vcc V 1 5 D+ 3 4 5 D- HSD- D- 2 3 7 6 HSD+ 2 3 4 4 5 D+ Figure 2. MicroPak (Top Through View) Figure 3. US8 (Top Through View) Figure 4. UMLP (Top Through View) Pin Definitions Pin Name INT D+, D- HSD+, HSD- V Description Interrupt Signaling Output Pin Switch Enable USB Data Bus onnector USB Source Inputs Ground Supply Voltage Truth Table Data Path harger Detect Path Switch onnection D+ D- INT Output HIGH D+, D- = Open 1-1 LOW LOW D+, D- = HSD+, HSD- 0X, X0 HIGH FSUSB46 Rev. 1.0.4 2
Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V Supply Voltage -0.5 +5.5 V V NTRL D Input Voltage (S) (1) -0.5 V V V SW D Switch I/O Voltage (1) -0.50 5.25 V I IK D Input Diode urrent -50 ma I OUT D Output urrent 50 ma T STG Storage Temperature -65 +150 ESD Human Body Model, JEDE: JESD22-A114 All Pins 7 I/O to 8 Power to 16 harged Device Model, JEDE: JESD22-101 2 Note: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. kv Recommended Operating onditions The Recommended Operating onditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V Supply Voltage 3.0 4.3 V V NTRL ontrol Input Voltage () (2) 0 V V V SW Switch I/O Voltage -0.5 V V T A Operating Temperature -40 +85 Note: 2. The control input must be held HIGH or LOW; it must not float. FSUSB46 Rev. 1.0.4 3
D Electrical haracteristics All typical value are at 25, V =3.3V unless otherwise specified. Symbol Parameter onditions V (V) T A =- 40º to +85º Min. Typ. Max. V IK lamp Diode Voltage I IN =-18mA 3.0-1.2 V V IH V IL Input Voltage High Input Voltage Low V OH Output Voltage High I OH =-2mA V OL Output Voltage Low I OL =2mA Units 3.0 to 3.6 1.3 V 4.3 1.7 V 3.0 to 3.6 0.5 V 4.3 0.7 V 3.0 to 3.6 2.4 4.3 2.4 3.0 to 3.6 0.25 4.3 0.25 I IN ontrol Input Leakage V SW =0 to V 4.3-1 1 µa I OZ I OFF Off State Leakage Power-Off Leakage urrent (All I/O Ports) HSD+ or HSD-=0V, 3.6V or floating V SW =0V to 4.3V, V =0V Figure 6 R ON HS Switch On Resistance (3) V SW=0.4V, I ON =-8mA Figure 5 4.3-2 2 µa 0-2 2 µa 3.0 3.9 6.5 V V R ON HS Delta R ON (4) V SW =0.4V, I ON =-8mA 3.0 0.65 I Quiescent Supply urrent V NTRL =0 or V, I OUT =0 4.3 1 µa I T Increase in I urrent Per ontrol Voltage and V V NTRL =2.6V V =4.3V 4.3 10 µa V NTRL =1.8V V =4.3V 4.3 20 µa Notes: 3. Measured by the voltage drop between HSDn and Dn pins at the indicated current through the switch. On resistance is determined by the lower of the voltage on the two (HSDn or Dn ports). 4. Guaranteed by characterization. FSUSB46 Rev. 1.0.4 4
A Electrical haracteristics All typical value are for V =3.3V at 25 unless otherwise specified. Symbol Parameter onditions V (V) t ON t OFF Turn-On Time to Output Turn-Off Time to Output R L =50Ω, L =5pF V SW =0.8V Figure 7, Figure 8 R L =50Ω, L =5pF V SW= 0.8V Figure 7, Figure 8 t PD Propagation Delay (5) L=5 pf, R L =50Ω Figure 7, Figure 9 R L =50Ω, L =5pF Break-Before-Make V SW1 =V SW2 =0.8V Figure 13 t BBM T A =- 40º to +85º Min. Typ. Max. Units 3.0 to 3.6 13 30 ns 3.0 to 3.6 12 25 ns 3.3 0.25 ns 3.0 to 3.6 2.0 6.5 ns t PLH/HL INT Propagation Delay (5) R L =500Ω, L =5pF 3.0 to 3.6 10 ns O IRR Xtalk BW Off Isolation Non-Adjacent hannel rosstalk -3db Bandwidth Note: 5. Guaranteed by characterization. R L =50Ω, f=240mhz Figure 15 R L =50Ω, f=240mhz Figure 16 R L =50Ω, L =0pF Figure 14 R L =50Ω, L =5pF Figure 14 3.0 to 3.6-30 db 3.0 to 3.6-45 db 720 MHz 3.0 to 3.6 550 MHz USB Hi-Speed-Related A Electrical haracteristics Symbol Parameter onditions V (V) t SK(P) Skew of Opposite Transitions of the Same L =5pF, R L =50Ω Output (6) Figure 10 t J Total Jitter (6) t R =t F =500ps (10-90%) at R L =50Ω, L =5pf, 480Mbps (PRBS=2 15 1) Note: 6. Guaranteed by characterization. T A =- 40º to +85º Min. Typ. Max. Units 3.0 to 3.6 20 ps 3.0 to 3.6 200 ps apacitance Symbol Parameter onditions T A =- 40º to +85º Min. Typ. Max. Units IN ontrol Pin Input apacitance V =0V 1.5 pf OUT INT Pin Output apacitance V =0V 2.5 pf ON D+, D- On apacitance V =3.3V, f=1mhz Figure 12 7.0 7.9 pf OFF D+, D- Off apacitance V =3.3V Figure 11 2.0 pf FSUSB46 Rev. 1.0.4 5
Test Diagrams V ON HSDn H SD n Dn A D+, D- V S W VSW V S W R = V O O / I O N N N Figure 5. On Resistance HSD n R S Dn L V O E = 0 o Vcc R L I ON V OUT V I n p u t V 0 or V Figure 6. Off/On Leakage t R ISE= 2.5 ns t F A L L = 2. 5 n s / O E 10 % 90 % 90 % V / 2 V / 2 10 % V Sel V O H 90 % 90 % O u t p u t - V O U T R L, R S, and L are functions of the application environment (see A Tables for specific values) L includes test fixture and stray capacitance. V O L t O N t O F F Figure 7. A Test ircuit Load Figure 8. Turn-On / Turn-Off Waveforms t RISE= 500ps t FALL = 500ps +400mV -400mV 10% 0V 90% 90% 10% Output t PHL t PLH Figure 9. Propagation Delay (t R t F 500ps) Figure 10. Intra-Pair Skew Test t SK(P) a p a c i t a n c e M e t e r H S D n 0 or V cc a p a c i t a n c e M e t e r H S D n V /O E = 0 o r V c c H S D n H S D n Figure 11. hannel Off apacitance Figure 12. hannel On apacitance FSUSB46 Rev. 1.0.4 6
Test Diagrams (ontinued) t RISE = 2.5ns HSDn V SW1 R S V Dn Input - V L 10% 0V R L V OUT 0.9* V OUT 90% V /2 t BBM 0.9* V OUT V R L, R S, and L are functions of the application environment (see A Table for specific values). L includes text ficture and stray capacitance. Figure 13. Break-Before-Make Interval Timing Network Analyzer R S V IN V S V R T V OUT R S, and R T are functions of the application environment (see A Table for specific values). Figure 14. Bandwidth Network Analyzer R S V IN V S V R S, and R T are functions of the application environment (see A Table for specific values). Figure 15. hannel Off Isolation R T V OUT Off Isolation = 20 Log (V OUT / V IN ) N Network Analyzer R S V V R T V IN R T V S R S, and R T are functions of the application environment (see A Table for specific values). rosstalk = 20 Log (V OUT / V IN ) FSUSB46 Rev. 1.0.4 7 R T V OUT Figure 16. Non-Adjacent hannel-to-hannel rosstalk
Physical Dimensions 2X 0.10 B 1.6 A 1.6 INDEX AREA 2X 0.10 TOP VIEW 0.55 MAX 0.05 Recommended Landpattern 0.05 0.00 DETAIL A 8X (0.09) 1.0 1 2 3 0.5 0.05 (0.20) 0.35 0.25 4 (0.1) 0.35 8X 0.25 3X (0.2) 8 7 6 5 4 BOTTOM VIEW 0.15 0.25 8X 0.10 A B 0.05 (0.15) 0.35 0.25 DETAIL A PIN #1 TERMINAL SALE: 2X Notes: 1. PAKAGE ONFORMS TO JEDE MO-255 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING ONFORMS TO ASME Y.14M-1994 4. PIN 1 FLAG, END OF PAKAGE OFFSET 5. DRAWING FILE NAME: MKT-MA08AREV4 MA08AREV4 Figure 17. 8-Lead MicroPak Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. FSUSB46 Rev. 1.0.4 8
Tape and Reel Specifications Package Designator L6X, L8X, L10X Tape Section avity Number avity Status over Tape Status Leader (Start End) 125 (Typical) Empty Sealed arrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed Standard Tape and Reel Specifications Standard tape and reel specifications for MicroPak are available at Fairchild Semiconductor s website: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf FSUSB46L8X_F130 Tape and Reel Specifications 10 30056 2.30 ± 0.1mm 1.78 ± 0.1mm 0.68 ± 0.1mm 8 30038 1.78 ± 0.1mm 1.78 ± 0.1mm 0.68 ± 0.1mm 6 30033 1.60 ± 0.1mm 1.15 ± 0.1mm 0.70 ± 0.1mm FSUSB46 Rev. 1.0.4 9
2.70 3.40 -A- FSUSB46 Hi-Speed USB2.0 (480Mbps) DPST Switch with Dedicated harger Port Detection Physical Dimensions 1.80 0.15 8 5 -B- 0.70 3.1±.1 PIN #1 IDENT. 1.55 1 4 2.3±0.1 0.2 B A ALL LEAD TIPS 1.00 0.5 TYP 0.30 TYP 0.90 MAX ALL LEAD TIPS 0.1 0.70±0.10 DETAIL A 0.10-0.18 -- 0.50TYP 0.10 0.00 0.17-0.27 0.13 A B 0.4 TYP GAGE PLANE 0-8 0.12 A. ONFORMS TO JEDE REGISTRATION MO-187 B. DIMENSIONS ARE IN MILLIMETERS.. DIMENSIONS ARE EXLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D. DIMENSIONS AND TOLERANES PER ANSI Y14.5M, 1982. DETAIL A SEATING PLANE MAB08AREV Figure 18. 8-Lead US8, JEDE MO-187 For current tape and reel specifications, visit Fairchild Semiconductor s online packaging area: http://www.fairchildsemi.com/ms/ms/ms-522.pdf Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. FSUSB46 Rev. 1.0.4 10
Physical Dimensions 2X 0.10 B 1.4 A 0.725 1.450 0.400 2X 1.20 0.10 0.450 1.250 0.625 0.350 7X 0.250 8X TOP VIEW 0.55 MAX 0.05 0.05 0.025 0.00 SEATING PLANE DETAIL A 0.40 1 2 4 5 0.35 0.25 7X 0.30 0.10 45 PIN#1 IDENT 8 6 (0.2) 0.15 8X 0.25 0.10 A B 0.05 0.20 0.10 BOTTOM VIEW DETAIL: A SALE : 2x NOTES: A. DOES NOT ONFORMS TO JEDE STANDARD. B. DIMENSIONS ARE IN MILLIMETERS.. DIMENSIONS AND TOLERANES ONFORMS TO ASME Y14.5M, 1994. D. DRAWING FILE NAME : UMLP08Arev1 Figure 19. 8-Lead, Ultrathin Molded Leadless Package (UMLP), 1.2 x 1.4mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. FSUSB46 Rev. 1.0.4 11
FSUSB46 Rev. 1.0.4 12 FSUSB46 Hi-Speed USB2.0 (480Mbps) DPST Switch with Dedicated harger Port Detection