Design for Testability & Design for Debug

EE-382M VLSI II Design for Testability & Design for Debug Bob Molyneaux Mark McDermott Anil Sabbavarapu EE 382M Class Notes Foil # 1 The University of Texas at Austin

Agenda Why test? Scan: What is it? What is it good for? Snapshot! : Debug Scanout Embedded Memory Testing JTAG Summary EE 382M Class Notes Foil # 2 The University of Texas at Austin

Why Test? EE 382M Class Notes Foil # 3 The University of Texas at Austin

The Manufacturing Process is Imperfect EE 382M Class Notes Foil # 4 The University of Texas at Austin

The Manufacturing Process is Imperfect EE 382M Class Notes Foil # 5 The University of Texas at Austin

The Manufacturing Process is Imperfect EE 382M Class Notes Foil # 6 The University of Texas at Austin

The Manufacturing Process is Imperfect EE 382M Class Notes Foil # 7 The University of Texas at Austin

Test Techniques Functional: Make it do what it does. Structural: Divide and conquer EE 382M Class Notes Foil # 8 The University of Texas at Austin

Functional Test Does my chip execute all architectural instruction sequences? In the presence of all possible data streams? EE 382M Class Notes Foil # 9 The University of Texas at Austin

Structural Test Does SPC1 do its job? Does MCU do its job? Still checking functionality but divide and conquer activity is taking place. EE 382M Class Notes Foil # 10 The University of Texas at Austin

Structural Test Do the NOR gates do their job? F1 Does the AND gate do its job? F2 A B C D E F G H F5 F3 F6 Still checking functionality but divide and conquer activity is taking place. F4 EE 382M Class Notes Foil # 11 The University of Texas at Austin

Structural Test Thesis If we can prove every gate in the part functions then we can conclude that the part works. Corollary Structural Scan But it makes most sense. EE 382M Class Notes Foil # 12 The University of Texas at Austin

Basics of Scan EE 382M Class Notes Foil # 13 The University of Texas at Austin

Fault Models Stuck-At Faults Bridging/break Faults Transistor Stuck-On/Open Faults Functional Faults Memory Faults Delay Faults Transition Faults State Transition Faults VLSI Testing Fault model.7 NCKUEE-KJLEE

Single Stuck-At Faults Test Vector 0 1 Faulty Response Fault-free Response 0 1/ 0 1 1 1/0 stuck-at-0 Assumptions: Only one line is faulty. (Why?) Faulty line permanently set to 0 or 1. Fault can be at an input or output of a gate. VLSI Testing Fault model.8 NCKUEE-KJLEE

Single Stuck-at Faults # single stuck-at fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches) Example: A 4-NAND XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults a b c d e f g 1 h i j k 1 z How many faults? VLSI Testing Fault model.9 NCKUEE-KJLEE

Multiple Stuck-At Faults Several stuck-at faults occur at the same time - Important in high density circuits For a circuit with k lines - There are 2k single stuck-at faults - There are 3 k -1 multiple stuck-at faults ATPG algorithms for multiple s-a-faults are much more complex and not as well developed VLSI Testing Fault model.10 NCKUEE-KJLEE

Why Single Stuck-At Faults? Complexity is greatly reduced. Many different physical defects may be modeled by the same logical single stuck-at fault. Single stuck-at fault is technology independent. Can be applied to TTL, ECL, CMOS, etc. Single stuck-at fault is design-style independent. Gate Arrays, Standard Cell, Custom VLSI Even when single stuck-at fault does not accurately model some physical defects, the tests derived for these faults may still be effective for these defects. Single stuck-at tests cover a large percentage of multiple stuck-at faults. VLSI Testing Fault model.11 NCKUEE-KJLEE

Bridging Faults Two or more normally distinct points (lines) are shorted together - Logic effect depends on technology - Wired-AND for TTL A f A f B g B g - Wired-OR for ECL A f A f B g B g - CMOS? VLSI Testing Fault model.12 NCKUEE-KJLEE

Feedback Bridging Faults Input C Output Can cause oscillation or latching (additional memory) Consequences: - The shorted signal lines form wired logic so the original logic function is changed - The circuit may become unstable if unwanted feedbacks exist Applying opposite values to the signal lines being tested to test these faults VLSI Testing Fault model.13 NCKUEE-KJLEE

CMOS Transistor Stuck-On 0 IDDQ? stuck-on Transistor stuck-on may cause ambiguous logic level. depends on the relative impedances of the pull-up & pull-down networks When input is low, both P and N transistors are conducting causing increased quiescent current, called IDDQ fault. VLSI Testing Fault model.14 NCKUEE-KJLEE

CMOS Transistor Stuck-OPEN Transistor stuck-open may cause output floating Can turn the circuit into a sequential one (temporarily keep the previous value) Stuck-open faults require two-vector tests: initialiation and test vectors 0 stuck-open? = previous state initialization vector 10 01 / 00 test vector stuck-open memory behavior VLSI Testing Fault model.15 NCKUEE-KJLEE

(Line) Break Faults Can be on the line between two gates or within one gate. Usually resulting in floating. May require two or more patterns to detect a break fault. IDDQ X X X X VLSI Testing Fault model.16 NCKUEE-KJLEE

Functional Faults Fault effects modeled at a higher level than logic for function modules, such as -- Decoders -- Multiplexers -- Adders -- RAM -- ROM -- CPU (instruction set) -- Cache memory VLSI Testing Fault model.17 NCKUEE-KJLEE

Functional Faults of Decoder f(l i /L j ): Instead of line L i, Line L j is selected f(l i /L i +L j ): In addition to L i, L j is selected f(l i /L j +L k ): Instead of L i, L j and L k are selected f(l i /0): None of the lines are selected A B 2-bit Decoder AB AB AB AB VLSI Testing Fault model.18 NCKUEE-KJLEE

Memory Faults Parametric Faults - Output Levels - Power Consumption - Noise Margin - Data Retention Time Functional Faults - Stuck-at Faults in Address Register, Data Register, and Address Decoder - Cell Stuck Faults - Adjacent Cell Coupling Faults - Pattern-Sensitive Faults VLSI Testing Fault model.19 NCKUEE-KJLEE

Memory Faults (Cont.) Pattern-sensitive faults: the presence of a faulty signal depends on the signal values of the nearby points - Most common in DRAMs 0 0 0 0 x b 0 a 0 a=b=0 x=0 a=b=1 x=1 Adjacent cell coupling faults - Pattern sensitivity between a pair of cells VLSI Testing Fault model.20 NCKUEE-KJLEE

Delay Fault Model Assumption - Some physical defects, such as process variations, make some delays in the CUT greater than some defined limits Two delay fault models are typically used - Gate delay fault model (a local delay fault model) - Path delay fault model (a global delay fault model) 5ns Regs. D CUT Regs. clk normal clk faulty VLSI Testing Fault model.21 NCKUEE-KJLEE

What is a test? Primary inputs (PI) Fault activation Combinational circuit X 1 0 1/0 0 1 0 1 X Stuck-at-0 fault Fault effect 1/0 Primary outputs (PO) Path sensitization 2

Primary inputs (PI) What is a test? Test Vector Fault activation Combinational circuit X 1 0 1/0 0 1 0 1 X Stuck-at-0 fault Fault effect 1/0 Primary outputs (PO) Path sensitization Test Response 3

Example! Generate a test for e stuck-at-1 Sa1 a b c e g d f 4

Example! 1) Activate the fault a 0 b c e g d f 5

Example! 1) Activate the fault a 0/1 b c e g d f 6

Example! 1) Activate the fault Fault Effect a 0/1 b c e g d f 7

Example! 1) Propagate the fault effect a b c 0/1 e 0/1 g d f 8

Example! 1) Propagate the fault effect a b c 0/1 e 0/1 g d f 9

Example! 1) Propagate the fault effect a b c 0/1 e 0/1 0/1 g d f 0 10

Example! 1) Propagate the fault effect a b c 0/1 e 0/1 0/1 g d f 0 11

Example! Justification a b c d f e 0 0/1 0/1 0 0/1 g 12

Example! Justification a b 1 c 1 d f 0/1 e 0 0/1 0 0/1 g 13

Example! Justification a b 0 1 c 1 d f 0/1 e 0 0/1 0 0/1 g 14

Some Considerations! Test is easy! But. 15

Some problems (the complexity) 2.2 Billion Transistors 16

Some problems (the circuit)! Generate a test for c stuck-at-1 Sa1 a b c e g d f 17

Some problems (the circuit)! c stuck-at-1 is an untestable fault a b 1 0 c 0/1 d 0 0/1 f e 1 0/1 1 1 g 18

Goals! You must use the appropriate tool! Automatic Test Pattern Generator (ATPG) 19

Theoretical Foundations: Boolean Difference q The function for the circuit is q Let the target fault be y/0, then the function for the faulty circuit is f = f(y=0) q Goal of test generation: find a vector that makes f XOR f = 1 16 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 16

Boolean Difference Continued q f XOR f = 1 iff f and f result in opposing logic values q Thus, any vector that can set f XOR f = 1 is able to produce opposing values at the outputs of the fault-free and faulty circuits respectively q Definition: 17 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 17

Boolean Difference Example q To excite the fault y/0, y=1 q Thus, xyz= 110 or 011 can detect the fault 18 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 18

Another Example q Let target fault be w/0 xyz=001, 101 can detect w/0 But: 19 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 19

A Third Example q Fault: z/0 This fault is untestable! 20 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 20

Wrap Up on Boolean Difference q Given a circuit with output f and fault q The set of vectors that can detect this fault includes all vectors that satisfy 21 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 21

Sequential ATPG q Huffman Model of a sequential circuit 57 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 57

Iterative Logic Array Expansion q To detect a fault, a sequence of vectors may be needed 58 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 58

Basics of Scan EE 382M Class Notes Foil # 13 The University of Texas at Austin

Sequential Circuits Testing Inputs outputs = f(inputs, state) Combinational Logic Registers State Outputs Clock In sequential circuits the initial state (register s values) is not by default known. Consequently, the sensitization of faults and the propagation of the corresponding erroneous responses may turn to be a hard task. A solution is to use techniques for the proper initialization of the circuit state to known values. Application of proper test vector sequences and/or the use of Set/Reset signals to setup the required state. Developmentofefficienttechniquesto set the initial state and observe the subsequent state after the response of the circuit. Scan Testing 3 General Scan Testing Scheme Scan In Registers Logic Inputs Outputs Scan Register Clock Scan Out The memory elements (latches or Flip Flops) in a design are properly connected to form aunifiedshiftregister(scan register or chain). This way the internal state of the circuit is determined (controlled) by shifting in (scan in)tothescanregistertherequiredtestdata to be applied to the combinational logic. Moreover, the existing internal state (previous logic response) can be observed by shifting out (scan out) thedatastoredintothescan register. Scan Testing 4 2

Scan Testing Design (Ι) Primary Inputs PI Combinational Logic PO Primary Outputs Pseudo Primary Outputs Full Scan Register Original Circuit PI PPI Scan In Combinational Logic PO PPO Pseudo Primary Inputs Scan Register Scan Out Scan Testing 5 Scan Testing Design (ΙI) Multiple Scan Chains Partial Scan PI Combinational Logic PO PI Combinational Logic PO Scan In_1 Scan Register Register Scan In_N... Scan Out_1 Scan In Scan Register Scan Register Scan Out_N Scan Out Scan Testing 6 3

Scan Path Design (I) Primary In nputs X 1 Z 1 X 2 X K Combinational Logic...... Z 2 Z N Primary Ou utputs SE SI 1 0 1 MUX Scan FF D Flip Flop 0 0 D Q D Q D Q 1 1 2 1 M CLK CLK CLK MUX... MUX Scan Chain 0 1 MUX SO CLK Scan Mode SE= 1 Scan Testing 7 Scan Path Design (II) Primary In nputs X 1 Z 1 X 2 X K Combinational Logic...... Z 2 Z N Primary Ou utputs SE SI 0 0 1 MUX 0 0 D Q D Q D Q 1 1 2 1 M CLK CLK CLK MUX... MUX Scan Chain 0 1 MUX SO CLK Normal Mode SE= 0 Scan Testing 8 4

Test Sequences During Scan Testing Prima ary Inputs SI Primary Outputs...... Test Vector...... clock cycles 1 st sequence 2 nd sequence 3 rd sequence 4 th sequence Ν th sequence (Ν+1) th sequence Test Response... SO clock cycles Scan Testing 9 Scan Application (Ι) 1 Scan cells testing 2 SE = 1 Scan in of alternating 3 Μ+1 clock cycles 0 and 1 from the SI input 4 Response observation at the SO output Μ = # of scan cells Scan Testing 10 5

Scan Application (ΙI) 5 Logic testing 6 SE = 1 : Test data scan in from the SI inputs Μ clock cycles (scan in cycles) 7 SE = 0 : Test pattern application from the PI inputs 8 Single clock pulse and response observation at the POs single clock cycle (capture cycle) Scan Testing 11 Scan Application (ΙII II) 9 SE = 1 : New test data scan in from the SIs and simultaneous scan out of the test responses from the SOs Μ clock cycles 10 Exists another test vector; YES 7 No 11 End Scan Testing 12 6

Basics of Scan F7 F8 S R A M F1 F2 A C F E B D G H F5 F9 F3 F6 F0 F4 EE 382M Class Notes Foil # 14 The University of Texas at Austin

SCAN IN Basics of Scan F7 F8 S R A M F1 F2 A C F E B D G H F5 F9 F3 F6 F0 F4 SCAN OUT EE 382M Class Notes Foil # 15 The University of Texas at Austin

Convert a Memory Element to a Scan Cell Memory element C C data in data out Scannable Register C C A B B data in Scan out Scan in A Master Register EE 382M Class Notes Foil # 16 Slave Register data out The University of Texas at Austin

Scan Design Components (1) scan cell (3) scan in and scan out (2) scan chain (4) scan clock scan chain scan chain PI (Scan in) PO (Scan out) PI (Scan in) PO (Scan out) scan cell scan in data in scan A clock scan cell System clock scan B clock EE 382M Class Notes Foil # 17 data out scan out The University of Texas at Austin

Why Scan design? Makes internal circuit access much more direct to allow for controllability and observability Converts a sequential test generation problem into a combinational test generation problem Enables automatic test pattern generation (ATPG) Enables use of low-pincount, low cost testers (ATE) EE 382M Class Notes Foil # 18 The University of Texas at Austin

Stuck-At Testing SCAN IN Test for C stuck-at 1 F7 F8 S R A M F1 F2 A C F E B D G H F5 F9 F3 F6 F0 F4 SCAN OUT EE 382M Class Notes Foil # 19 The University of Texas at Austin

SCAN IN Stuck-At Testing Test for C stuck-at 1 Load Scan Chain S R A M 0 1 A C F E B D G H 1 1 SCAN OUT EE 382M Class Notes Foil # 20 The University of Texas at Austin

SCAN IN Stuck-At Testing Test for C stuck-at 1 Pulse Clock Test Result S R A M?? A C F E B D G H 1?? SCAN OUT EE 382M Class Notes Foil # 21 The University of Texas at Austin

SCAN IN Stuck-At Testing Test for C stuck-at 1 Unload Scan Chain S R A M 0 1 A C F E B D G H 1 1 1 SCAN OUT EE 382M Class Notes Foil # 22 The University of Texas at Austin

Scan-based Structural Test Scan Inputs Primary I/O s (no connection) can chains logic logic logic logic sprimary I/O s (no connection) Control and clock inputs Tester Scan Outputs EE 382M Class Notes Foil # 23 The University of Texas at Austin