FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART I.1 Many of these slides were provided by Dr. Sebastian Hoyos January 2019 Texas A&M University 1 Spring, 2019
Outline Fundamentals of Analog-to-Digital Converters Introduction Sampling and Quantization Quantization noise and distortion INL and DNL Technological related issues Sample and Hold Switching issues S/H Accuracy Active S/H Switch around S/H Texas A&M University 2 Spring, 2019
R. Walden, 1999 Texas A&M University 3 Spring, 2019
What is an Analog-to-Digital Converter (ADC)? Analog Digital 0100101100101001010101010 1010100101001010010100101 0100100100100101100110010 10100100101001001010 Continuous with no apparent discontinuities The way we interpret our surroundings: sound, light, temperature etc ADC Discrete with limited range; based on binary numbers with limited number of bits. The way we mathematically represent and process our world using electronic brain power Texas A&M University 4 Spring, 2019
How does an ADC work? Analog Digital 0100101100101001010101010 100101001 1010100101001010010100101 010010100 0100100100100101100110010 100110010 10100100101001001010 11001010 Continuous with no apparent discontinuities The way we interpret our surroundings: sound, light, temperature etc ADC Discrete with limited range; based on binary numbers with limited number of bits. The way we mathematically represent and process our world using electronic brain power Texas A&M University 5 Spring, 2019
Analog How does an ADC work? x(t) ADC Digital t Quantization noise 100101001 010010100 100110010 11001010 x(n) δ(n) 2 N Levels separated by 1LSB, 1LSB = V FS* / 2 N nt S nt S * V FS = full scale range, V max -V min Texas A&M University 6 Spring, 2019
ADCs: Yesterday vs. Today Example: Digital photography (8-12b ADCs) Yesterday: 2000 Today: 2009 CCD/ CMOS Image Array AMP Balance Control ADC DSP (black level compensation, encoding...etc) CCD/ CMOS Image Array AMP ADC DSP (balance control, black level compensation, image stabilization, exposure levels, noise reduction, lens shading correction, encoding...etc) 0.5-0.8µm CMOS with 5V supply (moderate gate density and speed in DSPs) 2M pixel CCD sensor (low pixel scanning speed) Some pre-adc analog conditioning ~ 2.5mV / LSB 90nm-180nm CMOS with 1.2-1.8V supplies (high gate density and speed in DSPs) 12M pixel CCD sensor (high pixel scanning speed) Minimal pre-adc analog conditioning ~ 0.5mV / LSB Faster DSPs capable of performing numerous complex functions are developed thanks to advanced CMOS technologies. ADCs are indispensable, but now need to handle smaller signals at higher speeds with similar or higher resolutions. ADCs are becoming the bottleneck for advancement, and new design techniques need to be developed. Texas A&M University 7 Spring, 2019
Resolution (bits) ADCs: Tomorrow? ADC IEEE literature survey: 2006-2008 20 18 16 14 12 10 8 6 4 2 Sigma-Delta Pipelined Flash 0.01 0.1 1 10 100 1000 10000 Signal Bandwidth (MHz) Pipeline ADC is currently most published architecture Pipeline ADC is breaking the trend set by Sigma-Delta and Flash ADCs, and driven by consumer electronics Pipeline ADC is expected to be a key ADC architecture in future applications The development of new design techniques for high speed, low voltage and low power ADCs is crucial to stay on the future applications roadmap Texas A&M University 8 Spring, 2019
Multi-standard Wireless Systems Multiple services Reuse circuits as much as possible Power Area Competitiveness Smaller Cell phone, stronger function, longer battery duration Use of digital (analog unfriendly) nanometric tecnologies Texas A&M University 9 Spring, 2019
Super-heterodyne Receiver Invented by Armstrong in 1918 Hardware specific radio architecture Extensive filtering to relax ADC specs Suitable for narrow-band applications Texas A&M University 10 Spring, 2019
Design issues for multi-standard solutions Limited by flicker noise Not flexible Hardware intensive Excessive power at the front-end (Linearity issues) Extensive down conversions: LO and mixers increase both noise and power consumption Extensive filtering: Area, Power and Noise issues Not fully compatible for the Telecoms roadmap Texas A&M University 11 Spring, 2019
Current Multi-standard designs Antenna RF (1-2 GHz) Receiver for standard 1 IF (100-200 MHz) Minimum sharing of blocks BPF LNA VGA BPF LO1 LO2 Area and power consumption overhead RF Switch RF (1-2 GHz) Receiver for standard 2 BPF LNA VGA BPF LO1 IF (100-200 MHz) LO2 Not Flexible at all Limited number of standards can be accommodated Texas A&M University 12 Spring, 2019
Efficient radio transceiver: Direct Conversion Antenna Frequency Synthesizer 16-Channel Multiband Digital Receiver RF signal Antenna IF Filter 1 RF Filter 1 LNA & VGA Mixer 80 MHz ADC 1 Optional 4- channel digital receiver 4- channel digital receiver Software Platform DSP RF signal RF Filter 2 LNA & VGA Mixer IF Filter 2 ADC 2 4- channel digital receiver or FPGAs 4- channel digital receiver Direct conversion + broadband ADC (1 receiver per service) Lowpass filter is required (~ 50-100 mw) 13-14 bits 80 MHz Lowpass ADC (500 mw from ADI) Bank of receivers, filters and ADCs Texas A&M University 13 Spring, 2019
Roadmap for high-resolution Receivers How much RF processing should be done before the ADC? The front-end must be scalable and configurable to fit multiple standards Texas A&M University 14 Spring, 2019
15 The single-chip Transceiver Paradigm Modern technologies: Digital intensive System-on- Chip (SOC) environment Scaling of transistor dimensions in digital CMOS technologies Increased intra-die variability from device scaling Defect densities increase in newer technologies Yields decrease as SOC chip sizes increase Yield impact on analog specifications leads to process corner-based overdesign to allow for analog parameter variations Increased test cost Critical Analog components must be minimized M. Onabajo, 2011 Texas A&M University 15 Spring, 2019
Software radio transceiver: Design Issues Makes it sense to have a multi-standard solution based on this architecture? Bandwidth required? Dynamic range required? DTV SNRsignal=25 db; Blockers > 45 db; Crest factor > 20 db LNA+VGA+ADC Dynamic Range over 90 db (practical?) Can you use tracking filters? (back to the past) Texas A&M University 16 Spring, 2019
Ultimate goal: Reality or Dream Concept introduced in 1991 Modulation/demodulation waveforms in software Flexible multi-standard software architecture Texas A&M University 17 Spring, 2019
Texas A&M University 18 Spring, 2019 R. Walden, 1999
Where we were in 99? Where we are? WiMAX Texas A&M University 19 Spring, 2019
Fundamentals on ADCs: Part I Texas A&M University 20 Spring, 2019
A Little bit of History Texas A&M University 21 Spring, 2019
A Little bit of History Texas A&M University 22 Spring, 2019
Jitter and noise limitations on ENOB Texas A&M University 23 Spring, 2019
Data Converters: The main issue The quantized signal presents a finite number of output values that are associated with digital codes Texas A&M University 24 Spring, 2019
What the problem is? Texas A&M University 25 Spring, 2019
Issues: Sampling, Holding and conversion The quantized signal presents a finite number of output values that are associated with digital codes Texas A&M University 26 Spring, 2019
Properties of the Fourier Series Modulation properties Convolution in time Texas A&M University 27 Spring, 2019
Relevant properties of the Fourier Series Product in time Texas A&M University 28 Spring, 2019
Relevant properties of the Fourier Series Texas A&M University 29 Spring, 2019
Additional properties of the Fourier Series Texas A&M University 30 Spring, 2019
Define the problem: Sampling Operation Texas A&M University 31 Spring, 2019
Sampling Operation: Nyquist Rate According to the sampling theorem: If no alias issues, then Ideal sampling does not add distortion but replicas of the original spectrum Texas A&M University 32 Spring, 2019
Signal Sampling Theorem Time domain sampling Frequency Spectrum Texas A&M University 33 Spring, 2019
Signal Sampling employing a train of pulses Time domain sampling with pulses Spectrum Texas A&M University 34 Spring, 2019
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Texas A&M University 36 Spring, 2019 Fundamentals on ADCs: Part I Sampling k s c s s k s FT c s c c s k X T j X T k T t s j S j X j X nt t t x t s t x t x 1 2, 2 2 1 T k s c T s n n j k X T j X z n x e X 1 δ(t-nt) x s (t) t 0 T 2T 3T 4T T x c (t) δ(t-nt)
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Notice in the afore equation that the delay due to exp(-jft) has being ignored In practice, this term corresponds to a signal delay of T/2 seconds! Texas A&M University 38 Spring, 2019
S/H and Quantization errors The sampling and Held operations generate alias frequency components and (sinc) signal distortion, respectively Quantization generates harmonic distortion components when sinusoidal input signals are used Texas A&M University 39 Spring, 2019
VdFundamentals on ADCs: Part I Distortion due to S/H errors VitV tpk0ero t snthe S/H signal can be expressed as: rthe first part of this equation does not generate any distortion since it is a pure sine wave function The error signal is input dependent and non-linear! Fundamental component is at the signal frequency It can be expanded in a Fourier series and then the harmonic components can be found Texas A&M University 40 Spring, 2019
Distortion due to quantization errors: Ramp In general, the quantization error can be expressed as: v vn1 i 2 i in n n ifn1vnt orfor the case of a ramp input signal, then Vin(t)=Kt, then VtKtn i 2 N1tN1V 2 ifn1inifn1ktn N You may want to find the Fourier series that represent this sawtooth error function to find the harmonic distortion components. Texas A&M University 41 Spring, 2019
Texas A&M University 42 Spring, 2019 Fundamentals on ADCs: Part I The problem is more complex for a sine function, the quantization error can be expressed as a kind of frequency modulation function See Van deplassche, pp. 14: Interestingly, this complex expression can be simplified for n-bit converters, leading to a very simple result for the third order harmonic distortion Distortion due to quantization errors: Sinusoidal input oddispiffunctionbesselcomplexaevenispif0apavpp1ppin sin 1n2componentlfundamentaofPowercomponentharmonicrd3ofPower3HDn51.
1.5 HD3Fundamentals on ADCs: Part I Distortion due to quantization errors: Sinusoidal inputn 2 For 10-Bit ADC, HD3 is in the range of -90.31 db HD3 reduces at a rate of -9dB per additional Bit After 10 bits, this distortion can be easily ignored Texas A&M University 43 Spring, 2019
IMFundamentals on ADCs: Part I Distortion due to quantization errors: Sinusoidal input For the case of intermodulation distortion using a couple of test tones, it is found 32 Notice that SNR is over 20dB more relevant than HD3 for n>=7n2texas A&M University 44 Spring, 2019
Alias issue if undersampling Texas A&M University 45 Spring, 2019
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Under-sampling of a broadband signal Texas A&M University 47 Spring, 2019
SinFundamentals on ADCs: Part I S/H and Quantization errors The sampling and Held operations generate alias frequency components and (sinc) signal distortion, respectively Error is an odd function (no even harmonic distortions, why?) Quantization generates harmonic distortion components when sinusoidal input signals are used StE ro tq trerror signal Quantized signal Freq Freq Texas A&M University 48 Spring, 2019
Distortion due to quantization errors Texas A&M University 49 Spring, 2019
ADC metrics: Quantization error Signal is sampled at given instants Signal is encoded to a limited number of codes resulting in quantization noise (random signals) and distortion (periodic signals) Texas A&M University 50 Spring, 2019
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What the fundamental problem is? Mapping an infinite resolution analog signal into a digital but finite resolution representation Texas A&M University 52 Spring, 2019
Quantization noise for Random (Ramp) input signal Texas A&M University 53 Spring, 2019
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SQNR ADC metrics: SQNR The maximum Signal-to-Quantization Noise ratio (SQNR) for an N-bit ADC: P P A P / 2 N 2 2 / 2 6. 02N 1. db 2 signal ideal noise noise 2 / 12 76 For an ADC with a measured SNDR, the effective number of bits is defined as: ENOB SNDR(dB) 6.02 1.76 Texas A&M University 55 Spring, 2019
Quantization noise density The dynamic range of a system is equal to the signal to noise ratio measured over a bandwidth equal to half of the sampling (Nyquist) frequency q22then, 12Is the total while the quantization noise density (quantization noise measured in a bandwidth of 1 22q2Noisedensity f 6fsHz)s-fs/2 fs/2 Texas A&M University 56 Spring, 2019
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Practical Limitations Texas A&M University 61 Spring, 2019
Digital to Analog Converters Texas A&M University 62 Spring, 2019
Practical Definitions Texas A&M University 63 Spring, 2019
Practical Limitations Texas A&M University 64 Spring, 2019
Practical Limitations Quite critical issue! Usually not a major issue Texas A&M University 65 Spring, 2019
Practical Limitations: Offset error Texas A&M University 66 Spring, 2019
Practical Limitations Usually not a major issue Quite critical issue! Texas A&M University 67 Spring, 2019
Practical Limitations: Gain error Texas A&M University 68 Spring, 2019
Practical Limitations: Differential Error Texas A&M University 69 Spring, 2019
Practical Limitations Texas A&M University 70 Spring, 2019
Practical Limitations: Integral error Texas A&M University 71 Spring, 2019
Practical Limitations Texas A&M University 72 Spring, 2019
Practical Limitations: Absolute Accuracy Texas A&M University 73 Spring, 2019
Analog to Digital Converters Usually the effects of the systematic offsets can be minimized through calibration or accounted in digital domain Texas A&M University 74 Spring, 2019
Digital to Analog Converters Texas A&M University 75 Spring, 2019
Practical Limitations Texas A&M University 76 Spring, 2019
Practical Limitations Texas A&M University 77 Spring, 2019
Practical Limitations DNL must be smaller or equal to 1 LSB Texas A&M University 78 Spring, 2019
Practical Limitations Texas A&M University 79 Spring, 2019
Offset Voltages Texas A&M University 80 Spring, 2019
Practical Limitations Texas A&M University 81 Spring, 2019
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