l Logic-Level Gate Drive l Advanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 75 C Operating Temperature l Fast Switching l Fully Avalanche Rated l Lead-Free Description Fifth Generation HEXFET power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. G PD - 95575 IRL004SPbF IRL004LPbF HEXFET Power MOSFET D S V DSS = 40V R DS(on) = 0.0065Ω I D = 30A The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRL004L) is available for lowprofile application. D 2 Pak IRL004S TO-262 IRL004L Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ 0V 30 I D @ T C = 00 C Continuous Drain Current, V GS @ 0V 92 A I DM Pulsed Drain Current 520 P D @T A = 25 C Power Dissipation 3.8 W P D @T C = 25 C Power Dissipation 200 W Linear Derating Factor.3 W/ C V GS Gate-to-Source Voltage ± 6 V E AS Single Pulse Avalanche Energy 700 mj I AR Avalanche Current 78 A E AR Repetitive Avalanche Energy 20 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 R θja Junction-to-Ambient ( PCB Mounted,steady-state)* 40 C/W www.irf.com 07/9/04
Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 40 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.04 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 0.0065 V GS = 0V, I D = 78A Ω 0.009 V GS = 4.5V, I D = 65A V GS(th) Gate Threshold Voltage.0 V V DS = V GS, I D = 250µA g fs Forward Transconductance 63 S V DS = 25V, I D = 78A I DSS Drain-to-Source Leakage Current 25 V µa DS = 40V, V GS = 0V 250 V DS = 32V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 00 V GS = 6V na Gate-to-Source Reverse Leakage -00 V GS = -6V Q g Total Gate Charge 00 I D = 78A Q gs Gate-to-Source Charge 32 nc V DS = 32V Q gd Gate-to-Drain ("Miller") Charge 43 V GS = 4.5V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 6 V DD = 20V, t r Rise Time 20 I D = 78A, t d(off) Turn-Off Delay Time 25 ns R G = 2.5Ω, t f Fall Time 4 R D = 0.8Ω, See Fig. 0 L S Internal Source Inductance 7.5 nh Between lead, and center of die contact C iss Input Capacitance 5330 V GS = 0V C oss Output Capacitance 480 pf V DS = 25V C rss Reverse Transfer Capacitance 320 ƒ =.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 30 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 520 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 78A, V GS = 0V t rr Reverse Recovery Time 78 20 ns T J = 25 C, I F = 78A Q rr Reverse RecoveryCharge 80 270 nc di/dt = 00A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ) Starting T J = 25 C, L = 0.23mH R G = 25Ω, I AS = 78A. (See Figure 2) ƒ I SD 78A, di/dt 370A/µs, V DD V (BR)DSS, T J 75 C Pulse width 300µs; duty cycle 2%. * When mounted on " square PCB ( FR-4 or G-0 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. Calculated continuous current based on maximum allowable junction temperature; for recommended current-handing of the package refer to Design Tip # 93-4 Uses IRL004 data and test conditions 2 www.irf.com
0000 I D, Drain-to-Source Current (A) 000 00 0 VGS TOP 5V 0V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 2.7V 2.7V 20µs PULSE WIDTH 0. T J = 25 C 0. 0 00 V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current (A) 000 00 0 VGS TOP 5V 0V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 2.7V 2.7V 20µs PULSE WIDTH T J = 75 C 0. 0 00 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 000 00 0 T J = 25 C T J = 75 C V DS= 50V 20µs PULSE WIDTH 0. 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.5 I D = 30A 2.0.5.0 0.5 V GS= 0V 0.0-60 -40-20 0 20 40 60 80 00 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance (pf) 0000 VGS = 0V, f = MHz Ciss = Cgs Cgd, C ds SHORTED Crss = Cgd 8000 Coss = Cds Cgd C iss 6000 C oss 4000 2000 C rss 0 0 00 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 2 0 8 6 4 2 I = D 78 A V DS = 32V V DS = 20V FOR TEST CIRCUIT SEE FIGURE 3 0 0 30 60 90 20 50 80 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 000 00 0 T J = 75 C T J = 25 C V GS = 0 V 0. 0.0 0.5.0.5 2.0 2.5 3.0 V SD,Source-to-Drain Voltage (V) 0000 I D, Drain Current (A) 000 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) 0us 00us ms 0ms TC = 25 C TJ = 75 C Single Pulse 0 00 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
40 20 LIMITED BY PACKAGE V GS V DS R D D.U.T. I D, Drain Current (A) 00 80 60 40 R G 0V Pulse Width µs Duty Factor 0. % Fig 0a. Switching Time Test Circuit - V DD 20 V DS 90% 0 25 50 75 00 25 50 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0.0 0.05 t 0.02 SINGLE PULSE t2 0.0 (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC 0.0 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
L V DS D.U.T. R G V - DD 4.5 V I AS t p 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS t p V DD E AS, Single Pulse Avalanche Energy (mj) 800 500 200 900 600 300 TOP BOTTOM I D 32A 55A 78A 0 25 50 75 00 25 50 75 Starting T, Junction Temperature ( J C) V DS Fig 2c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 2b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 4.5 V Q GS Q G Q GD 2V.2µF 50KΩ.3µF D.U.T. V - DS V G V GS 3mA Charge Fig 3a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-channel HEXFET Power MOSFETs www.irf.com 7
D 2 Pak Package Outline Dimensions are shown in millimeters (inches) D 2 Pak Part Marking Information THIS IS AN IR F530S WITH LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" Note: "P" in ass embly line position indicates "Lead-Free" OR INT ERNATIONAL RECTIFIER LOGO ASS EMBLY LOT CODE F530S PART NUMBER DATE CODE YE AR 0 = 2000 WEEK 02 LINE L INT ERNAT IONAL RECTIFIER LOGO AS S E MB LY LOT CODE F530S PART NUMBER DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 0 = 2000 WEEK 02 A = ASSEMBLY SITE CODE 8 www.irf.com
TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL303L LOT CODE 789 ASSEMBLED ON WW 9, 997 IN THE AS SEMBLY LINE "C" Note: "P" in assembly line pos ition indicates "L ead-f ree" OR INTERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C INT ERNAT IONAL RECTIFIER LOGO AS S EMBL Y LOT CODE PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 997 WEEK 9 A = ASSEMBLY SITE CODE www.irf.com 9
D 2 Pak Tape & Reel Information Dimensions are shown in millimeters (inches) TRR.60 (.063).50 (.059) 4.0 (.6) 3.90 (.53).60 (.063).50 (.059) 0.368 (.045) 0.342 (.035) FEED DIRECTION TRL.85 (.073).65 (.065) 0.90 (.429) 0.70 (.42).60 (.457).40 (.449) 6.0 (.634) 5.90 (.626).75 (.069).25 (.049) 5.42 (.609) 5.22 (.60) 24.30 (.957) 23.90 (.94) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.50 (.532) 2.80 (.504) 27.40 (.079) 23.90 (.94) 4 330.00 (4.73) MAX. 60.00 (2.362) MIN. NOTES :. COMFORMS TO EIA-48. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (.039) 24.40 (.96) 3 30.40 (.97) MAX. 4 Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) 252-705 TAC Fax: (30) 252-7903 Visit us at www.irf.com for sales contact information. 07/04 0 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/