DYNAMICALLY RECONFIGURABLE PWM CONTROLLER FOR THREE PHASE VOLTAGE SOURCE INVERTERS. In this Chapter the SPWM and SVPWM controllers are designed and

77 Chapter 5 DYNAMICALLY RECONFIGURABLE PWM CONTROLLER FOR THREE PHASE VOLTAGE SOURCE INVERTERS In this Chapter the SPWM and SVPWM controllers are designed and implemented in Dynamic Partial Reconfigurable Hardware (DPRH). In the conventional FPGA design, one control logic can be programmed at a time. In the industrial control, the reconfigurable computing offers an advantage of having more than two architectures in the same FPGA and these architectures are dynamically configured without shutting down the system. Also, the resources are shared during reconfiguration resulting in better usage of FPGA resources. This Chapter brings out the literature of dynamic reconfigurable concepts, Dynamic Partial Reconfiguration (DPR) using Spartan-3 FPGA and the Dynamic Partial Reconfigurable PWM (DPRPWM) controller for VSI. 5.1. Dynamic Reconfiguration in FPGA Dynamic reconfiguration is defined as the selective updation of a subsection or the entire FPGA s programmable logic and routing resources while the remainder of the device s programmable resources continues to function without interruption. Dynamic Reconfigurable Hardware (DRH) provides the flexibility of changing digital hardware configurations during application execution. By taking advantage of reconfigurations, hardware can be shared among various applications and upgraded remotely without rebooting. The DRH allows us to modify

78 the target device content without any lengthy procedures such as making changes in the code, code compilation, synthesis and bit stream download into the target device. This feature saves chip area, considerable time and is well suited for unmanned applications such as robotics, continuous process plant and space applications. Fig. 5.1 is a simplified representation of dynamic reconfiguration in progress. Several sub circuits are shown resident on the FPGA array, but only one is to be reconfigured. Fig. 5. 1. Concept of dynamic reconfiguration in FPGA The operation of the appropriate sub circuit is suspended and only the logic cells to be modified are overwritten with new configuration data. The other active sub circuits continue to function during the reconfiguration period. Dynamically reconfigurable FPGAs offer the fastest possible way to change an active FPGA circuit since only the parts that need to be reconfigured are interrupted. This results in faster overall system operation [108-115, 132-134].

79 Dynamic Partial Reconfiguration (DPR) is carried by two design methods called Difference Based (DB) flow and modular based flow. In DB based flow the designer must manually edit low-level changes. Module Design Synthesis of each module Floor planning- modules IOBs and global logic Insert UCF Active module phase- augument UCF with module level timing constraints. NGDBUILD, MAP, PAR, BITGEN and PIMCREATE Design verification using FPGA editor Assembly of entire design Bitstream generation and download into FPGA Fig. 5. 2. Schematic representation of modular based design flow The designer can change the configuration of several kinds of components like look-up-table equations, internal RAM contents, I/O standards, multiplexers, flip-flop initialization and reset values. For complex designs, this flow results inaccurate due to the low-level edition in the bitstream generation. In the module based design, the system is split in to several modules. The configuration bitstream is generated for

80 each module. Some of these modules may be reconfigurable and others fixed. In this work the modular based design is adopted and its design flow is given in Fig. 5. 2 [133]. In the partial reconfiguration flow, the modules are routed bus macro. The macro is a hardwired macro which gives communication between the internal reconfigurable modules in the system. The need for DRH in PECs is that it is possible to have two or more PWM controllers, other control algorithms and change the control functions among them without shutting down the FPGA in the system. The advantages in PECs are the single chip implementation of PWM control schemes with reduced resource utilization by sharing the common modules and also the concept can be extended to motor control schemes such as vector control, direct torque control (DTC) and so on. The DRH provides the flexibility of configuring a part of the controller when the rest of the control section is in operation. The DRH can be used in the applications such as PEC control, motor control, position control, robotics and spacecrafts. 5.2. Dynamic Partial Reconfiguration (DPR) using Spartan-3 FPGA In this work, the low cost Spartan-3 FPGA is used to implement the PWM control, therefore, the dynamic partial reconfiguration features in Spartan-3 FPGA is discussed. FPGAs provide an array of logic cells that can be configured to perform a given function by means of a configuration bit stream. In the Xilinx s Virtex and Spartan FPGA

81 families (Spartan II to Spartan IV), the module based and difference based flow are used to perform dynamic partial reconfiguration (DPR) [107-108, 132]. In general, DPR consists of two functional areas which are fixed/static parts and dynamic parts. The dynamic parts are independent parts of the input design that need not be active during the whole application run time. Bus macros are used as fixed data paths for signal communication between the reconfigurable module and other modules. Xilinx provides the Bus Macros and also it can be user developed. In this work, internal Block RAM of FPGA is used to store the generated bit streams through Parallel Configuration Access Port (PCAP) within the FPGA instead of using an embedded processor. Spartan-3 FPGAs support some of the dynamic partial reconfiguration capabilities, but has some limitations compared to Virtex devices. Till now, the lack of ICAP module on pure Spartan-3 FPGAs makes the DPR impossible without using any other additional external devices. Therefore, a portable soft PCAP core is developed using VHDL within the target FPGA, which controls the partial reconfiguration flow through SelectMAP port and supplies configuration clock for reconfiguration. As a result, using the PCAP reduces hardware cost and power consumption of a self reconfigurable system. Partial reconfiguration is possible through either serial JTAG interface or parallel slave SelectMAP mode. Since parallel

82 slave SelectMAP interface has higher performance than the serial JTAG interface, the SelectMAP port is used in this study [108, 132]. The most significant disadvantage of dynamic reconfigurability is the additional complexity in the design cycle and this will probably change in near future. Creating a partial reconfiguration design requires following design flow [133-134]: Design Entry - Development and synthesize HDL code as per partial reconfiguration guidelines. Initial budgeting - Design the floorplan, constrain the logic, and create timing constraints for the top-level design and each module. Run active implementation (NGDBUILD, MAP, PAR,) for each reconfigurable module and each configuration of a particular reconfigurable module. Assembly Phase Implementation: Minimum - Full design (initial power-up configuration). Recommended - Every possible combination of device configurations of fixed and reconfigurable modules for simulation and/or verification Verify design (static timing analysis, functional simulation). Visually inspect design using FPGA Editor to ensure no unexpected routing crosses module boundaries. Though the software enforces this rule, it is still important to manually check this result.

83 Create bitstream for full design (initial power-up configuration). Create individual (or partial) bitstreams for each reconfigurable module. Download the device with initial power-up configuration. Reprogram reconfigurable modules as needed with individual (or partial) bitstreams. 5.3. FPGA Implementation of VLSI Architecture for Dynamic Partially Reconfigurable PWM (DPRPWM) Controller The dynamically reconfigurable hardware architecture consisting of SPWM and SVPWM shown in Fig. 5. 3 is developed using VHDL [124125] and it has three layers which are application domain, platform and circuit implementation. In application domain, the techniques of SPWM and SVPWM are incorporated, and this layer addresses the applications to be configured during run time. The platform layer consists of the internal modules of the modulation schemes like transformations, waveform generation, comparator, clock divider, switching pattern generation and dead time insertion. An additional modulator can also be incorporated in the existing design in which the existing modules need to be configured. The circuit implementation layer is developed and used for the basic circuit realizations [88].

Dynamic part SPWM SVPWM Transformation Sine wave generator Cosine Comparator Sector detection Triangle wave generator Switch pattern generator Clock divider Duty calculator atan Sine Dead time inserter Dynamic part Platform Application Domain 84 qadd qsqrt qmult qsub qmod qsqr qdivide Fig. 5.3. Dynamic partially reconfigurable PWM controller Architecture Static part Circuit Implementation Arithmetic circuits required to formulate the duty calculator function

85 The reconfiguration connections of SPWM and SVPWM are shown by line in Fig. 5. 3 and is implemented using Xilinx Spartan FPGA having 400 K gate density and 100 MHz clock. In this design, resource sharing is the main reconfiguration concept in of SPWM circuit implementation layer. or SVPWM, the application During forms the interconnection of the internal modules in platform layer and, further the internal modules of platform domain realize the circuits available in circuit implementation layer. 5.3.1. Description of the DPRPWM control Design The functional parts are classified as static and dynamic to demonstrate the dynamic partial reconfigurable (DPR) concepts in modulators. The static part comprises of the basic circuit implementations for different arithmetic operations such as addition, subtraction, multiplication, division, squaring and square root which are realized using fixed point realizations, i.e. Q-Format realizations [28-32, 95, 107]. Dynamic part consists of two levels of dynamic partial reconfigurable modules. First part is functional level DPR module which consists of the internal functional modules of SPWM and SVPWM. The major functional units are transformations, wave generation (sine and triangle), trigonometric functional units (atan, sine and cosine), comparator, sector detection, clock divider, duty calculator and PWM pattern generator. Second dynamic part is an application level to activate either SPWM or

86 SVPWM. The bit streams for the DPR modules are stored in BlockRAM of FPGA. The bit stream generation process consists of generating bit streams for all individual functional units and for application units. In some DPR application, external memory is employed to store the generated bit streams using an external controller or processor for accessing and controlling the bit streams. 5.3.2. Reconfiguration of DPRPWM Control When the SPWM is configured by bit streams, the components in the platform are configured as shown Fig 5.3. The digital implementation structure of SPWM is described in Fig. 5.4 and the internal modules of SVPWM are shown in shown in Fig. 5.5. The corresponding SVPWM modules are reconfigured when its bit stream is loaded. According to the performance requirement, either SPWM or SVPWM will be reconfigured automatically using PCAP controller. In the automatic environment, for example, a low harmonic performance requirement, the control signal in PCAP enables the reconfiguration of application level as SVPWM and thereby enables the corresponding functional units to realize the SVPWM in the platform domain. For realizing SVPWM, the bit streams are transferred from BlockRAM to dynamic part and functional units such as transform for converting the three phase parameters to two phase parameters, sector detector for detecting the sectors using the phase angle and magnitude parameter from transform unit are included. The duty calculator calculates the different duty periods using required

87 parameters from sector detection and trigonometric unit. The pattern generation unit generates the switch patterns using the duty periods, the dead time insertion unit inserts the dead/dwell time in the generated switch/pwm patterns. Fig. 5. 6. Shows the functional flow chart of DPRPWM controller. clk Reset s1 Sine wave generator s3 Comparator and dead time inserter Triangle wave generator s5 s4 s6 s2 Fig. 5.4. Digital implementation of SPWM Sector detection Va Vb Vc 3-2 co-ordinate converter Vdc Sin/cos PWM Generation and Dead Time inserter Duty calculator Ts Td Fig. 5.5. Digital implementation of SVPWM P1 P3 P5 P4 P6 P2

88 Start Read the bit streams Is SPWM is selected Yes No Load the bit streams for SPPWM modules Load the bit streams for SVPWM modules Modules for SPWM are configured Modules for SVPWM are configured Check for new bit streams Fig. 5. 6. Functional flow chart of DPRPWM controller 5.3.3. Internal modules of SPWM and SVPWM Since most of the modules for PEC control are basic arithmetic computations, comparator, sine wave generations and its development is presented. The internal modules of SPWM and SVPWM and their implementations are presented in Chapter 3 and 4 respectively.

89 5.3.4. Reconfiguration Time Calculation The main performance of dynamic reconfigurable architectures is reconfiguration time. The time taken by full and partial reconfiguration in Spartan 3 FPGA is given as: Tfull-config=Sconfig/Frecon (5.1) where, Sconfig is the total configuration size in bytes of the FPGA and Frecon is the reconfiguration frequency in bytes per second. Tpart-config=Qcolumns * Sconfig/Frecon (5.2) where Sconfig in this case is determined by Sconfig= Nframes * Llength The time taken by full and partial reconfiguration in Spartan 3 FPGA is calculated using the equations (5. 1) and (5. 2) In this implementation, the DPR is used in FPGA, particularly XC3S400 FPGA having 767 frames and each frame has 2208 bits, 3584 slices, in an array of 32 rows by 28 columns [108-109, 132-133]. On average, 1 CLB column=3584/28=128 slices. The design takes approximately 734 slices for SVPWM and 737 slices for SPWM, therefore, a minimum of (734/128=6, 737/128=6) 6 columns are required. The required buffer space needed is calculated as follows: For partial reconfiguration, Sconfig-partial = 6 * 2208= 13212 bytes. For full reconfiguration, Sconfig-full = 28 * 2208= 61824 bytes. The partial configuration time for one column is, (13212 /50 MHz) = 0.2642 ms. Therefore, the partial configuration time for 6 columns is,

90 Tpart-config = 6 * 0.2642= 1.58544 ms. The full reconfiguration time for one column is, (61824 /50 MHz) = 1.23648 ms. The full reconfiguration time is, Tfull-config=Sconfig/Frecon = (28*61824)/50MHz=34.62144 ms. From the analysis, for a 50 MHz clock, it is noted that there is a significant decrease in the time taken for partial reconfiguration (1.58544 ms i.e. 4.57% of full reconfiguration time) when compared to full reconfiguration time (34.62144 ms). The Tpart-config will be still less for increased frequency. Therefore, for fault tolerant control applications, the frequency should be high to reduce the Trecon. 5.4. Implementation of the DPRPWM Controller This section presents the design and development of DPRPWM controller for three phase VSI in a single Xilinx Spartan 3 XCS400PQ208 FPGA. The DPRPWM controller is designed such that it switches over between the popular pulse width modulation techniques like SPWM and SVPWM. FPGA platform supports the run-time reconfiguration of control functions and algorithms directly in hardware and meets hard real-time performance criteria in terms of timings for PWM generation as well as reconfiguration. The DPRPWM control is simulated and experimentally verified using a low cost Xilinx Spartan-3 FPGA. The results of SPWM and SVPWM controller are presented.

91 5.4.1. Simulation Results The individual SPWM and SVPWM controllers are designed and simulated using ModelSim and Xilinx simulators. The DRH PWM control is implemented using Xilinx PlanAhead available in Xilinx ISE 11.1i. 5.4.1.1. Simulation Results of Individual SPWM and SVPWM Modulators The SPWM and SVPWM modulators are synthesized using Xilinx 11.1i. The implementation report of the designed SPWM and SVPWM modulators are given in Table 3.1 and Table 4. 1 respectively. The ModelSim 5.7 and Xilinx simulator has been used for simulation of the SPWM and SVPWM modulator with different fs and fo. In DRH implementation of PWM for combined SPWM and SVPWM control, Xilinx PlanAhead is used [133-134]. Fig. 5. 7. Three phase SPWM wave forms: f0 = 50 Hz and fs = 1.157 khz. The SPWM waveform with fs of 1.157 khz and fo of 50 Hz is shown in Fig. 5. 7. The resource utilization of individual modules of SPWM and

92 SVPWM are given in Fig. 5. 8 and Fig. 5. 9 respectively. The SVPWM waves with fs of 20 khz, fo of 50 Hz is shown in Fig. 5. 10 1200 1000 800 No. of 4 input LUTs No.of Slices 600 400 200 0 Sin Generato r Tri generato r Clo ck divide QA LU P WM dead time Fig. 5. 8. Resource utilization of individual modules in SPWM 1200 1000 800 No. of 4 input LUTs No.of Slices 600 400 200 0 3/2 transfo rm Secto r find Switch pattern QA LU Duty calculato r Fig. 5. 9. Resource utilization of individual modules in SVPWM Fig. 5. 10. SVPWM waveforms in 6 sector: fo = 50 Hz and fs = 20 khz

93 5.4.1.2. Simulation Results of DPRPWM control The first step is the development and synthesis of the internal modules of the SPWM and SVPWM controllers as static part of the system. The DPR design flow is discussed in Section 5.1. The modular based DPR design is implemented using Xilinx PlanAhead [133-134]. The simulation results of SVPWM reconfiguration is shown in Fig. 5.11 and Fig. 5.12. In simulation, the reconfiguration time is 2 ns when 100 MHz system clock is used and reconfiguration time depends on the clock frequency. The DPR PWM can be extended to the fault tolerant control systems. The schematic of the DRH PWM design is shown in Fig. 5.13 to Fig. 5.15 and the floorplan is shown in Fig. 5.16. Reconfiguration to SVPWM Fig. 5.11. Simulation result of DPRPWM controller

94 Reconfiguration to SVPWM Fig. 5.12. Simulation result of DPRPWM controller (Expanded scale) Fig. 5.13. Schematic of DRH PWM controller with bus macro

95 Fig. 5.14. Schematic of DRH PWM controller with PWM output signal part Fig. 5.15. Schematic of DRH PWM controller showing the internal logics

96 Fig. 5.16. Floorplan of DRHPWM controller 5.4.2. Experimental Results The DPR PWM control has been implemented in Xilinx- Spartan 3 XCS400PQ208 FPGA. The DRH for PWM control for three phase VSIs using the FPGA is shown Fig. 5.17 and the experimental setup consists of FPGA, driver, three phase VSI and an induction motor load (0.18kW, 415V, 50 Hz and 0.75kW, 415V, 50 Hz). The experimentation is carried out with the initial setting of SPWM in light load with reduced motor voltage of 150 Volts line to line. The results of line to line voltage, voltage harmonics and current for the different frequencies are verified. The SPWM signals, the inverter output voltage (line to line), voltage harmonic

97 spectrum and line current are shown in Fig. 5.18 to Fig. 5.21 respectively. FPGA Induction motor Power module Speed sensor Current sensor Driver circuit Fig. 5.17. Experimental setup of FPGA based DRHPWM controller fed induction motor drive The PWM output waveform is verified in the experiment with different fs up to 15 khz. The THD is measured using Fluke power quality analyzer. The voltage waveform has a THD of 16.6% when the fo is 30 Hz and the fs is 10.42 khz and the THD is reduced when the fs as well as the fundamental is increased. The result shows the practical feasibility of SPWM using DPR hardware in real time. The SVPWM is dynamically reconfigured and tested for different fs, fo and modulation index. The line voltages, voltage harmonic spectrum for different fs, line current are shown in Fig. 5.22 to Fig. 5.25 respectively. The Phase voltage and current wave form with PF angle in the 5.5 kw, 415V, 50 Hz, Three phase induction motor load is shown in Fig. 5. 26 and Fig. 5. 27.

98 The logic utilization is shared in the dynamic reconfigurable PWM control scheme. The logic utilized in SPWM is 737 slices and in SVPWM it is 734. These two modulators are implemented for dynamic reconfiguration between them, therefore, the logic utilization is improved by sharing the commonly modules in the design as described in Section 5.3. The time taken in reconfiguration is evaluated for partial as well as for full reconfiguration and partial reconfiguration took less time compared with full reconfiguration. The simulation results provide the details of the different operating condition such as fs, fo and modulation index of the modulator and are verified in the experiments. The experimental results for different modulator setting such as fs, fo, modulation index, DC bus voltage are verified and the results are acceptable to a practical applications. The line current in SPWM has high frequency harmonics when fo is 50 Hz and fs is 10.42 khz. In SVPWM, the voltage harmonics are with in the limit when the f o is around rated values and fs is above 10 khz. These harmonics can be reduced by increasing the word length in the signal processing (16 bits) and incorporating a suitable dead time control algorithm. The main aim of these experiments is to validate the practical possibility of the DPR control for PWM in real time. The conventional implementation should be implemented in two individual FPGA or by reprogramming the device. In this work, two PWM modulators are loaded in a single FPGA and they are dynamically configured by bit streams. From the simulation and

99 experimental results, the DPR PWM control is verified with different operating conditions such as fs, fo and modulation index with induction motor load. The measured speed is given in Table 5.1. Moreover, DPR is implemented in a low cost Spartan-3 FPGA and reduces the reconfiguration time compared to full reconfiguration. Table 5. 1. Speed of Induction motor drives for different f0 S.No 1 2 3 4 5 6 Fundamental Frequency, fo (Hz) Calculated synchronous speed for 4 pole (RPM) 0.3 3.0 10.0 15.0 30.0 50.0 9 90 300 450 900 1500 Measured speed (RPM) 0.18 kw, 415V, 3 phase No load 8.5 87 296 445 885 1493 Measured speed (RPM) 0.75 kw, 415V, 3 phase No load 7.0 85 292 447 886 1492 Half full load 9 84 277 419 841 1450 Pulse P1 Pulse P5 Fig. 5.18. SPWM wave form in P1 and P4: fs=1.157 khz

100 V / div 100 10 ms / div Fig. 5.19. Inverter output voltage, U R-Y and U Y-B Line to line voltage: f0 = 30 Hz, fs =10.42 khz, M=0.65 Fig. 5.20. Voltage THD: f0=30 Hz, fs = 10.42 khz, and M=0.65. Fig. 5.21. Line current waveforms: f0=50 Hz, fs = 10.42 khz, and M=0.65

101 200 V / div Displacement between two voltage waves 20 ms / div Fig. 5.22. Inverter output voltage, U R-Y and U Y-B Line to line voltage: f0 = 50 Hz, fs =20 khz, and M=0.8 Fig. 5.23. Voltage THD: f0 = 30 Hz, fs =2 khz, and M=0.8 Fig. 5.24. Voltage harmonic spectrum: f0 = 40 Hz, fs =12.28kHz, and M=0.8.

102 Line current 1.8 A rms Fig. 5.25. Three phase current waveforms: f0 = 40 Hz, fs =12.28 khz, and M=0.8 Φ- PF angle Voltage wave form Current wave form Fig. 5.26. R-Phase Voltage and Current wave at fo = 40.25 Hz, fs = 12.28 khz

103 Φ- PF angle Fig. 5.27. B-Phase Voltage and Current wave at fo = 40.25 Hz, fs = 12.28 khz 5.5. Discussions The conventional FPGA implementation, one PWM control can be implemented [64-80]. In this work, two PWM modulators are loaded in a single FPGA and they are dynamically configured by bit streams. From the simulation and experimental results, the DPRPWM control is verified with different operating conditions such as fs, fo and modulation index. Moreover, DPRPWM control is implemented in a low cost Spartan FPGA and reduces the reconfiguration time compared to full reconfiguration. From the SPWM, SVPWM and DPRPWM developed, the comparison of performance measures of Q-Format based SPWM, SVPWM and DPRPWM are given in Table 4.4. The advantages of QALU based PWM controllers consumes less FPGA resources compared to Integer fixed point based

104 PWM controllers. Also, a Q-format based PWM controller provides the single chip implementation, which eliminates the host processor. From the comparison shown in Table 5. 2, it is validated that QALU based PWM controller reduces the FPGA resources and also provides the single chip solutions. Table 5. 2. Comparison of performance of different PWM controller implementations S.N0 Performance Details 8 bit SPWM 8 bit SVPWM 8 bit DPRPWM Conventional SVPWM [89] 1 Device utilization : No. of slices taken by the design 341 737 737 1796 2 Possibility of single chip implementation Possible using QALU Possible using QALU Possible by DPRPWM Not Possible by conventional design 5.6. Conclusion The concept of dynamic reconfiguration has been applied to the inverter control with the PWM schemes of SPWM and SVPWM. The possibility of the practical implementation of DPR for PEC control is experimentally verified with a low cost FPGA from Xilinx. The partial reconfiguration time taken in the design is (1.58544 ms i.e. 4.57% of full reconfiguration time) which less than that of full reconfiguration. The DPR is well suitable for power electronic control compared to full reconfiguration. The capability of DRH is limited to support not only

105 these two techniques, but it can also adopt all major PWM techniques, vector control of AC drives and fault tolerant control by storing all the PWM schemes in the configuration RAM. Also the design can be extended for multilevel and multi phase modulators. This concept has been extensively used in computer vision applications and is to be exploited more for industrial control and power electronic converter and motor control applications.